Revision 1.0
CMOS SRAM
May 1999
K6F4016S4M Family
- 1 -
The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Document Title
256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
0.0
1.0
Remark
Advance
Final
History
Initial Draft
Finalize
- DC characteristics change
I
CC1
: 3mA
4mA
I
CC2
: 30mA
35mA
I
SB1
: 15/1
A(LL/SL)
10/5
A(LL/SL)
I
DR
: 3/1
A(LL/SL, Vcc=1.5V)
3/2
A(LL/SL, Vcc=1.2V)
- 48-CSP package dimension change
Die thickness : 0.32mm
0.45mm
E : 0.80mm
0.93mm
E1 : 0.55mm
0.68mm
- Change V
DR
1.0V to 1.5V
- Change I
DR
test condition ; V
CC
=1.2V to 1.5V
Draft Date
April 2, 1998
May 13, 1999
Revision 1.0
CMOS SRAM
May 1999
K6F4016S4M Family
- 2 -
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Typ.)
Operating
(I
CC1
, Max)
K6F4016S4M-I
Industrial(-40~85
C)
2.4~2.6V
70
1)
/100ns
0.5
A
4mA
48-
BGA
256K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
GENERAL DESCRIPTION
The K6F4016S4M families are fabricated by SAMSUNG
s
advanced full CMOS process technology. The families support
industrial temperature range and 48 ball Chip Scale Package
for user flexibility of system design. The families also support
low data retention voltage for battery back-up operation with
low data retention current.
FEATURES
Process Technology: Full CMOS
Organization: 256K x16 bit
Power Supply Voltage: 2.4~2.6V
Low Data Retention Voltage: 1.5V(Min)
Three state output status and TTL Compatible
Package Type: 48-
BGA-8.20x8.70
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
48-ball CSP - Top View (Ball Down)
LB
OE
A0
A1
A2
N.C
I/O9
UB
A3
A4
CS
I/O1
I/O10
I/O11
A5
A6
I/O2
I/O3
Vss
I/O12
A17
A7
I/O4
Vcc
Vcc
I/O13
N.C
A16
I/O5
Vss
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O16
N.C
A12
A13
WE
I/O8
N.C
A8
A9
A10
A11
N.C
1
2
3
4
5
6
A
B
C
D
E
F
G
H
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice
.
Name
Function
Name
Function
CS
Chip Select Input
Vcc
Power
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
UB
Upper Byte(I/O
9
~
16
)
A
0
~A
17
Address Inputs
LB
Lower Byte(I/O
1
~
8
)
I/O
1
~I/O
16
Data Inputs/Outputs
N.C.
No Connection
Precharge circuit.
Memory array
2048 rows
128
16 columns
I/O Circuit
Column select
Clk gen.
Row
select
WE
OE
UB
CS
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
LB
I/O
9
~I/O
16
Vcc
Vss
Row
Addresses
Control Logic
Column Addresses
Revision 1.0
CMOS SRAM
May 1999
K6F4016S4M Family
- 3 -
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.2 to 3.0V
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 3.6V
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-55 to 150
C
Operating Temperature
T
A
-40 to 85
C
FUNCTIONAL DESCRIPTION
1. X means don
t care. (Must be low or high state)
CS
OE
WE
LB
UB
I/O
1~8
I/O
9~16
Mode
Power
H
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
X
1)
X
1)
X
1)
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
L
X
1)
High-Z
High-Z
Output Disabled
Active
L
H
H
X
1)
L
High-Z
High-Z
Output Disabled
Active
L
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
L
H
L
L
Dout
Dout
Word Read
Active
L
X
1)
L
L
H
Din
High-Z
Lower Byte Write
Active
L
X
1)
L
H
L
High-Z
Din
Upper Byte Write
Active
L
X
1)
L
L
L
Din
Din
Word Write
Active
PRODUCT LIST
Industrial Temperature Products(-40~85
C)
Part Name
Function
K6F4016S4M-ZI70
K6F4016S4M-ZI10
48-
BGA, 70ns, 2.5V
48-
BGA, 100ns, 2.5V
Revision 1.0
CMOS SRAM
May 1999
K6F4016S4M Family
- 4 -
DC AND OPERATING CHARACTERISTICS
1. Super low power product=5
A with special handling
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS=V
IL
, V
IN
=V
IH
or V
IL
-
-
2
mA
Average operating current
I
CC1
Cycle time=1
s, 100%duty,
I
IO
=0mA,
CS
0.2V, V
IN
0.2V or V
IN
V
CC
-0.2V
-
-
4
mA
I
CC2
Cycle time=Min, I
IO
=0mA
,
100% duty,
CS=V
IL,
V
IN
=V
IH
or V
IL
-
-
35
mA
Output low voltage
V
OL
I
OL
= 0.5mA
-
-
0.4
V
Output high voltage
V
OH
I
OL
= -0.5mA
2.0
-
-
V
Standby Current(TTL)
I
SB
CS=V
IH
or LB=UB=V
IH
, Other inputs=V
IH
or V
IL
-
-
0.3
mA
Standby Current (CMOS)
I
SB1
CS
Vcc-0.2V or LB=UB
Vcc-0.2V, CS
0.2V,
Other inputs=0~Vcc
-
0.5
10
1)
A
RECOMMENDED DC OPERATING CONDITIONS
1)
Note :
1. Industrial Product : T
A
=-40 to 85
C, otherwise specified
2. Overshoot : Vcc + 1.0 V in case of pulse width
20ns
3. Undershoot : -1.0 V in case of pulse width
20ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
2.4
2.5
2.6
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.0
-
Vcc+0.2
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
Revision 1.0
CMOS SRAM
May 1999
K6F4016S4M Family
- 5 -
AC CHARACTERISTICS
( T
A
=-40 to 85
C, Vcc=2.4~2.6V )
Parameter List
Symbol
Speed Bins
Units
70ns
100ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
100
-
ns
Address access time
t
AA
-
70
-
100
ns
Chip select to output
t
CO
-
70
-
100
ns
Output enable to valid output
t
OE
-
35
-
50
ns
UB, LB Access Time
t
BA
-
70
-
100
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
UB, LB enable to low-Z output
t
BLZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
25
0
30
ns
UB, LB disable to high-Z output
t
BHZ
0
25
0
30
ns
Output disable to high-Z output
t
OHZ
0
25
0
30
ns
Output hold from address change
t
OH
10
-
15
-
ns
Write
Write cycle time
t
WC
70
-
100
-
ns
Chip select to end of write
t
CW
60
-
80
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
60
-
80
-
ns
UB, LB Valid to End of Write
t
BW
60
-
80
-
ns
Write pulse width
t
WP
55
-
70
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
30
ns
Data to write time overlap
t
DW
30
-
40
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
1. CS
Vcc-0.2V(CS controlled) or LB=UB
Vcc-0.2V, CS
0.2V(LB, UB controlled)
2. Super low power product=2
A with special handling.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
Vcc-0.2V
1)
1.5
-
2.6
V
Data retention current
I
DR
Vcc= 1. 5V, CS
Vcc-0.2V
1)
-
0.5
3
2)
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ns
Recovery time
t
RDR
tRC
-
-
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage : 1.1V
Output load (See right) :C
L
= 100pF+1TTL
C
L
=30pF+1TTL
C
L
1)
1. Including scope and jig capacitance
R
2
2)
R
1
2)
V
TM
3)
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.3V
Revision 1.0
CMOS SRAM
May 1999
K6F4016S4M Family
- 6 -
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB or/and LB=V
IL
)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
t
RC
CS
Address
UB, LB
OE
Data out
t
AA
t
RC
t
OH
t
OH
t
AA
t
CO
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
BHZ
t
HZ
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
Revision 1.0
CMOS SRAM
May 1999
K6F4016S4M Family
- 7 -
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
Data Undefined
UB, LB
WE
Data in
Data out
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS Controlled)
Address
CS
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
t
WC
t
CW(2)
t
WR(4)
t
AW
t
BW
t
WP(1)
t
AS(3)
t
DH
t
DW
t
WHZ
t
OW
t
WC
t
CW(2)
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
High-Z
High-Z
Data Valid
t
AS(3)
Revision 1.0
CMOS SRAM
May 1999
K6F4016S4M Family
- 8 -
Address
CS
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled)
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS going low to end of write.
3.
t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end or write to the address change.
t
WR
applied in case a write ends as CS or WE going high.
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
DATA RETENTION WAVE FORM
CS or LB/UB controlled
V
CC
2.4V
2.0V
V
DR
CS or LB/UB
GND
Data Retention Mode
CS
V
CC
- 0.2V
or LB=UB
Vcc-0.2V
t
SDR
t
RDR
t
AS(3)
Revision 1.0
CMOS SRAM
May 1999
K6F4016S4M Family
- 9 -
PACKAGE DIMENSIONS
6
5
4
3
2
1
A
B
C
D
E
F
G
H
C
/
2
B/2
C
B
B1
C
1
Ball #A1
B
B/2
Elastomer
SRAM Die
C
Ball #A1
C
/
2
Bottom View
Top View
D
E
2
E
1
E
C
Detail A
Side View
0
.
6
8
/
T
y
p
.
0
.
4
5
/
T
y
p
.
0
.
2
5
/
T
y
p
.
A
Y
Elastomer
0.3/Typ.
Die
Detail A
Notes.
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
Min
Typ
Max
A
-
0.75
-
B
8.10
8.20
8.30
B1
-
3.75
-
C
8.60
8.70
8.80
C1
-
5.25
-
D
0.30
0.35
0.40
E
-
0.93
0.94
E1
-
0.68
-
E2
-
0.25
-
Y
-
-
0.08
Unit : millimeter(inch)
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