K6F8008U2M Family

Revision 2.01

January 2002

CMOS SRAM

Document Title

1M x8 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No.

0.0

1.0

2.0

2.01

Remark

Preliminary

Finalize

Final

History

Initial draft

Finalize
- Adopt new code.
- Improve V

, V

OUT

max. on 'ABSOLUTE MAXIMUM RATINGS' from

3.6V to V

+0.5V.

- Improve V

on 'DC AND OPERATING CHARACTERISTICS' from

2.2 to 2.4V.

Revise
- Errata correction
- Improve V

max. on 'RECOMMENDED DC OPERATING CONDI

TIONS' from 0.4V to 0.6V.
- Change t

: from 20ns to 25ns for 55ns product.

from 25ns to 30ns for 70ns product.
- Change t

WHZ

: from 25ns to 20ns for 70ns product.

Revise
- Errata Correction : Changed 256 x8 columns to 512 x8 columns in the
Functional Block Diagram.

Draft Date

August 25, 1999

February 24, 2000

April 26, 2000

January 7, 2002

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.

K6F8008U2M Family

Revision 2.01

January 2002

CMOS SRAM

1M x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM

GENERAL DESCRIPTION

The K6F8008U2M families are fabricated by SAMSUNG

advanced full CMOS process technology. The families support
industrial operating temperature ranges and have chip scale
package for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.

FEATURES

Process Technology: Full CMOS

Organization: 1M x8

Power Supply Voltage: 2.7~3.3V

Low Data Retention Voltage: 1.5V(Min)

Three state output and TTL Compatible

Package Type: 44-TSOP2-400F/R, 48-FBGA-8.00x12.00

Name

Function

Name

Function

, CS

Chip Select Inputs

Address Inputs

Output Enable Input

Vcc

Power

Write Enable Input

Vss

Ground

I/O

~I/O

Data Inputs/Outputs

DNU

Do Not Use

PRO

DUCT FAMILY

1. The parameter is measured with 30pF test load.

Product Family

Operating Temperature

Vcc Range

Speed

Power Dissipation

PKG Type

Standby

SB1

, Typ.)

Operating

CC1

, Max)

K6F8008U2M-F

Industrial(-40~85

2.7~3.3V

/70ns

0.5

3mA

44-TSOP2-400F/R

48-FBGA-8.00x12.00

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTION

Clk gen.

Row
select

I/O

~I/O

Data
cont

Vcc
Vss

Precharge circuit.

Memory array
2048 rows
512

8 columns

I/O Circuit

Column select

CS1

Control Logic

CS2

Row
Addresses

Column Addresses

DNU

CS2

DNU

CS1

DNU

I/O1

DNU

I/O5

Vss

I/O2

A17

I/O6

Vcc

I/O3

A16

I/O7

Vss

I/O4

DNU

A14

A15

DNU

I/O8

DNU

A12

A13

DNU

A18

A10

A11

A19

48-FBGA: Top View (Ball Down)

CS1

DNU

I/O1

I/O2

Vcc

Vss

I/O3

I/O4

DNU

A19

A18

A17

A16

CS2

DNU

I/O8

I/O7

Vss

Vcc

I/O6

I/O5

DNU

A10

A11

A12

44-TSOP2

Forward

44-TSOP2

Reverse

CS2

DNU

I/O8

I/O7

Vss

Vcc

I/O6

I/O5

DNU

A10

A11

A12

A13

A15

A14

A13

A14

CS1

DNU

I/O1

I/O2

Vcc

Vss

I/O3

I/O4

DNU

A19

A18

A17

A16

A15

K6F8008U2M Family

Revision 2.01

January 2002

CMOS SRAM

PRODUCT LIST

Industrial Temperature Products(-40~85

Part Name

Function

K6F8008U2M-TF55
K6F8008U2M-TF70

K6F8008U2M-RF55
K6F8008U2M-RF70

K6F8008U2M-FF55
K6F8008U2M-FF70

44-TSOP2-F, 55ns, 3.0V
44-TSOP2-F, 70ns, 3.0V
44-TSOP2-R, 55ns, 3.0V
44-TSOP2-R, 70ns, 3.0V

48-FBGA, 55ns, 3.0V
48-FBGA, 70ns, 3.0V

ABSOLUTE MAXIMUM RATINGS

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item

Symbol

Ratings

Unit

Voltage on any pin relative to Vss

, V

OUT

-0.2 to V

+0.5V

Voltage on Vcc supply relative to Vss

-0.2 to 4.0

Power Dissipation

1.0

Storage temperature

STG

-65 to 150

Operating Temperature

-40 to 85

FUNCTIONAL DESCRIPTION

1. X means don

t care. (Must be low or high state)

I/O

1~8

Mode

Power

High-Z

Deselected

Standby

High-Z

Deselected

Standby

High-Z

Output Disabled

Active

Dout

Read

Active

Din

Write

Active

K6F8008U2M Family

Revision 2.01

January 2002

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS

Note:
1. T

=-40 to 85

C, otherwise specified.

2. Overshoot: V

+2.0V in case of pulse width

20ns.

3. Undershoot: -2.0V in case of pulse width

20ns.

4. Overshoot and undershoot are sampled, not 100% tested.

Item

Symbol

Min

Typ

Max

Unit

Supply voltage

Vcc

2.7

3.0

3.3

Ground

Vss

Input high voltage

2.2

Vcc+0.2

Input low voltage

-0.2

0.6

CAPACITANCE

(f=1MHz, T

=25

1. Capacitance is sampled, not 100% tested

Item

Symbol

Test Condition

Min

Max

Unit

Input capacitance

=0V

Input/Output capacitance

=0V

DC AND OPERATING CHARACTERISTICS

1. Super low power product=10

A with special handling.

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Input leakage current

=Vss to Vcc

-1

Output leakage current

IH,

or OE=V

or WE=V

, V

=Vss to Vcc

-1

Operating power supply current

=0mA, CS

IL,

, WE=V

, V

or V

Average operating current

CC1

Cycle time=1

s, 100%duty, I

=0mA, CS

0.2V,

Vcc-0.2V, V

0.2V or V

VCC-0.2V

CC2

Cycle time=Min, I

=0mA, 100% duty,

, CS

IH,

VIN=V

or V

Output low voltage

= 2.1mA

0.4

Output high voltage

= -1.0mA

2.4

Standby Current(TTL)

, CS

, Other inputs=V

or V

0.3

Standby Current(CMOS)

SB1

Vcc-0.2V, CS

Vcc-0.2V(CS

controlled) or

0.2V(CS

controlled), Other inputs=0~Vcc

0.5

K6F8008U2M Family

Revision 2.01

January 2002

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS

(Test Load and Input/Output Reference)

Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C

=100pF+1TTL

=30pF+1TTL

DATA RETENTION CHARACTERISTICS

Vcc-0.2V,CS

Vcc-0.2V(CS

controlled) or CS

Vcc-0.2V(CS

controlled).

2. Super low power product=4

A with special handling.

Item

Symbol

Test Condition

Min

Typ

Max

Unit

Vcc for data retention

Vcc-0.2V

1.5

3.3

Data retention current

Vcc=1.5V, CS

Vcc-0.2V

0.5

Data retention set-up time

SDR

See data retention waveform

Recovery time

RDR

tRC

AC CHARACTERISTICS

(Vcc=2.7~3.3V, Industrial product: T

=-40 to 85

Parameter List

Symbol

Speed Bins

Units

55ns

70ns

Min

Max

Min

Max

Read

Read Cycle Time

Address Access Time

Chip Select to Output

Output Enable to Valid Output

Chip Select to Low-Z Output

Output Enable to Low-Z Output

OLZ

Chip Disable to High-Z Output

Output Disable to High-Z Output

OHZ

Output Hold from Address Change

Write

Write Cycle Time

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time

Write to Output High-Z

WHZ

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

1. Including scope and jig capacitance

2. R

=3070

=3150

3. V

=2.8V

K6F8008U2M Family

Revision 2.01

January 2002

CMOS SRAM

Address

Data Out

Previous Data Valid

Data Valid

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1)

(Address Controlled

CS1=OE=V

, CS2=WE=V

)

TIMING WAVEFORM OF READ CYCLE(2)

(WE=V

)

Data Valid

High-Z

Address

Data out

NOTES (READ CYCLE)

and

OHZ

are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition,

(Max.) is less than

(Min.) both for a given device and from device to device

interconnection.

OLZ

OHZ

HZ(1,2)

CO2

CO1

K6F8008U2M Family

Revision 2.01

January 2002

CMOS SRAM

DATA RETENTION WAVE FORM

controlled

2.7V

2.2V

GND

Data Retention Mode

- 0.2V

SDR

RDR

TIMING WAVEFORM OF WRITE CYCLE(3)

(CS

Controlled)

Address

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS

, a high CS

and a low WE. A write begins at the latest transition among CS

goes low,

going high and WE going low : A write end at the earliest transition among CS

going high, CS

going low and WE going high,

is measured from the begining of write to the end of write.

2. t

is measured from the CS

going low or CS

going high to the end of write.

3. t

is measured from the address valid to the beginning of write.

4. t

is measured from the end of write to the address change. t

applied in case a write ends as CS

or WE going high t

WR2

applied

in case a write ends as CS

going to low.

CW(2)

Data in

Data Valid

Data out

High-Z

CW(2)

WR(4)

WP(1)

AS(3)

controlled

2.7V

0.4V

GND

Data Retention Mode

SDR

RDR

0.2V

K6F8008U2M Family

Revision 2.01

January 2002

CMOS SRAM

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

Unit: millimeters(inches)

.
0

#22

#44

#23

0.35

0.10

0.014

0.004

0.80

0.0315

I
N

0.047

1.20

MAX.

0.741

18.81

MAX.

18.41

0.10

0.725

0.004

11.76

0.20

0.463

0.008

+ 0.

- 0.0

0.50

+ 0.0

- 0.

002

0.15

0.00

0.020

.
1

.
4

0.10

0.004

PACKAGE DIMENSIONS

0~8

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

( )

0.805

0.032

( )

MAX

1.00

0.10

0.039

0.004

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)

.
0

#22

#44

#23

0.35

0.10

0.014

0.004

0.80

0.0315

I
N

0.047

1.20

MAX.

0.741

18.81

MAX.

18.41

0.10

0.725

0.004

11.76

0.20

0.463

0.008

+ 0

.10

- 0.0

0.50

+ 0.0

- 0.0

0.15

0.00

0.020

.
1

.
4

0.10

0.004

0~8

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

( )

0.805
0.032

( )

MAX

1.00

0.10

0.039

0.004

K6F8008U2M Family

Revision 2.01

January 2002

CMOS SRAM

/
2

PACKAGE DIMENSION

B/2

Bottom View

Top View

Side View

.
8

/
T

.
2

/
T

Detail A

Min

Typ

Max

0.75

7.90

8.00

8.10

3.75

11.90

12.00

12.10

5.25

0.30

0.35

0.40

1.10

1.20

0.85

0.20

0.25

0.30

0.08

0.50

#A1

.
3

A1 INDEX MARK

Notes.

1. Bump counts: 48(8 row x 6 column)

2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

4. Typ: Typical

5. Y is coplanarity: 0.08(Max)

Unit: millimeters

48 BALL FINE PITCH BGA(0.75mm ball pitch)

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K6F8008U2M-TF55