PRELIMINARY
Revision 2.0
- 1 -
June 2002
PRELIMINARY
K6R1004V1D
CMOS SRAM
for AT&T
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 1.0
Rev. 2.0
Remark
Preliminary
Preliminary
Preliminary
Final
Final
History
Initial document.
Speed bin modify
Current modify
1. Final datasheet release
2. Delete 12ns speed bin.
3. Change Icc for Industrial mode.
1. Delete UB,LB releated timing diagram.
Item
Previous
Current
I
CC(Industrial)
8ns
100mA
90mA
10ns
85mA
75mA
Draft Data
May. 11. 2001
June. 18. 2001
September. 9. 2001
December. 18. 2001
June. 19. 2002
PRELIMINARY
Revision 2.0
- 2 -
June 2002
PRELIMINARY
K6R1004V1D
CMOS SRAM
for AT&T
1Mb Async. Fast SRAM Ordering Information
Org.
Part Number
VDD(V)
Speed ( ns )
PKG
Temp. & Power
256K x4
K6R1004C1D-JC(I) 10/12
5
10/12
J : 32-SOJ
C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
K6R1004V1D-JC(I) 08/10
3.3
8/10
128K x8
K6R1008C1D-J(T)C(I) 10/12
5
10/12
J : 32-SOJ
T : 32-TSOP2
K6R1008V1D-J(T)C(I) 08/10
3.3
8/10
64K x16
K6R1016C1D-J(T,E)C(I) 10/12
5
10/12
J : 44-SOJ
T : 44-TSOP2
E : 48-TBGA
K6R1016V1D-J(T,E)C(I) 08/10
3.3
8/10
PRELIMINARY
Revision 2.0
- 3 -
June 2002
PRELIMINARY
K6R1004V1D
CMOS SRAM
for AT&T
256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)
GENERAL DESCRIPTION
FEATURES
Fast Access Time 8,10ns(Max.)
Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R1004V1D-08: 80mA(Max.)
K6R1004V1D-10: 65mA(Max.)
Single 3.3
0.3V Power Supply
TTL Compatible Inputs and Outputs
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Center Power/Ground Pin Configuration
Standard Pin Configuration :
K6R1004V1D-J : 32-SOJ-400
Operating in Commercial and Industrial Temperature range.
The K6R1004V1D is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits.
The K6R1004V1D uses 4 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using
SAMSUNG
s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1004V1D is packaged in a 400 mil 32-pin plastic SOJ.
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
17
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O
1
~ I/O
4
Data Inputs/Outputs
V
CC
Power(+3.3V)
V
SS
Ground
N.C
No Connection
PIN CONFIGURATION
(Top View)
Clk Gen.
I/O
1
~ I/O
4
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
R
o
w
S
e
l
e
c
t
Data
Cont.
Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
512x4 Columns
I/O Circuit &
SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
17
A
16
A
15
A
14
A
13
OE
I/O
4
Vss
Vcc
I/O
3
A
12
A
11
A
10
A
9
A
8
N.C
N.C
A
0
A
1
A
2
A
3
CS
I/O
1
Vcc
Vss
I/O
2
WE
A
4
A
5
A
6
A
7
N.C
A
10
A
11
A
12
A
13
A
14
A
15
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
9
A
16
A
17
A
8
PRELIMINARY
Revision 2.0
- 4 -
June 2002
PRELIMINARY
K6R1004V1D
CMOS SRAM
for AT&T
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70
C)
* V
IL
(Min) = -2.0V a.c (Pulse Width
8ns) for I
20mA.
** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
8ns) for I
20mA.
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
3.0
3.3
3.6
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.0
-
V
CC
+0.3**
V
Input Low Voltage
V
IL
-0.3*
-
0.8
V
CAPACITANCE*
(T
A
=25
C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
C
I/O
V
I/O
=0V
-
8
pF
Input Capacitance
C
IN
V
IN
=0V
-
6
pF
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
,
V
OUT
-0.5 to 4.6
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-0.5 to 4.6
V
Power Dissipation
P
d
1
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
Commercial
T
A
0 to 70
C
Industrial
T
A
-40 to 85
C
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70
C, Vcc=3.3
0.3V, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
IN
=V
SS
to
V
CC
-2
2
A
Output Leakage Current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to
V
CC
-2
2
A
Operating Current
I
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or
V
IL,
I
OUT
=0mA
Com.
8ns
-
80
mA
10ns
-
65
Ind.
8ns
-
90
10ns
-
75
Standby Current
I
SB
Min. Cycle, CS=V
IH
-
20
mA
I
SB1
f=0MHz, CS
V
CC
-0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V
-
5
Output Low Voltage Level
V
OL
I
OL
=8mA
-
0.4
V
Output High Voltage Level
V
OH
I
OH
=-4mA
2.4
-
V
PRELIMINARY
Revision 2.0
- 5 -
June 2002
PRELIMINARY
K6R1004V1D
CMOS SRAM
for AT&T
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
C, V
CC
=3.3
0.3V, unless otherwise noted.)
Output Loads(B)
D
OUT
5pF*
319
353
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+3.3V
* Including Scope and Jig Capacitance
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R1004V1D-08
K6R1004V1D-10
Unit
Min
Max
Min
Max
Read Cycle Time
t
RC
8
-
10
-
ns
Address Access Time
t
AA
-
8
-
10
ns
Chip Select to Output
t
CO
-
8
-
10
ns
Output Enable to Valid Output
t
OE
-
4
-
5
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
4
0
5
ns
Output Disable to High-Z Output
t
OHZ
0
4
0
5
ns
Output Hold from Address Change
t
OH
3
-
3
-
ns
Chip Selection to Power Up Time
t
PU
0
-
0
-
ns
Chip Selection to Power DownTime
t
PD
-
8
-
10
ns
PRELIMINARY
Revision 2.0
- 6 -
June 2002
PRELIMINARY
K6R1004V1D
CMOS SRAM
for AT&T
Address
Data Out
Previous Valid Data
Valid Data
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R1004V1D-08
K6R1004V1D-10
Unit
Min
Max
Min
Max
Write Cycle Time
t
WC
8
-
10
-
ns
Chip Select to End of Write
t
CW
6
-
7
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
6
-
7
-
ns
Write Pulse Width(OE High)
t
WP
6
-
7
-
ns
Write Pulse Width(OE Low)
t
WP1
8
-
10
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
4
0
5
ns
Data to Write Time Overlap
t
DW
4
-
5
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End of Write to Output Low-Z
t
OW
3
-
3
-
ns
Valid Data
High-Z
t
RC
CS
Address
OE
Data out
t
HZ(3,4,5)
t
AA
t
CO
t
OE
t
OLZ
t
LZ(4,5)
t
OHZ
t
PU
t
PD
50%
50%
V
CC
Current
I
CC
I
SB
t
DH
PRELIMINARY
Revision 2.0
- 7 -
June 2002
PRELIMINARY
K6R1004V1D
CMOS SRAM
for AT&T
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
Address
CS
t
WP(2)
t
DW
t
DH
Valid Data
WE
Data in
Data out
t
WC
t
WR(5)
t
AW
t
CW(3)
High-Z(8)
High-Z
OE
t
OHZ(6)
t
AS(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low Fixed)
Address
CS
t
WP1(2)
t
DW
t
DH
t
OW
t
WHZ(6)
Valid Data
WE
Data in
Data out
t
WC
t
AS(4)
t
WR(5)
t
AW
t
CW(3)
(10)
(9)
High-Z(8)
High-Z
PRELIMINARY
Revision 2.0
- 8 -
June 2002
PRELIMINARY
K6R1004V1D
CMOS SRAM
for AT&T
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. t
WP
is measured from the beginning of write to the end of
write.
3. t
CW
is measured from the later of CS going low to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS=Controlled)
Address
CS
t
AW
t
DW
t
DH
Valid Data
WE
Data in
Data out
High-Z
High-Z(8)
t
CW(3)
t
WP(2)
t
AS(4)
t
WC
t
WR(5)
High-Z
High-Z
t
LZ
t
WHZ(6)
FUNCTIONAL DESCRIPTION
* X means Don
t Care.
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
X*
Not Select
High-Z
I
SB
, I
SB1
L
H
H
Output Disable
High-Z
I
CC
L
H
L
Read
D
OUT
I
CC
L
L
X
Write
D
IN
I
CC
PRELIMINARY
Revision 2.0
- 9 -
June 2002
PRELIMINARY
K6R1004V1D
CMOS SRAM
for AT&T
PACKAGE DIMENSIONS
Units:millimeters/Inches
#1
32-SOJ-400
#32
20.95
0.12
0.825
0.005
1
0
.
1
6
0
.
4
0
0
+0.10
MAX
21.36
0.841
0.20
-0.05
+0.004
0.008
-0.002
9.40
0.25
0.370
0.010
MAX
0.148
3.76
MIN
0.69
0.027
1.30
( )
0.051
1.30
( )
0.051
0.95
( )
0.0375
+0.10
0.43
-0.05
+0.004
0.017
-0.002
+0.10
0.71
-0.05
+0.004
0.028
-0.002
1.27
0.050
#16
#17
0.004
0.10
MAX
11.18
0.12
0.440
0.005
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