K6R1016C1D
CMOS SRAM
Revision 1.0
- 1 -
June 2002
PRELIMINARY
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(5.0V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 0.3
Rev. 1.0
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
History
Initial release with Preliminary.
Page 4, DC operation condition modify
Current modify
1. Delete 15ns speed bin.
2. Change Icc for Industrial mode.
1. Final datasheet release.
2. Correct read cycle timing diagram(2).
Item
Previous
Current
I
CC(Industrial)
10ns
85mA
75mA
12ns
75mA
65mA
Draft Data
June. 8. 2001
June. 16. 2001
September. 9. 2001
December. 18.2001
June. 19. 2002
K6R1016C1D
CMOS SRAM
Revision 1.0
- 2 -
June 2002
PRELIMINARY
1Mb Async. Fast SRAM Ordering Information
Org.
Part Number
VDD(V)
Speed ( ns )
PKG
Temp. & Power
256K x4
K6R1004C1D-JC(I) 10/12
5
10/12
J : 32-SOJ
C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
K6R1004V1D-JC(I) 08/10
3.3
8/10
128K x8
K6R1008C1D-J(T)C(I) 10/12
5
10/12
J : 32-SOJ
T : 32-TSOP2
K6R1008V1D-J(T)C(I) 08/10
3.3
8/10
64K x16
K6R1016C1D-J(T,E)C(I) 10/12
5
10/12
J : 44-SOJ
T : 44-TSOP2
E : 48-TBGA
K6R1016V1D-J(T,E)C(I) 08/10
3.3
8/10
K6R1016C1D
CMOS SRAM
Revision 1.0
- 3 -
June 2002
PRELIMINARY
64K x 16 Bit High-Speed CMOS Static RAM
The K6R1016C1D is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
K6R1016C1D uses 16 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control (UB, LB). The device is fabricated
using SAMSUNG
s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1016C1D is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward or 48-TBGA.
GENERAL DESCRIPTION
FEATURES
Fast Access Time 10,12(Max.)
Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R1016C1D-10 : 65mA(Max.)
K6R1016C1D-12 : 55mA(Max.)
Single 5.0V
10% Power Supply
TTL Compatible Inputs and Outputs
I/O Compatible with 3.3V Device
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Center Power/Ground Pin Configuration
Data Byte Control: LB: I/O
1
~ I/O
8
, UB: I/O
9
~ I/O
16
Standard Pin Configuration:
K6R1016C1D-J : 44-SOJ-400
K6R1016C1D-T: 44-TSOP2-400BF
K6R1016C1D-E: 48-TBGA ( 6.0mm X 7.0mm )
with 0.75 ball pitch
Operating in Commercial and Industrial Temperature range.
Clk Gen.
I/O
1
~I/O
8
OE
UB
CS
FUNCTIONAL BLOCK DIAGRAM
R
o
w
S
e
l
e
c
t
Data
Cont.
Column Select
A
10
A
11
A
12
A
13
A
14
A
15
CLK
Gen
.
Pre-Charge Circuit
Memory Array
512 Rows
128x16 Columns
I/O Circuit &
A
0
I/O
9
~I/O
16
Data
Cont.
WE
LB
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
9
A
8
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
15
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
LB
Lower-byte Control(I/O
1
~I/O
8
)
UB
Upper-byte Control(I/O
9
~I/O
16
)
I/O
1
~ I/O
16
Data Inputs/Outputs
V
CC
Power(+5.0V)
V
SS
Ground
N.C
No Connection
K6R1016C1D
CMOS SRAM
Revision 1.0
- 4 -
June 2002
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
,
V
OUT
-0.5 to V
CC
+0.5
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-0.5 to 7.0
V
Power Dissipation
P
d
1
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
Commercial
T
A
0 to 70
C
Industrial
T
A
-40 to 85
C
RECOMMENDED DC OPERATING CONDITIONS*
(TA= to 70
C)
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
8ns) for I
20mA.
*** V
IH
(Max) = V
CC +
2.0V a.c(Pulse Width
8ns) for I
20mA.
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
-
V
CC
+0.5***
V
Input Low Voltage
V
IL
-0.5**
-
0.8
V
LB
OE
A0
A1
A2
N.C
I/O1
UB
A3
A4
CS
I/O9
I/O2
I/O3
A5
A6
I/O11
I/O10
Vss
I/O4
N.C
A7
I/O12
Vcc
Vcc
I/O5
N.C
N.C
I/O13
Vss
I/O7
I/O6
A14
A15
I/O14
I/O15
I/O8
N.C
A12
A13
WE
I/O16
N.C
A8
A9
A10
A11
N.C
1
2
3
4
5
6
A
B
C
D
E
F
G
H
48-TBGA
( Top View )
PIN CONFIGURATION(TOP VIEW)
SOJ/
TSOP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A
15
A
14
A
13
OE
UB
LB
I/O
16
I/O
15
I/O
14
I/O
13
Vss
Vcc
I/O
12
I/O
11
I/O
10
I/O
9
N.C
A
12
A
11
A
10
A
9
N.C
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
I/O
3
I/O
4
Vcc
Vss
I/O
5
I/O
6
I/O
7
I/O
8
WE
A
5
A
6
A
7
A
8
N.C
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
K6R1016C1D
CMOS SRAM
Revision 1.0
- 5 -
June 2002
PRELIMINARY
TEST CONDITIONS*
* The above test conditions are also applied at industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
C, V
CC
=5.0V
10%, unless otherwise noted.)
Output Loads(B)
D
OUT
5pF*
480
255
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5.0V
* Including Scope and Jig Capacitance
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
CAPACITANCE*
(T
A
=25
C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
C
I/O
V
I/O
=0V
-
8
pF
Input Capacitance
C
IN
V
IN
=0V
-
6
pF
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70
C, Vcc=5.0V
10%, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
IN
=V
SS
to
V
CC
-2
2
A
Output Leakage Current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to
V
CC
-2
2
A
Operating Current
I
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or
V
IL,
I
OUT
=0mA
Com.
10ns
-
65
mA
12ns
-
55
Ind.
10ns
-
75
12ns
-
65
Standby Current
I
SB
Min. Cycle, CS=V
IH
-
20
mA
I
SB1
f=0MHz, CS
V
CC
-0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V
-
5
Output Low Voltage Level
V
OL
I
OL
=8mA
-
0.4
V
Output High Voltage Level
V
OH
I
OH
=-4mA
2.4
-
V
K6R1016C1D
CMOS SRAM
Revision 1.0
- 6 -
June 2002
PRELIMINARY
Address
Data Out
Previous Valid Data
Valid Data
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB, LB=V
IL
t
AA
t
RC
t
OH
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R1016C1D-10
K6R1016C1D-12
Unit
Min
Max
Min
Max
Read Cycle Time
t
RC
10
-
12
-
ns
Address Access Time
t
AA
-
10
-
12
ns
Chip Select to Output
t
CO
-
10
-
12
ns
Output Enable to Valid Output
t
OE
-
5
-
6
ns
UB, LB Access Time
t
BA
-
5
-
6
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
ns
UB, LB Enable to Low-Z Output
t
BLZ
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
5
0
6
ns
Output Disable to High-Z Output
t
OHZ
0
5
0
6
ns
UB, LB Disable to High-Z Output
t
BHZ
0
5
0
6
ns
Output Hold from Address Change
t
OH
3
-
3
-
ns
Chip Selection to Power Up Time
t
PU
0
-
0
-
ns
Chip Selection to Power DownTime
t
PD
-
10
-
12
ns
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R1016C1D-10
K6R1016C1D-12
Unit
Min
Max
Min
Max
Write Cycle Time
t
WC
10
-
12
-
ns
Chip Select to End of Write
t
CW
7
-
8
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
7
-
8
-
ns
Write Pulse Width(OE High)
t
WP
7
-
8
-
ns
Write Pulse Width(OE Low)
t
WP1
10
-
12
-
ns
UB, LB Valid to End of Write
t
BW
7
-
8
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
5
0
6
ns
Data to Write Time Overlap
t
DW
5
-
6
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End of Write to Output Low-Z
t
OW
3
-
3
-
ns
K6R1016C1D
CMOS SRAM
Revision 1.0
- 7 -
June 2002
PRELIMINARY
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE =Clock)
Address
CS
UB, LB
WE
Data in
Data out
t
WC
t
CW(3)
t
BW
t
WP(2)
t
AS(4)
t
DH
t
DW
t
OHZ(6)
High-Z
High-Z
Valid Data
OE
t
AW
t
WR(5)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Valid Data
High-Z
t
RC
CS
Address
UB, LB
OE
Data out
t
HZ(3,4,5)
t
AA
t
CO
t
BA
t
OE
t
OLZ
t
LZ(4,5)
t
OHZ
t
BHZ(3,4,5)
t
BLZ(4,5)
t
PU
t
PD
50%
50%
V
CC
Current
I
CC
I
SB
t
DH
K6R1016C1D
CMOS SRAM
Revision 1.0
- 8 -
June 2002
PRELIMINARY
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS=Controlled)
Address
CS
t
AW
t
DW
t
DH
Valid Data
WE
Data in
Data out
High-Z
High-Z(8)
UB, LB
t
CW(3)
t
WP(2)
t
AS(4)
t
WC
t
WR(5)
High-Z
High-Z
t
LZ
t
WHZ(6)
t
BW
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE =Low fixed)
Address
CS
UB, LB
WE
Data in
Data out
t
WC
t
CW(3)
t
BW
t
WP1(2)
t
DH
t
DW
t
WR(5)
t
AS(4)
t
OW
t
WHZ(6)
(10)
(9)
High-Z
Valid Data
t
AW
High-Z
K6R1016C1D
CMOS SRAM
Revision 1.0
- 9 -
June 2002
PRELIMINARY
FUNCTIONAL DESCRIPTION
* X means Don
t Care
.
CS
WE
OE
LB
UB
Mode
I/O Pin
Supply Current
I/O
1
~I/O
8
I/O
9
~I/O
16
H
X
X*
X
X
Not Select
High-Z
High-Z
I
SB
, I
SB1
L
H
H
X
X
Output Disable
High-Z
High-Z
I
CC
L
X
X
H
H
L
H
L
L
H
Read
D
OUT
High-Z
I
CC
H
L
High-Z
D
OUT
L
L
D
OUT
D
OUT
L
L
X
L
H
Write
D
IN
High-Z
I
CC
H
L
High-Z
D
IN
L
L
D
IN
D
IN
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE
going low; A write ends at the earliest transition CS going high or WE going high. t
WP
is measured from the beginning of write
to the end of write.
3. t
CW
is measured from the later of CS going low to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
Address
CS
Valid Data
UB, LB
WE
Data in
Data out
TIMING WAVEFORM OF WRITE CYCLE(4)
(UB, LB Controlled)
t
WC
t
CW(3)
t
BW
t
WP(2)
t
DH
t
DW
t
WR(5)
t
AW
t
AS(4)
High-Z
High-Z(8)
t
BLZ
t
WHZ(6)
High-Z
K6R1016C1D
CMOS SRAM
Revision 1.0
- 10
June 2002
PRELIMINARY
#1
44-SOJ-400
#44
25.58
0.12
1.125
0.005
MAX
28.98
1.141
MAX
0.148
3.76
1.19
( )
0.047
1.27
( )
0.050
0.95
( )
0.0375
+0.10
0.43
-0.05
+0.004
0.017
-0.002
+0.10
0.71
-0.05
+0.004
0.028
-0.002
1.27
0.050
1
0
.
1
6
0
.
4
0
0
+0.10
0.20
-0.05
+0.004
0.008
-0.002
9.40
0.25
0.370
0.010
MIN
0.69
0.027
#22
#23
0.004
0.10
MAX
11.18
0.12
0.440
0.005
PACKAGE DIMENSIONS
Units:millimeters/Inches
1.00
0.10
0.039
0.004
44-TSOP2-400BF
0.002
#1
0.05
#22
#23
0.30
0.012
0.80
0.0315
MIN
0.047
1.20
MAX
0.741
18.81
MAX
18.41
0.10
0.725
0.004
11.76
0.20
0.463
0.008
+ 0.075
- 0.035
0.50
+ 0.003
- 0.001
0.125
0.005
0.020
1
0
.
1
6
0
.
4
0
0
0.10
0.004
0~8
0.45 ~0.75
0.018 ~ 0.030
( )
0.805
0.032
( )
MAX
Units:millimeters/Inches
#44
0.25
0.010
TYP
+
0.10
-
0.05
+
0.004
-
0.002
K6R1016C1D
CMOS SRAM
Revision 1.0
- 11
June 2002
PRELIMINARY
C
1
/
2
PACKAGE DIMENSION
6
5
4
3
2
1
A
B
C
D
E
F
G
H
C
B/2
B
C
1
B
C
Bottom View
Top View
D
E
2
E
1
E
C
Side View
0
.
5
5
/
T
y
p
.
0
.
3
5
/
T
y
p
.
A
Y
Detail A
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
B1
-
3.75
-
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.40
0.45
0.50
E
0.80
0.90
1.00
E1
-
0.55
-
E2
0.30
0.35
0.40
Y
-
-
0.08
B1
#A1
Notes.
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.08(Max)
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)
Unit: millimeters
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