K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 1 -

September 2001

for AT&T

Document Title

64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,

please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev. No.

Rev. 0.0

Rev. 1.0

Rev. 2.0

Rev. 2.1

Rev. 2.2

Rev. 3.0

Rev. 3.1

Rev. 3.2

Rev. 3.3

Rev. 4.0

Remark

Preliminary

Final

History

Initial release with Preliminary.

Release to Final Data Sheet.
1.1. Delete Preliminary.
1.2. Changed DC characteristics.

Added 48-fine pitch BGA.

Changed device part name for FP-BGA.

ex) K6R1016V1C-Z -> K6R1016V1C-F

Changed device ball name for FP-BGA.

1. Added 10ns speed for FP-BGA only.
2. Changed Standby Current.

3. Added Data Retention Characteristics.

Added 10ns speed for all packages(44SOJ / 44TSOP2 / 48FPBGA)

Supply Voltage Change
1. Only 10ns Bin : 3.15V ~ 3.6V
2. The Rest Bin : 3.0V ~ 3.6V

Change

Delete 20ns speed bin

Item

Changed

12ns

85mA

95mA

15ns

83mA

93mA

20ns

80mA

90mA

Item

Changed

Symbol

Changed

I/O1 ~ I/O8

I/O9 ~ I/O16

I/O1 ~ I/O8

Item

Changed

Standby Current(Isb1)

0.3mA

0.5mA

Item

Changed

Min

Max

Min

Max

2.0

+0.5

2.0

+0.3

-0.5

0.8

-0.3

0.8

Draft Data

Aug. 5. 1998

Sep. 7. 1998

Sep. 17. 1998

Nov. 5. 1998

Dec. 10. 1998

Mar. 2. 1999

Apr. 24. 2000

Aug. 25. 2000

Oct. 2. 2000

Sep. 24. 2001

K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 2 -

September 2001

for AT&T

64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)

The K6R1016V1C is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
K6R1016V1C uses 16 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control (UB, LB). The device is fabricated
using SAMSUNG

s advanced CMOS process and designed for

high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1016V1C is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward or 48-Fine pitch BGA.

GENERAL DESCRIPTION

FEATURES

� Fast Access Time 10,12,15ns(Max.)
� Low Power Dissipation
Standby (TTL) : 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
Operating

K6R1016V1C-10: 105 mA(Max.)

K6R1016V1C-12: 95mA(Max.)
K6R1016V1C-15: 93mA(Max.)
� Single 3.3V Power Supply
� TTL Compatible Inputs and Outputs
� Fully Static Operation
- No Clock or Refresh required
� Three State Outputs
� 2V Minimum Data Retention: L-ver. only
� Center Power/Ground Pin Configuration
� Data Byte Control: LB: I/O

~ I/O

, UB: I/O

~ I/O

� Standard Pin Configuration:
K6R1016V1C-J: 44-SOJ-400
K6R1016V1C-T: 44-TSOP2-400BF

K6R1016V1C-F: 48-Fine pitch BGA with 0.75 Ball pitch

Clk Gen.

I/O

~I/O

FUNCTIONAL BLOCK DIAGRAM

o
w

e
l
e
c
t

Data

Cont.

Column Select

CLK

Gen

Pre-Charge Circuit

Memory Array

512 Rows

128x16 Columns

I/O Circuit &

I/O

~I/O

Data

Cont.

K6R1016V1C-C10/C12/C15

Commercial Temp.

K6R1016V1C-I10/I12/I15

Industrial Temp.

ORDERING INFORMATION

PIN FUNCTION

Pin Name

Pin Function

- A

Address Inputs

Write Enable

Chip Select

Output Enable

Lower-byte Control(I/O

~I/O

)

Upper-byte Control(I/O

~I/O

)

I/O

~ I/O

Data Inputs/Outputs

Power(+3.3V)

Ground

N.C

No Connection

K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 3 -

September 2001

for AT&T

ABSOLUTE MAXIMUM RATINGS*

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter

Symbol

Rating

Unit

Voltage on Any Pin Relative to V

OUT

-0.5 to 4.6

Voltage on V

Supply Relative to V

-0.5 to 4.6

Power Dissipation

Storage Temperature

STG

-65 to 150

�

Operating Temperature

Commercial

0 to 70

�

Industrial

-40 to 85

�

RECOMMENDED DC OPERATING CONDITIONS

= 0 to 70

�

(1) For K6R1016V1C-10 only.

(2) For all speed grades except K6R1016V1C-10.

(3) V

(Max) = V

CC +

2.0V a.c(Pulse Width

8ns) for I

20mA

(4) V

(Min) = -2.0V a.c(Pulse Width

8ns) for I

20mA.

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

(1)

3.15

3.3

3.6

Supply Voltage

(2)

3.0

3.3

3.6

Ground

Input High Voltage

2.0

+0.3

(3)

Input Low Voltage

-0.3

(4)

0.8

N.C

I/O1

I/O9

I/O2

I/O3

I/O11

I/O10

Vss

I/O4

N.C

I/O12

Vcc

I/O5

N.C

I/O13

Vss

I/O7

I/O6

A14

A15

I/O14

I/O15

I/O8

N.C

A12

A13

I/O16

N.C

A10

A11

N.C

48-CSP

PIN CONFIGURATION(TOP VIEW)

SOJ/

TSOP2

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22

OE
UB
LB
I/O

I/O

Vss
Vcc
I/O

I/O

N.C
A

N.C

I/O

Vcc
Vss

I/O

N.C

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 4 -

September 2001

for AT&T

TEST CONDITIONS*

* The above test conditions are also applied at industrial temperature range.

Parameter

Value

Input Pulse Levels

0V to 3V

Input Rise and Fall Times

3ns

Input and Output timing Reference Levels

1.5V

Output Loads

See below

AC CHARACTERISTICS

=0 to 70

�

C, Vcc=3.3V+0.3V/-0.15V, unless otherwise noted.)

Output Loads(B)

OUT

5pF*

319

353

for t

, t

WHZ

, t

OLZ

& t

OHZ

+3.3V

* Including Scope and Jig Capacitance

Output Loads(A)

OUT

= 50

= 1.5V

30pF*

* Capacitive Load consists of all components of the
test environment.

CAPACITANCE*

=25

�

C, f=1.0MHz)

* Capacitance is sampled and not 100% tested.

Item

Symbol

Test Conditions

MIN

Max

Unit

Input/Output Capacitance

I/O

=0V

Input Capacitance

=0V

DC AND OPERATING CHARACTERISTICS*

(

=0 to 70

�

C, Vcc=3.3V+0.3V/-0.15V, unless otherwise specfied)

* The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

Test Conditions

Min

Max

Unit

Input Leakage Current

-2

�

Output Leakage Current

CS=V

or OE =V

or WE=V

OUT

-2

�

Operating Current

Min. Cycle, 100% Duty
CS=V

IL,

= V

IL,

OUT

= 0mA

10ns

105

12ns

15ns

Standby Current

Min. Cycle, CS =V

SB1

f=0MHz, CS

-0.2V,

-0.2V or V

0.2V

Normal

L-Ver.

0.5

Output Low Voltage Level

=8mA

0.4

Output High Voltage Level

=-4mA

2.4

K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 5 -

September 2001

for AT&T

WRITE CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

K6R1016V1C-10

K6R1016V1C-12

K6R1016V1C-15

Unit

Min

Max

Min

Max

Min

Max

Write Cycle Time

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width(OE High)

Write Pulse Width(OE Low)

WP1

UB , LB Valid to End of Write

Write Recovery Time

Write to Output High-Z

WHZ

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

READ CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

K6R1016V1C-10

K6R1016V1C-12

K6R1016V1C-15

Unit

Min

Max

Min

Max

Min

Max

Read Cycle Time

Address Access Time

Chip Select to Output

Output Enable to Valid Output

UB, LB Access Time

Chip Enable to Low-Z Output

UB, LB Enable to Low-Z Output

BLZ

Output Enable to Low-Z Output

OLZ

Chip Disable to High-Z Output

Output Disable to High-Z Output

OHZ

UB, LB Disable to High-Z Output

BHZ

Output Hold from Address Change

Chip Selection to Power Up Time

Chip Selection to Power DownTime

Address

Data Out

Previous Valid Data

Valid Data

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1)

(Address Controlled

CS=OE=V

, WE=V

, UB, LB=V

K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 6 -

September 2001

for AT&T

NOTES(READ CYCLE)
1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. t

and t

OHZ

are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V

levels.

4. At any given temperature and voltage condition, t

(Max.) is less than t

(Min.) both for a given device and from device to

device.

5. Transition is measured

�

200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=V

IL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF READ CYCLE(2)

(WE=V

)

Valid Data

High-Z

Address

UB, LB

Data out

HZ(3,4,5)

OLZ

LZ(4,5)

OHZ

BHZ(3,4,5)

BLZ(4,5)

50%

Current

TIMING WAVEFORM OF WRITE CYCLE(1)

(OE =Clock)

Address

UB, LB

Data in

Data out

CW(3)

WP(2)

AS(4)

OHZ(6)

High-Z

Valid Data

WR(5)

K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 7 -

September 2001

for AT&T

TIMING WAVEFORM OF WRITE CYCLE(3)

(CS=Controlled)

Address

Valid Data

Data in

Data out

High-Z

High-Z(8)

UB, LB

CW(3)

WP(2)

AS(4)

WR(5)

High-Z

WHZ(6)

TIMING WAVEFORM OF WRITE CYCLE(2)

(OE =Low fixed)

Address

UB, LB

Data in

Data out

CW(3)

WP1(2)

WR(5)

AS(4)

WHZ(6)

(10)

(9)

High-Z

Valid Data

High-Z

K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 8 -

September 2001

for AT&T

FUNCTIONAL DESCRIPTION

* X means Don

t Care

Mode

I/O Pin

Supply Current

I/O

~I/O

I/O

~I/O

Not Select

High-Z

, I

SB1

Output Disable

High-Z

Read

OUT

High-Z

OUT

Write

High-Z

NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE

going low; A write ends at the earliest transition CS going high or WE going high. t

is measured from the beginning of write

to the end of write.

3. t

is measured from the later of CS going low to end of write.

4. t

A S

is measured from the address valid to the beginning of write.

5. t

W R

is measured from the end of write to the address change. t

applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

Address

Valid Data

UB, LB

Data in

Data out

TIMING WAVEFORM OF WRITE CYCLE(4)

(UB, LB Controlled)

CW(3)

WP(2)

WR(5)

AS(4)

High-Z

High-Z(8)

BLZ

WHZ(6)

High-Z

K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 9 -

September 2001

for AT&T

DATA RETENTION CHARACTERISTICS*

to 70

�

* The above parameters are also guaranteed at industrial temperature range.

Data Retention Characteristic is for L-ver only.

Parameter

Symbol

Test Condition

Min.

Typ.

Max.

Unit

for Data Retention

-0.2V

2.0

3.6

Data Retention Current

=3.0V, CS

-0.2V

-0.2V or V

0.2V

0.4

=2.0V, CS

-0.2V

-0.2V or V

0.2V

0.3

Data Retention Set-Up Time

SDR

See Data Retention
Wave form(below)

Recovery Time

RDR

DATA RETENTION WAVE FORM

CS controlled

3.0V

GND

Data Retention Mode

- 0.2V

SDR

RDR

K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 10

September 2001

for AT&T

44-SOJ-400

#44

25.58

�

0.12

1.125

�

0.005

MAX

28.98

1.141

MAX

0.148

3.76

1.19

( )

0.047

1.27

( )

0.050

0.95

( )

0.0375

+0.10

0.43

- 0.05

+0.004

0.017

-0.002

+0.10

0.71

-0.05

+0.004

0.028

-0.002

1.27

0.050

1
0

.
1
6

0
.
4
0
0

+0.10

0.20

-0.05

+0.004

0.008

-0.002

9.40

�

0.25

0.370

�

0.010

MIN

0.69

0.027

#22

#23

0.004

0.10 MAX

11.18

�

0.12

0.440

�

0.005

PACKAGE DIMENSIONS

Units:millimeters/Inches

1.00

�

0.10

0.039

�

0.004

44-TSOP2-400BF

0.002

0.05

#22

#23

0.30

0.012

0.80

0.0315

MIN

0.047

1.20

MAX

0.741

18.81 MAX

18.41

�

0.10

0.725

�

0.004

11.76

�

0.20

0.463

�

0.008

+ 0.075

- 0.035

0.50

+ 0.003

- 0.001

0.125
0.005

0.020

1
0
.
1
6

0
.
4

0
0

0.10

0.004

0~8

�

0.45 ~0.75

0.018 ~ 0.030

( )

0.805

0.032

( )

MAX

Units:millimeters/Inches

#44

0.25

0.010 TYP

0.10

0.05

0.004

0.002

K6R1016V1C-C/C-L, K6R1016V1C-I/C-P

CMOS SRAM

Revision 4.0

- 11

September 2001

for AT&T

1
/
2

PACKAGE OUTLINE

(Units : millimeter)

B/2

Bottom View

Top View

Side View

0
.
8
0
/
T
y
p
.

0
.
2
5
/
T
y
p
.

Detail A

Min

Typ

Max

0.75

5.90

6.00

6.10

3.75

6.90

7.00

7.10

5.25

0.30

0.35

0.40

1.05

1.20

0.80

0.20

0.25

0.30

0.08

0.50

#A1

0
.
3
0

A1 INDEX MARK

Notes.
1. Bump counts: 48(8row x 6column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerance are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.08(Max)

Электронный компонент: K6R1016V1C-I/C-P