K6R3024V1D
CMOS SRAM
Revision 1.0
- 1 -
December 2001
for AT&T
Document Title
128Kx24 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 0.3
Rev. 0.4
Rev. 1.0
Remark
Design-In
Preliminary
Preliminary
Preliminary
Preliminary
Final
History
Design-In Specification
Pin Configurations Modified ( page 2 )
Add Timing Diagram page 6 ~ 8 )
Modified Read Cycle Timing(2)
1) Version change from M to D
2) C
in
from 20 to 15 pF
3) Icc from 300 to 170mA for 9ns products
from 270 to 150mA for 10ns products
from 240 to 130mA for 12ns products
4) Isb ( TTL ) from 120 to 40 mA for all products
( CMOS ) from 30 to 15 mA for all products
5) Part number change from -9 to -09 for 9ns products
Change write parameter( tDW) from 6ns to 5ns at -10
Final Specification Release
Draft Data
Dec. 05. 2000
Mar. 07. 2001
April. 04.2001
June. 23.2001
Oct. 31. 2001
Dec. 19. 2001
K6R3024V1D
CMOS SRAM
Revision 1.0
- 2 -
December 2001
for AT&T
128K x 24 Bit High-Speed CMOS Static RAM(3.3V Operating)
The K6R3024V1D is a 3,145,728-bit high-speed Static Random
Access Memory organized as 131,072 words by 24 bits. The
K6R3024V1D uses 24 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG's
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R3024V1D is a three
megabit static RAM constructed on an multilayer laminate sub-
strate using three 3.3V, 128K x 8 static RAMS encapsulated in a
Ball Grid Array(BGA).
GENERAL DESCRIPTION
FEATURES
Fast Access Time 9,10,12ns
Power Dissipation
Standby (TTL) : 40mA(Max.)
(CMOS) : 15mA(Max.)
Operating K6R3024V1D-09 : 170mA(Max.)
K6R3024V1D-10 : 150mA(Max.)
K6R3024V1D-12 : 130mA(Max.)
Single 3.3V Power Supply
TTL Compatible Inputs and Outputs
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Center Power/Ground Pin Configuration
119(7x17)Pin Ball Grid Array Package(14mmx22mm)
Operating in Commercial and Industrial Temperature range.
128K x 8
FUNCTIONAL BLOCK DIAGRAM
8
A0-16
ORDERING INFORMATION
K6R3024V1D-HC09/HC10/HC12
Commercial Temp.
K6R3024V1D-HI09/HI10/HI12
Industrial Temp.
CS1
WE
OE
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
16
Addresses Inputs
WE
Write Enable
CS
1
,CS
2
,
CS
3
Chip Select
OE
Output Enable
I/O
0
~ I/O
23
Data Inputs/Outputs
V
CC
Power(+3.3v)
V
ss
Ground
NC
No Connection
SRAM
128K x 8
SRAM
128K x 8
SRAM
8
8
17
I/O
0-7
I/O
8-15
I/O
16-23
PIN CONFIGURATIONS
(TOP VIEW)
CS2
CS3
K6R3024V1D
1
2
3
4
5
6
7
A
NC
A
A
A
A
A
NC
B
NC
A
A
CS
1
A
A
NC
C
I/O
NC
CS
2
NC
CS
3
NC
I/O
D
I/O
V
CC
V
ss
V
ss
V
ss
V
CC
I/O
E
I/O
V
ss
V
CC
V
ss
V
CC
V
ss
I/O
F
I/O
V
CC
V
ss
V
ss
V
ss
V
CC
I/O
G
I/O
V
ss
V
CC
V
ss
V
CC
V
ss
I/O
H
I/O
V
CC
V
ss
V
ss
V
ss
V
CC
I/O
J
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
K
I/O
V
CC
V
ss
V
ss
V
ss
V
CC
I/O
L
I/O
V
ss
V
CC
V
ss
V
CC
V
ss
I/O
M
I/O
V
CC
V
ss
V
ss
V
ss
V
CC
I/O
N
I/O
V
ss
V
CC
V
ss
V
CC
V
ss
I/O
P
I/O
V
CC
V
ss
V
ss
V
ss
V
CC
I/O
R
I/O
NC
NC
NC
NC
NC
I/O
T
NC
A
A
WE
A
A
NC
U
NC
A
A
OE
A
A
NC
K6R3024V1D
CMOS SRAM
Revision 1.0
- 3 -
December 2001
for AT&T
RECOMMENDED DC OPERATING CONDITIONS
*(T
A
=0 to 70
C)
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
8ns) for I
20mA.
*** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
8ns) for I
20mA.
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0
-
V
CC
+0.3***
V
Input Low Voltage
V
IL
-0.3**
-
0.8
V
TRUTH TABLE
CS
1
CS
2
CS
3
OE
WE
Mode
I/O
Power
H
X
X
X
X
Standby
High-Z
Standby
X
L
X
X
X
Standby
High-Z
Standby
X
X
H
X
X
Standby
High-Z
Standby
L
H
L
L
H
Read
DATA
OUT
Active
L
H
L
X
L
Write
DATA
IN
Active
L
H
L
H
H
Outputs Disabled
High-Z
Active
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
,
V
OUT
-0.5 to 4.6
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-0.5 to 4.6
V
Power Dissipation
P
d
2
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
Commercial
T
A
0 to 70
C
Industrial
T
A
-40 to 85
C
K6R3024V1D
CMOS SRAM
Revision 1.0
- 4 -
December 2001
for AT&T
AC TEST CONDITIONS*
(T
A
=0 to 70
C, Vcc=3.3
0.3V, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
3ns
Input and output Timing Reference Levels
1.5V
Output Load
See Below
CAPACITANCE*
(T
A
=25
C, f=1.0MHz)
* Capacitance is sampled and not 100% tested
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
C
I/O
V
I/O
=0V
-
8
pF
Input Capacitance
C
IN
V
IN
=0V
-
15
pF
Output Loads(B)
D
OUT
5pF*
319
216
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+3.3V
* Including Scope and Jig Capacitance
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70
C, Vcc=3.3
0.3V, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
* CS represents CS
1
, CS
2
and CS
3
in this data sheet. CS
2
as of opposite polarity to CS
1
and CS
3.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
IN
=V
ss
to V
CC
-
6
A
Output Leakage Current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to
V
CC
-
2
A
Operating Current
I
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or
V
IL,
I
OUT
=0mA
-09
-
170
mA
-10
-
150
mA
-12
-
130
mA
Standby Current
I
SB
Min. Cycle, CS=V
IH
-09
-
40
mA
-10
-
40
mA
-12
-
40
mA
I
SB1
f=0MHz, CS
V
CC
-0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V
-09
-
15
mA
-10
-
15
mA
-12
-
15
mA
Output Low Voltage Level
V
OL
I
OL
=8mA
-
0.4
V
Output High Voltage Level
V
OH
I
OH
=-4mA
2.4
-
V
K6R3024V1D
CMOS SRAM
Revision 1.0
- 5 -
December 2001
for AT&T
READ CYCLE*
Parameter
Symbol
K6R3024V1D-09
K6R3024V1D-10
K6R3024V1D-12
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
9
-
10
-
12
-
ns
Address Access Time
t
AA
-
9
-
10
-
12
ns
Chip Select to Output
t
CO
-
9
-
10
-
12
ns
Output Enable to Valid Output
t
OE
-
4
-
5
-
6
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
4
0
5
0
6
ns
Output Disable to High-Z Output
t
OHZ
0
5
0
6
0
7
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
ns
Chip Select to Power-Up Time
t
PU
0
-
0
-
0
-
ns
Chip Deselect to Power DownTime
t
PD
-
9
-
10
-
12
ns
WRITE CYCLE*
* This parameter is guaranteed by design but not tested.
These specifications are for the individual K6R3024V1D Static RAMs.
Parameter
Symbol
K6R3024V1D-09
K6R3024V1D-10
K6R3024V1D-12
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
9
-
10
-
12
-
ns
Chip Select to End of Write
t
CW
7
-
7
-
8
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
7
-
7
-
8
-
ns
Write Pulse Width(OE High)
t
WP
7
-
7
-
8
-
ns
Write Pulse Width(OE Low)
t
WP1
9
-
9
-
10
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
5
0
5
0
5
ns
Data to Write Time Overlap
t
DW
5
-
5
-
7
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
3
-
ns
K6R3024V1D
CMOS SRAM
Revision 1.0
- 6 -
December 2001
for AT&T
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
9. CS represents CS
1
, CS
2
and CS
3
in this data sheet. CS
2
as of opposite polarity to CS
1
and CS
3.
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
CS
Address
OE
Data out
t
AA
t
OLZ
t
LZ(4,5)
t
OHZ
t
RC
t
OE
t
CO
t
PU
t
PD
Valid Data
t
HZ(3,4,5)
50%
50%
V
CC
Current
I
CC
I
SB
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
K6R3024V1D
CMOS SRAM
Revision 1.0
- 7 -
December 2001
for AT&T
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
Address
CS
t
WP(2)
t
DW
t
DH
Valid Data
WE
Data in
Data out
t
WC
t
WR(5)
t
AW
t
CW(3)
High-Z(8)
High-Z
OE
t
OHZ(6)
t
AS(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low Fixed)
Address
CS
t
WP1(2)
t
DW
t
DH
t
OW
t
WHZ(6)
Valid Data
WE
Data in
Data out
t
WC
t
AS(4)
t
WR(5)
t
AW
t
CW(3)
(10)
(9)
High-Z(8)
High-Z
K6R3024V1D
CMOS SRAM
Revision 1.0
- 8 -
December 2001
for AT&T
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. t
WP
is measured from the beginning of write to the end of
write.
3. t
CW
is measured from the later of CS going low to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
11. CS represents CS
1
, CS
2
and CS
3
in this data sheet. CS
2
as of opposite polarity to CS
1
and CS
3.
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
=
Controlled)
Address
CS
t
AW
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z(8)
t
CW(3)
t
WP(2)
t
AS(4)
t
WC
t
WR(5)
High-Z
High-Z
t
LZ
t
WHZ(6)
K6R3024V1D
CMOS SRAM
Revision 1.0
- 9 -
December 2001
for AT&T
0.750
0.15
1.27
1.27
12.50
0.10
0.60
0.10
0.60
0.10
1.50REF
C1.00
C0.70
14.00
0.10
22.00
0.10
20.50
0.10
NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
Indicator of
Ball(1A) Location
119 BGA PACKAGE DIMENSIONS
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