K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
- 1 -
May 1999
Document Title
512Kx8 Bit High Speed Static RAM(3.3V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
Rev. 2.1
Rev. 2.2
Remark
Design Target
Preliminary
Final
Final
Final
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Add 30pF capacitive in test load.
2.3. Relax DC characteristics.
Change operating current at Industrial Temperature range.
Previous spec. Changed spec.
Items (10/12/15ns part) (10/12/15ns part)
Icc 205/200/195mA 230/225/220mA
Add 44 pins plastic TSOP(II) forward Package.
Item
Previous
Current
I
CC
10ns
170mA
205mA
12ns
160mA
200mA
15ns
150mA
195mA
I
SB
f=max.
40mA
50mA
I
SB1
f=0
10 / 1mA
10 / 1.2mA
I
DR
V
DR
=3.0V
0.9mA
1.0mA
Draft Data
Jan. 1st, 1997
Jun. 1st, 1997
Feb.11th.1998
Jun.27th 1998
May. 4th 1999
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
- 2 -
May 1999
512K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)
GENERAL DESCRIPTION
FEATURES
Fast Access Time 10,12,15ns(Max.)
Low Power Dissipation
Standby (TTL) : 50mA(Max.)
(CMOS) : 10mA(Max.)
1.2mA(Max.)- L-Ver.
Operating K6R4008V1B-10 : 205mA(Max.)
K6R4008V1B-12 : 200mA(Max.)
K6R4008V1B-15 : 195mA(Max.)
Single 3.3
0.3V Power Supply
TTL Compatible Inputs and Outputs
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
2V Minimum Data Retention ; L-Ver. only
Center Power/Ground Pin Configuration
Standard Pin Configuration
K6R4008V1B-J : 36-SOJ-400
K6R4008V1B-T: 36-TSOP2-400F
K6R4008V1B-U: 44-TSOP2-400AF
Clk Gen.
I/O
1
~I/O
8
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
R
o
w
S
e
l
e
c
t
Data
Cont.
Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
1024x8 Columns
I/O Circuit
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
18
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O
1
~ I/O
8
Data Inputs/Outputs
V
CC
Power(+3.3V)
V
SS
Ground
N.C
No Connection
The K6R4008V1B is a 4,194,304-bit high-speed Static Random
Access Memory organized as 524,288 words by 8 bits. The
K6R4008V1B uses 8 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG
s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density high-speed system applications. The
K6R4008V1B is packaged in a 400 mil 36-pin plastic SOJ or
TSOP(II) forward or 44-pin plastic TSOP(II) forward.
A
10
A
12
A
14
A
16
A
18
K6R4008V1B-C10/C12/C15
Commercial Temp.
K6R4008V1B-I10/I12/I15
Industrial Temp.
ORDERING INFORMATION
A
9
A
11
A
13
A
15
A
17
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
- 3 -
May 1999
PIN CONFIGURATION
(Top View)
36-SOJ/
N.C
A
18
A
17
A
16
A
15
OE
I/O
8
I/O
7
Vss
Vcc
I/O
6
I/O
5
A
14
A
13
A
12
A
11
A
10
N.C
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
Vcc
Vss
I/O
3
I/O
4
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
TSOP2
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
18
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O
1
~ I/O
8
Data Inputs/Outputs
V
CC
Power(+3.3V)
V
SS
Ground
N.C
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
N.C
N.C
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
Vcc
Vss
I/O
3
I/O
4
WE
A
5
A
6
A
7
A
8
A
9
N.C
N.C
N.C
N.C
N.C
A
18
A
17
A
16
A
15
OE
I/O
8
I/O
7
Vss
Vcc
I/O
6
I/O
5
A
14
A
13
A
12
A
11
A
10
N.C
N.C
N.C
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44-TSOP2
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
,
V
OUT
-0.5 to 4.6
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-0.5 to 4.6
V
Power Dissipation
P
D
1.0
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
Commercial
T
A
0 to 70
C
Industrial
T
A
-40 to 85
C
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
- 4 -
May 1999
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70
C, Vcc=3.3
0.3V, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
IN
=V
SS
to
V
CC
-2
2
A
Output Leakage Current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to
V
CC
-2
2
A
Operating Current
I
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or
V
IL,
I
OUT
=0mA
10ns
-
205
mA
12ns
-
200
15ns
-
195
Standby Current
I
SB
Min. Cycle, CS=V
IH
-
50
mA
I
SB1
f=0MHz, CS
V
CC
-0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V
Normal
-
10
mA
L-Ver.
-
1.2
Output Low Voltage Level
V
OL
I
OL
=8mA
-
0.4
V
Output High Voltage Level
V
OH
I
OH
=-4mA
2.4
-
V
CAPACITANCE*
(T
A
=25
C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
C
I/O
V
I/O
=0V
-
8
pF
Input Capacitance
C
IN
V
IN
=0V
-
7
pF
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70
C)
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
8ns) for I
20mA.
*** V
IH
(Max) = V
CC +
2.0V a.c (Pulse Width
8ns) for I
20mA.
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
3.0
3.3
3.6
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.0
-
V
CC
+0.3***
V
Input Low Voltage
V
IL
-0.3**
-
0.8
V
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
- 5 -
May 1999
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R4008V1B-10
K6R4008V1B-12
K6R4008V1B-15
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
10
-
12
-
15
-
ns
Address Access Time
t
AA
-
10
-
12
-
15
ns
Chip Select to Output
t
CO
-
10
-
12
-
15
ns
Output Enable to Valid Output
t
OE
-
5
-
6
-
7
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
5
0
6
0
7
ns
Output Disable to High-Z Output
t
OHZ
0
5
0
6
0
7
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
t
PU
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
t
PD
-
15
-
12
-
15
ns
TEST CONDITIONS*
* The above test conditions are also applied at industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
C, V
CC
=3.3
0.3V, unless otherwise noted.)
Output Loads(B)
D
OUT
5pF*
319
353
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+3.3V
* Including Scope and Jig Capacitance
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
- 6 -
May 1999
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R4008V1B-10
K6R4008V1B-12
K6R4008V1B-15
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
10
-
12
-
15
-
ns
Chip Select to End of Write
t
CW
7
-
8
-
10
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
7
-
8
-
10
-
ns
Write Pulse Width(OE High)
t
WP
7
-
8
-
10
-
ns
Write Pulse Width(OE Low)
t
WP1
10
-
12
-
15
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
5
0
6
0
7
ns
Data to Write Time Overlap
t
DW
5
-
6
-
7
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
3
-
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
CS
Address
OE
Data out
t
AA
t
OLZ
t
LZ(4,5)
t
OH
t
OHZ
t
RC
t
OE
t
CO
t
PU
t
PD
Valid Data
t
HZ(3,4,5)
50%
50%
V
CC
Current
I
CC
I
SB
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
- 7 -
May 1999
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
Address
CS
t
WP(2)
t
DW
t
DH
Valid Data
WE
Data in
Data out
t
WC
t
WR(5)
t
AW
t
CW(3)
High-Z(8)
High-Z
OE
t
OHZ(6)
t
AS(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low Fixed)
Address
CS
t
WP1(2)
t
DW
t
DH
t
OW
t
WHZ(6)
Valid Data
WE
Data in
Data out
t
WC
t
AS(4)
t
WR(5)
t
AW
t
CW(3)
(10)
(9)
High-Z(8)
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
=
Controlled)
Address
CS
t
AW
t
DW
t
DH
Valid Data
WE
Data in
Data out
High-Z
High-Z(8)
t
CW(3)
t
WP(2)
t
AS(4)
t
WC
t
WR(5)
High-Z
High-Z
t
LZ
t
WHZ(6)
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
- 8 -
May 1999
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. t
WP
is measured from the beginning of write to the end of
write.
3. t
CW
is measured from the later of CS going low to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
* X means Don
t Care.
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
X*
Not Select
High-Z
I
SB
, I
SB1
L
H
H
Output Disable
High-Z
I
CC
L
H
L
Read
D
OUT
I
CC
L
L
X
Write
D
IN
I
CC
DATA RETENTION CHARACTERISTICS*
(T
A
=0 to 70
C)
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
Parameter
Symbol
Test Condition
Min.
Typ.
Max.
Unit
V
CC
for Data Retention
V
DR
CS
V
CC
- 0.2V
2.0
-
3.6
V
Data Retention Current
I
DR
V
CC
=3.0V, CS
V
CC
- 0.2V
V
IN
V
CC
- 0.2V or V
IN
0.2V
-
-
1.0
mA
V
CC
= 2.0V, CS
V
CC
- 0.2V
V
IN
V
CC
- 0.2V or V
IN
0.2V
-
-
0.7
mA
Data Retention Set-Up Time
t
SDR
See Data Retention
Wave form(below)
0
-
-
ns
Recovery Time
t
RDR
5
-
-
ms
DATA RETENTION WAVE FORM
V
CC
3.0V
V
IH
V
DR
CS
GND
Data Retention Mode
CS
V
CC
- 0.2V
t
SDR
t
RDR
CS controlled
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
- 9 -
May 1999
PACKAGE DIMENSIONS
Units:millimeters/Inches
36-TSOP2-400F
#19
#18
0.075 MAX
0.10 MAX
1.00
0.039
#36
#1
+0.10
0.15
-0.05
+0.004
0.006
-0.002
11.76
0.20
0.463
0.008
(0.50)
(0.020)
18.41
0.10
0.725
0.004
MAX
18.81
0.741
MAX
1.20
0.047
MIN
0.002
0.05
(0.705)
(0.028)
0.40
0.10
0.016
0.004
0~8
TYP
0.45 ~0.75
0.018 ~ 0.030
1.00
0.10
0.039
0.004
1
0
.
1
6
0
.
4
0
0
#1
36-SOJ-400
#36
23.50
0.12
0.925
0.005
MAX
23.90
0.941
MAX
0.148
3.76
1.19
( )
0.047
1.27
( )
0.050
0.95
( )
0.0375
+0.10
0.43
-0.05
+0.004
0.017
-0.002
+0.10
0.71
-0.05
+0.004
0.028
-0.002
1.27
0.050
#18
#19
1
0
.
1
6
0
.
4
0
0
+0.10
0.20
-0.05
+0.004
0.008
-0.002
9.40
0.25
0.370
0.010
MIN
0.69
0.027
0.004
0.10
MAX
11.18
0.12
0.440
0.005
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
- 10
May 1999
44-TSOP2-400AF
0.002
#1
0.05
#22
#44
#23
0.35
0.10
0.014
0.004
0.80
0.0315
MIN.
0.047
1.20
MAX.
0.741
18.81
MAX.
18.41
0.10
0.725
0.004
11.76
0.20
0.463
0.008
+ 0.
10
- 0.0
5
0.50
+ 0.0
04
- 0.
002
0.15
0.00
6
0.020
1
0
.
1
6
0
.
4
0
0
0.10
0.004
0~8
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
( )
0.805
0.032
( )
MAX
1.00
0.10
0.039
0.004
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