K6R4004C1D
CMOS SRAM
PRELIMINARY
Rev 1.0
- 1 -
July 2002
Document Title
1Mx4 Bit High Speed Static RAM(5.0V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 0.3
Rev. 1.0
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
History
Initial release with Preliminary.
Change Icc. Isb and Isb1
1. Correct AC parameters : Read & Write Cycle mA
2. Delete Low Ver.
3. Delete Data Retention Characteristics
1. Delete 15ns speed bin.
2. Change Icc for Industrial mode.
1. Final datasheet release.
2. Delete 12ns speed bin.
3. Delete UB,LB releated AC characteristics and timing diagram.
4. Correct Read Cycle time waveform(2).
Item
Previous
Current
I
CC(Commercial)
10ns
90mA
65mA
12ns
80mA
55mA
15ns
70mA
45mA
I
CC(Industrial)
10ns
115mA
85mA
12ns
100mA
75mA
15ns
85mA
65mA
I
SB
30mA
20mA
I
SB1
10mA
5mA
Item
Previous
Current
I
CC(Industrial)
10ns
85mA
75mA
12ns
75mA
65mA
Draft Data
September. 7. 2001
November, 3. 2001
November, 3. 2001
December, 18. 2001
July, 09, 2002
K6R4004C1D
CMOS SRAM
PRELIMINARY
Rev 1.0
- 2 -
July 2002
4Mb Async. Fast SRAM Ordering Information
Org.
Part Number
VDD(V)
Speed ( ns )
PKG
Temp. & Power
1M x4
K6R4004C1D-JC(I) 10
5
10
J : 32-SOJ
C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
L : Commercial Temperature
,Low Power Range
P : Industrial Temperature
,Low Power Range
K6R4004V1D-JC(I) 08/10
3.3
8/10
512K x8
K6R4008C1D-J(T)C(I) 10
5
10
J : 36-SOJ
T : 44-TSOP2
K6R4008V1D-J(T)C(I) 08/10
3.3
8/10
256K x16
K6R4016C1D-J(T,E)C(I) 10
5
10
J : 44-SOJ
T : 44-TSOP2
E : 48-TBGA
K6R4016V1D-J(T,E)C(I,L,P) 08/10
3.3
8/10
K6R4004C1D
CMOS SRAM
PRELIMINARY
Rev 1.0
- 3 -
July 2002
1M x 4 Bit High-Speed CMOS Static RAM
GENERAL DESCRIPTION
FEATURES
Fast Access Time 10ns(Max.)
Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R4004C1D-10 : 65mA(Max.)
Single 5.0V
10
%
Power Supply
TTL Compatible Inputs and Outputs
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Center Power/Ground Pin Configuration
Standard Pin Configuration
K6R4004C1D-J : 32-SOJ-400
Operating in Commercial and Industrial Temperature range.
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
19
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O
1
~ I/O
4
Data Inputs/Outputs
V
CC
Power(+5.0V)
V
SS
Ground
N.C
No Connection
The K6R4004C1D is a 4,194,304-bit high-speed Static Random
Access Memory organized as 1,048,576 words by 4 bits. The
K6R4004C1D uses 4 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG
s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R4004C1D is packaged
in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION
(Top View)
SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
19
A
18
A
17
A
16
A
15
OE
I/O
4
Vss
Vcc
I/O
3
A
14
A
13
A
12
A
11
A
10
N.C
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
Vcc
Vss
I/O
2
WE
A
5
A
6
A
7
A
8
A
9
Clk Gen.
I/O
1
~I/O
4
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
R
o
w
S
e
l
e
c
t
Data
Cont.
Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
1024 Rows
1024 x 4 Columns
I/O Circuit
A
10
A
12
A
14
A
16
A
18
A
11
A
13
A
15
A
17
A
19
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
K6R4004C1D
CMOS SRAM
PRELIMINARY
Rev 1.0
- 4 -
July 2002
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
,
V
OUT
-0.5 to V
CC+
0.5
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-0.5 to 7.0
V
Power Dissipation
P
D
1.0
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
Commercial
T
A
0 to 70
C
Industrial
T
A
-40 to 85
C
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70
C)
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
8ns) for I
20mA.
*** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
8ns) for I
20mA.
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
-
V
CC
+0.5**
V
Input Low Voltage
V
IL
-0.5*
-
0.8
V
CAPACITANCE*
(T
A
=25
C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
C
I/O
V
I/O
=0V
-
8
pF
Input Capacitance
C
IN
V
IN
=0V
-
6
pF
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70
C, Vcc=5.0V
10%, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
IN
=V
SS
to
V
CC
-2
2
A
Output Leakage Current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to
V
CC
-2
2
A
Operating Current
I
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or
V
IL,
I
OUT
=0mA
Com.
10ns
-
65
mA
Ind.
10ns
-
75
Standby Current
I
SB
Min. Cycle, CS=V
IH
-
20
mA
I
SB1
f=0MHz, CS
V
CC
-0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V
-
5
Output Low Voltage Level
V
OL
I
OL
=8mA
-
0.4
V
Output High Voltage Level
V
OH
I
OH
=-4mA
2.4
-
V
K6R4004C1D
CMOS SRAM
PRELIMINARY
Rev 1.0
- 5 -
July 2002
TEST CONDITIONS*
* The above test conditions are also applied at industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
C, V
CC
=5.0V
10%, unless otherwise noted.)
Output Loads(B)
D
OUT
5pF*
480
255
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5.0V
* Including Scope and Jig Capacitance
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R4004C1D-10
Unit
Min
Max
Read Cycle Time
t
RC
10
-
ns
Address Access Time
t
AA
-
10
ns
Chip Select to Output
t
CO
-
10
ns
Output Enable to Valid Output
t
OE
-
5
ns
Chip Enable to Low-Z Output
t
LZ
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
5
ns
Output Disable to High-Z Output
t
OHZ
0
5
ns
Output Hold from Address Change
t
OH
3
-
ns
Chip Selection to Power Up Time
t
PU
0
-
ns
Chip Selection to Power DownTime
t
PD
-
10
ns
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