K6T0808C1D Family
CMOS SRAM
Revision 1.0
November 1997
Document Title
32Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No
0.0
0.1
1.0
Remark
Design target
Preliminily
Final
History
Initial draft
First revision
-
K
M62256DL/DLI I
SB1
= 100
50
A
KM62256DL-L I
SB1
= 20
10
A
KM62256DLI-L I
SB1
= 50
15
A
- C
IN
= 6
8pF, C
IO
= 8
10pF
- KM62256D-4/5/7 Family
tOH = 5
10ns
- KM62256DL/DLI I
DR
= 50
30
A
KM62256DL-L/DLI-L I
DR
= 30
15
A
Finalize
- Remove I
CC
write value
- Improved operating current
I
CC2
= 70
60mA
- Improved standby current
KM62256DL/DLI I
SB1
= 50
30
A
KM62256DL-L I
SB1
= 10
5
A
KM62256DLI-L I
SB1
= 15
5
A
- Improved data retention current
KM62256DL/DLI I
DR
= 30
5
A
KM62256DL-L/DLI-L I
DR
= 15
3
A
- Remove 45ns part from commercial product and 100ns part
from industrial product.
Replace test load 100pF to 50pF for 55ns part
Draft Data
May 18, 1997
April 1, 1997
November 11, 1997
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
K6T0808C1D Family
CMOS SRAM
Revision 1.0
November 1997
32Kx8 bit Low Power CMOS Static RAM
GENERAL DESCRIPTION
The K6T0808C1D families are fabricated by SAMSUNG
s
advanced CMOS process technology. The families support
various operating temperature ranges and have various
package types for user flexibility of system design. The fami-
lies also support low data retention voltage for battery back-
up operation with low data retention current.
FEATURES
Process Technology : TFT
Organization : 32Kx8
Power Supply Voltage : 4.5~5.5V
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : 28-DIP-600B, 28-SOP-450
28-TSOP1-0813.4 F/R
PIN DESCRIPTION
Pin Name
Function
Pin Name
Function
CS
Chip Select Input
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
A
0
~A
14
Address Inputs
NC
No connect
PRODUCT FAMILY
1. The parameter is tested with 50pF test load.
Product Family
Operating Temperature
V
CC
Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(Icc
2,
Max)
K6T0808C1D-L
Commercial (0~70
C)
4.5 to 5.5V
55
1)
/70ns
30
A
60mA
28-DIP,28-SOP
28-TSOP1-F/R
K6T0808C1D-B
5
A
K6T0808C1D-P
Industrial (-40~85
C)
70ns
30
A
28-SOP
28-TSOP1-F/R
K6T0808C1D-F
5
A
FUNCTIONAL BLOCK DIAGRAM
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
28-DIP
28-SOP
15
16
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A11
A9
A8
A13
WE
VCC
A3
A14
A12
A7
A6
A5
A4
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
28-TSOP
Type1 - Forward
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
28
25
24
23
22
21
20
19
18
17
16
15
OE
28-TSOP
A11
A9
A8
A13
WE
VCC
A3
A14
A12
A7
A6
A5
A4
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
28
25
24
23
22
21
20
19
18
17
16
15
OE
Type1 - Reverse
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Precharge circuit.
Memory array
256 rows
128
8
columns
I/O Circuit
Column select
Clk gen.
Row
select
A10 A3
A0
A1
A2
A11
A9
A13
A8
A12
A14
A4
A5
A7
CS
WE
I/O
1
Data
cont
Data
cont
OE
I/O
8
A6
Control
Logic
K6T0808C1D Family
CMOS SRAM
Revision 1.0
November 1997
PRODUCT LIST
Commercial Temperature Products(0~70
C)
Industrial Temperature Products(-40~85
C)
Part Name
Function
Part Name
Function
K6T0808C1D-DL55
K6T0808C1D-DB55
K6T0808C1D-DL70
K6T0808C1D-DB70
K6T0808C1D-GL55
K6T0808C1D-GB55
K6T0808C1D-GL70
K6T0808C1D-GB70
K6T0808C1D-TL55
K6T0808C1D-TB55
K6T0808C1D-TL70
K6T0808C1D-TB70
K6T0808C1D-RL55
K6T0808C1D-RB55
K6T0808C1D-RL70
K6T0808C1D-RB70
28-DIP, 55ns, L-pwr
28-DIP, 55ns, LL-pwr
28-DIP, 70ns, L-pwr
28-DIP, 70ns, LL-pwr
28-SOP, 55ns, L-pwr
28-SOP, 55ns, LL-pwr
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP1 F, 55ns, L-pwr
28-TSOP1 F, 55ns, LL-pwr
28-TSOP1 F, 70ns, L-pwr
28-TSOP1 F, 70ns, LL-pwr
28-TSOP1 R, 55ns, L-pwr
28-TSOP1 R, 55ns, LL-pwr
28-TSOP1 R, 70ns, L-pwr
28-TSOP1 R, 70ns, LL-pwr
K6T0808C1D-GP70
K6T0808C1D-GF70
K6T0808C1D-TP70
K6T0808C1D-TF70
K6T0808C1D-RP70
K6T0808C1D-RF70
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP1 F, 70ns, L-pwr
28-TSOP1 F, 70ns, LL-pwr
28-TSOP1 R, 70ns, L-pwr
28-TSOP1 R, 70ns, LL-pwr
FUNCTIONAL DESCRIPTION
1. X means don
t care (Must be in high or low states)
CS
OE
WE
I/O
Mode
Power
H
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
High-Z
Output Disabled
Active
L
L
H
Dout
Read
Active
L
X
1)
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.5 to 7.0
V
-
Voltage on Vcc supply relative to Vss
V
CC
-0.5 to 7.0
V
-
Power Dissipation
P
D
1.0
W
-
Storage temperature
T
STG
-65 to 150
C
-
Operating Temperature
T
A
0 to 70
C
K6T0808C1D-L
-40 to 85
C
K6T0808C1D-P
Soldering temperature and time
T
SOLDER
260
C, 10sec (Lead Only)
-
-
K6T0808C1D Family
CMOS SRAM
Revision 1.0
November 1997
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. Commercial Product : T
A
=0 to 70
C, otherwise specified
Industrial Product : T
A
=-40 to 85
C, otherwise specified
2. Overshoot : V
CC
+3.0V in case of pulse width
30ns
3. Undershoot : -3.0V in case of pulse width
30ns
4. Overshoot and undershoot are sampled, not 100% tested
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.5V
2)
V
Input low voltage
V
IL
-0.5
3)
-
0.8
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled not, 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
, V
IO
=V
SS
to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
, Read
-
5
10
mA
Average operating current
I
CC1
Cycle time=1
s, 100% duty, I
IO
=0mA
CS
0.2V, V
IN
0.2V, V
IN
Vcc -0.2V
Read
-
2
5
mA
Write
-
20
I
CC2
Cycle time=Min,100% duty, I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
-
45
60
mA
Output low voltage
V
OL
I
OL
=2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS=V
IH
, Other inputs=V
IH
or V
IL
-
-
1
mA
Standby Current (CMOS)
I
SB1
CS
Vcc-0.2V, Other inputs=0~Vcc
Low Power
-
1
30
A
Low Low Power
-
0.2
5
A
K6T0808C1D Family
CMOS SRAM
Revision 1.0
November 1997
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
C
L
=50pF+1TTL
AC CHARACTERISTICS
(Vcc=4.5~5.5V, K6T0808C1D-L Family:T
A
=0 to 70
C, K6T0808C1D-P Family:T
A
=-40 to 85
C)
1. The parameter is tested with 50pF test load.
Parameter List
Symbol
Speed Bins
Units
55
1)
ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
30
ns
Output disable to high-Z output
t
OHZ
0
20
0
30
ns
Output hold from address change
t
OH
10
-
10
-
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
50
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
Vcc-0.2V
2.0
-
5.5
V
Data retention current
I
DR
Vcc=3.0V, CS
Vcc-0.2V
L-Ver
-
1
15
A
LL-Ver
-
0.2
3
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
K6T0808C1D Family
CMOS SRAM
Revision 1.0
November 1997
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ
t
RC
t
OE
t
CO
K6T0808C1D Family
CMOS SRAM
Revision 1.0
November 1997
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
Controlled)
Address
CS
t
WC
t
WR(4)
t
AS(3)
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
t
CW(2)
t
WP(1)
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, t
WP
is measured from the begining of write
to the end of write.
2. t
CW
is measured from the CS going low to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
V
CC
4.5V
2.2V
V
DR
CS
GND
Data Retention Mode
CS
V
CC
- 0.2V
t
SDR
t
RDR
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
WC
t
AW
t
AS(3)
K6T0808C1D Family
CMOS SRAM
Revision 1.0
November 1997
PACKAGE DIMENSIONS
Units: millimeter(inch)
1.65
#1
28 PIN DUAL INLINE PACKAGE(600mil)
#28
13.60
0.20
0.535
0.008
36.32
0.20
1.430
0.008
( )
0.065
1.52
0.10
0.060
0.004
0.46
0.10
0.018
0.004
1
5
.
2
4
0
.
6
0
0
+0.10
MAX
36.72
1.446
0.25
-0.05
+0.004
0.010
-0.002
#14
#15
2.54
0.100
MAX
3.81
0.20
0.150
0.008
5.08
0.200
MIN
0.015
0.38
0.130
0.012
3.30
0.30
0~15
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
0~8
#28
11.81
0.30
0.465
0.012
18.29
0.20
0.720
0.008
MAX
18.69
0.736
MAX
2.59
0.20
0.102
0.008
3.00
0.118
MIN
0.002
0.05
0.004 MAX
0.10 MAX
#15
0.41
0.10
0.016
0.004
#1
#14
0.89
( )
0.035
1
1
.
4
3
0
.
4
5
0
8.38
0.20
0.330
0.008
1.02
0.20
0.040
0.008
+0.10
0.15
-0.05
+0.004
0.006
-0.002
1.27
0.050
K6T0808C1D Family
CMOS SRAM
Revision 1.0
November 1997
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)
#28
1.00
0.10
0.039
0.004
M
A
X
8
.
4
0
0
.
3
3
1
0
.
0
0
4
M
A
X
0
.
1
0
M
A
X
#1
13.40
0.20
0.528
0.008
#15
#14
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.55
0.0217
0.425
( )
0.017
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
#28
1.00
0.10
0.039
0.004
M
A
X
8
.
4
0
0
.
3
3
1
0
.
0
0
4
M
A
X
0
.
1
0
M
A
X
#1
0.50
( )
0.020
11.80
0.10
0.465
0.004
0.45 ~0.75
0.018 ~0.030
13.40
0.20
0.528
0.008
#15
#14
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
0.425
( )
0.017
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
0.55
0.0217
+0.10
0.20
-0.05
+0.004
0.008
-0.002
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)
0.50
( )
0.020
11.80
0.10
0.465
0.004
0.45 ~0.75
0.018 ~0.030
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
TYP
0.25
0.010
Units: millimeter(inch)
PDF 
ZIP