K6T0808V1D, K6T0808U1D Family

CMOS SRAM

Revision 1.0

November 1997

Document Title

32Kx8 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No.

0.0

1.0

Remark

Preliminary

Final

History

Initial draft

Finalize
- Add 70ns part in KM62U256D Family
- Show I

read only, and increased value

= 2mA

Read = 5mA

- Seperate I

CC1

read and write

CC1

= 5mA

CC1

Read = 5mA, I

CC1

Write = 10mA

- Improved standby current(I

SB1

)

Commercial part : 10

Extended and Industrial part : 20

- Improved V

(Min.) : 0.4V

0.6V

- Improved power dissipation : 0.7W

Draft Data

April 1, 1997

November 12, 1997

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO, LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

K6T0808V1D, K6T0808U1D Family

CMOS SRAM

Revision 1.0

November 1997

32Kx8 bit Low Power and Low Voltage CMOS Static RAM

GENERAL DESCRIPTION

The K6T0808V1D and K6T0808U1D families are fabricated

by SAMSUNG's advanced CMOS process technology. The
families support various operating temperature range and

have various package types for user flexibility of system

design. The families also support low data retention voltage

for battery back-up operation with low data retention current.

FEATURES

· Process Technology: 0.4

m CMOS

· Organization: 32Kx8
· Power Supply Voltage
K6T0808V1D family: 3.0~3.6V
K6T0808U1D family: 2.7~3.3V
· Low Data Retention Voltage: 2V(Min)
· Three state output and TTL Compatible
· Package Type: 28-SOP-450, 28-TSOP1-0813.4F/R

PRODUCT FAMILY

1. The parameter is measured with 30pF test load.
2. K6T0808V1D Family support SOP package without 100ns speed bin.

Product Family

Operating Tempera-

ture

Range

Speed

Power Dissipation

PKG Type

Standby

SB1

, Max)

Operating

(Icc

, Max)

K6T0808V1D-B

Commercial(0~70

3.0V ~3.6V

/100ns

35mA

28-SOP

28-TSOP1-F/R

K6T0808U1D-B

2.7V ~ 3.3V

/85/100ns

K6T0808V1D-D

Extended(-25~85

3.0V ~3.6V

/100ns

K6T0808U1D-D

2.7V ~ 3.3V

/85/100ns

K6T0808V1D-F

Industrial(-40~85

3.0V ~3.6V

/100ns

K6T0808U1D-F

2.7V ~ 3.3V

/85/100ns

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

PIN DESCRIPTION

Pin Name

Function

Pin Name

Function

Address Inputs

I/O

~I/O

Data Inputs/Outputs

Write Enable Input

Vcc

Power

Chip Select Input

Vss

Ground

Output Enable Input

No connect

FUNCTIONAL BLOCK DIAGRAM

A14

A12

I/O1

I/O2

I/O3

VSS

VCC

A13

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

28-SOP

A11

A13

VCC

A14

A12

A10

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

28-TSOP

Type1 - Forward

28-TSOP

A11

A13

VCC

A14

A12

A10

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

Type1 - Reverse

Precharge circuit.

Memory array
256 rows
128

columns

I/O Circuit

Column select

Clk gen.

Row
select

A10 A3

A11

A13

A12

A14

I/O

Data
cont

I/O

Control
logic

K6T0808V1D, K6T0808U1D Family

CMOS SRAM

Revision 1.0

November 1997

PRODUCT LIST

Commercial Temp. Product

(0~70

Extended Temp. Products

(-25~85

Industrial Temp Products

(-40~85

Part Name

Function

Part Name

Function

Part Name

Function

K6T0808V1D-GB70

K6T0808V1D-TB70

K6T0808V1D-TB10

K6T0808V1D-RB70

K6T0808V1D-RB10

K6T0808U1D-GB70

K6T0808U1D-GB85

K6T0808U1D-GB10

K6T0808U1D-TB70

K6T0808U1D-TB85

K6T0808U1D-TB10

K6T0808U1D-RB70

K6T0808U1D-RB85

K6T0808U1D-RB10

28-SOP, 70ns, 3.3V

28-TSOP F, 70ns, 3.3V

28-TSOP F, 100ns, 3.3V

28-TSOP R, 70ns, 3.3V

28-TSOP R, 100ns, 3.3V

28-SOP, 70ns, 3.0V

28-SOP, 85ns, 3.0V

28-SOP, 100ns, 3.0V

28-TSOP F, 70ns, 3.0V

28-TSOP F, 85ns, 3.0V

28-TSOP F, 100ns, 3.0V

28-TSOP R, 70ns, 3.0V

28-TSOP R, 85ns, 3.0V

28-TSOP R, 100ns, 3.0V

K6T0808V1D-GD70

K6T0808V1D-TD70

K6T0808V1D-TD10

K6T0808V1D-RD70

K6T0808V1D-RD10

K6T0808U1D-GD70

K6T0808U1D-GD85

K6T0808U1D-GD10

K6T0808U1D-TD70

K6T0808U1D-TD85

K6T0808U1D-TD10

K6T0808U1D-RD70

K6T0808U1D-RD85

K6T0808U1D-RD10

28-SOP, 70ns, 3.3V

28-TSOP F, 70ns, 3.3V

28-TSOP F, 100ns, 3.3V

28-TSOP R, 70ns, 3.3V

28-TSOP R, 100ns, 3.3V

28-SOP, 70ns, 3.0V

28-SOP, 85ns, 3.0V

28-SOP, 100ns, 3.0V

28-TSOP F, 70ns, 3.0V

28-TSOP F, 85ns, 3.0V

28-TSOP F, 100ns, 3.0V

28-TSOP R, 70ns, 3.0V

28-TSOP R, 85ns, 3.0V

28-TSOP R, 100ns, 3.0V

K6T0808V1D-GF70

K6T0808V1D-TF70

K6T0808V1D-TF10

K6T0808V1D-RF70

K6T0808V1D-RF10

K6T0808U1D-GF70

K6T0808U1D-GF85

K6T0808U1D-GF10

K6T0808U1D-TF70

K6T0808U1D-TF85

K6T0808U1D-TF10

K6T0808U1D-RF70

K6T0808U1D-RF85

K6T0808U1D-RF10

28-SOP, 70ns, 3.3V

28-TSOP F, 70ns, 3.3V

28-TSOP F, 100ns, 3.3V

28-TSOP R, 70ns, 3.3V

28-TSOP R, 100ns, 3.3V

28-SOP, 70ns, 3.0V

28-SOP, 85ns, 3.0V

28-SOP, 100ns, 3.0V

28-TSOP F, 70ns, 3.0V

28-TSOP F, 85ns, 3.0V

28-TSOP F, 100ns, 3.0V

28-TSOP R, 70ns, 3.0V

28-TSOP R, 85ns, 3.0V

28-TSOP R, 100ns, 3.0V

FUNCTIONAL DESCRIPTION

1. X means don't care (Must be in high or low states)

I/O

Mode

Power

High-Z

Deselected

Standby

High-Z

Output Disabled

Active

Dout

Read

Active

Din

Write

Active

ABSOLUTE MAXIMUM RATINGS

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item

Symbol

Ratings

Unit

Remark

Voltage on any pin relative to Vss

OUT

-0.5 to V

+0.5

Voltage on Vcc supply relative to Vss

-0.5 to 4.6

Power Dissipation

1.0

Storage temperature

STG

-65 to 150

Operating Temperature

0 to 70

K6T0808V1D-L, K6T0808U1D-L

-25 to 85

K6T0808V1D-N, K6T0808U1D-N

-40 to 85

K6T0808V1D-P, K6T0808U1D-P

Soldering temperature and time

SOLDER

260

C, 10sec (Lead Only)

K6T0808V1D, K6T0808U1D Family

CMOS SRAM

Revision 1.0

November 1997

RECOMMENDED DC OPERATING CONDITIONS

Note:
1. Commercial Product : T

=0 to 70

C, otherwise specified

Industrial Product : T

=-40 to 85

C, otherwise specified

2. Overshoot : V

+3.0V in case of pulse width

30ns

3. Undershoot : -3.0V in case of pulse width

30ns

4. Overshoot and undershoot are sampled, not 100% tested

Item

Symbol

Product

Min

Typ

Max

Unit

Supply voltage

Vcc

K6T0808V1D Family

3.0

3.3

3.6

K6T0808U1D Family

2.7

3.0

3.3

Ground

Vss

ALL

Input high voltage

K6T0808V1D, K6T0808U1D Family

2.2

Vcc+0.3

Input low voltage

K6T0808V1D, K6T0808U1D Family

-0.3

0.6

CAPACITANCE

(f=1MHz, TA=25

1. Capacitance is sampled, not 100% tested

Item

Symbol

Test Condition

Min

Max

Unit

Input capacitance

=0V

Input/Output capacitance

=0V

DC AND OPERATING CHARACTERISTICS

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Input leakage current

=Vss to Vcc

-1

Output leakage current

CS=V

or OE=V

or WE=V

, V

to Vcc

-1

Operating power supply current

=0mA, CS=V

IL,

or V

, Read

Average operating current

CC1

Cycle time=1

s, 100% duty, I

=0mA

0.2V, V

Vcc -0.2V

Read

1.5

Write

CC2

Cycle time=Min,100% duty, I

=0mA, CS=V

IL,

or V

Output low voltage

=2.1mA

0.4

Output high voltage

=-1.0mA

2.4

Standby Current(TTL)

CS=V

, Other inputs=V

or V

0.3

Standby Current (CMOS)

SB1

Vcc-0.2V, Other inputs=0~Vcc

0.1

K6T0808V1D, K6T0808U1D Family

CMOS SRAM

Revision 1.0

November 1997

1. Including scope and jig capacitance

TEST CONDITIONS

(Test Load and Test Input/Output Reference)

Input pulse level : 0.4 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C

=100pF+1TTL

=30pF+1TTL

1. Refer to AC CHARACTERISTICS

AC OPERATING CONDITIONS

AC CHARACTERISTICS

(K6T0808V1D Family : Vcc=3.0~3.6V, , K6T0808U1D Family : Vcc=2.7~3.3V

Commercial product :T

=0 to 70

C, Extended product :T

=-25 to 85

C, Industrial product : T

=-40 to 85

1. The parameter is measured with 30pF test load

Parameter List

Symbol

Speed Bins

Units

85ns

100ns

Min

Max

Min

Max

Min

Max

Read

Read cycle time

100

Address access time

100

Chip select to output

100

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

OLZ

Chip disable to high-Z output

Output disable to high-Z output

OHZ

Output hold from address

Write

Write cycle time

100

Chip select to end of write

Address set-up time

Address valid to end of write

Write pulse width

Write recovery time

Write to output high-Z

WHZ

Data to write time overlap

Data hold from write time

End write to output low-Z

DATA RETENTION CHARACTERISTICS

Item

Symbol

Test Condition

Min

Typ

Max

Unit

Vcc for data retention

Vcc-0.2V

2.0

3.6

Data retention current

Vcc=3.0V, CS

Vcc-0.2V

Data retention set-up time

SDR

See data retention waveform

Recovery time

RDR

K6T0808V1D, K6T0808U1D Family

CMOS SRAM

Revision 1.0

November 1997

Address

Data Out

Previous Data Valid

Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1)

(Address Controlled

CS=OE=V

, WE=V

)

TIMING WAVEFORM OF READ CYCLE(2)

(WE=V

)

Data Valid

High-Z

Address

Data out

NOTES (READ CYCLE)

and

OHZ

are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition,

(Max.) is less than

(Min.) both for a given device and from device to device

interconnection.

OLZ

OHZ

K6T0808V1D, K6T0808U1D Family

CMOS SRAM

Revision 1.0

November 1997

TIMING WAVEFORM OF WRITE CYCLE(2)

(CS

Controlled)

Address

WR(4)

AS(3)

Data Valid

Data in

Data out

High-Z

CW(2)

WP(1)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE

going low : A write end at the earliest transition among CS going high and WE going high, t

is measured from the begining of write

to the end of write.

2. t

is measured from the CS going low to end of write.

3. t

is measured from the address valid to the beginning of write.

4. t

is measured from the end of write to the address change. t

applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

4.5V

2.2V

CS
GND

Data Retention Mode

- 0.2V

SDR

RDR

TIMING WAVEFORM OF WRITE CYCLE(1)

(WE Controlled)

Address

CW(2)

WR(4)

WP(1)

WHZ

Data Undefined

Data Valid

Data in

Data out

AS(3)

K6T0808V1D, K6T0808U1D Family

CMOS SRAM

Revision 1.0

November 1997

PACKAGE DIMENSIONS

28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)

#28

1.00

0.10

0.039

0.004

.
4

.
3

.
0

.
1

13.40

0.20

0.528

0.008

#15

#14

+0.10

0.20

-0.05

+0.004

0.008

-0.002

0.55

0.0217

0.425

( )

0.017

MIN

0.05

0.002

MAX

1.20

0.047

.
0

.
3

#28

1.00

0.10

0.039

0.004

.
4

.
3

.
0

.
1

0.50

( )

0.020

11.80

0.10

0.465

0.004

0.45 ~0.75

0.018 ~0.030

13.40

0.20

0.528

0.008

#15

#14

+0.10

0.15

-0.05

+0.004

0.006

-0.002

0~8

0.425

( )

0.017

MIN

0.05

0.002

MAX

1.20

0.047

.
0

.
3

TYP

0.25

0.010

0.55

0.0217

+0.10

0.20

-0.05

+0.004

0.008

-0.002

28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)

0.50

( )

0.020

11.80

0.10

0.465

0.004

0.45 ~0.75

0.018 ~0.030

+0.10

0.15

-0.05

+0.004

0.006

-0.002

0~8

TYP

0.25

0.010

Units: millimeter(inch)

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K6T0808U1D-GF70