PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
1
Document Title
128K x8 bit Low Power CMOS Static RAM
Revision History
Revision No.
0.0
0.1
1.0
2.0
Remark
Design target
Preliminary
Final
Final
History
Initial draft
First revision
- Seperate read and write at I
CC
, I
CC1
I
CC =
I
CC1
Read : 15mA, Write : 35mA
Finalized
- Add 70ns speed bin for commercial product and 85ns speed
bin for industrial.
Revised
- Improved operating current
Add typical value.
I
CC
Read : 15mA
10mA(Remove write current)
I
CC2
: 90mA
60mA
- Speed bin change
Remove 45ns from commercial part
Remove 55ns and 100ns from industrial part.
Draft Date
November 22, 1995
April 15, 1996
September 5, 1996
November 5, 1997
The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
2
128K x8 bit Low Power CMOS Static RAM
GENERAL DESCRIPTION
The K6T1008C2C families are fabricated by SAMSUNG
s
advanced CMOS process technology. The families support
various operating temperature ranges and have various
package types for user flexibility of system design. The fami-
lies also support low data retention voltage for battery back-
up operation with low data retention current.
FEATURES
Process Technology: TFT
Organization: 128K x8
Power Supply Voltage: 4.5~5.5V
Low Data Retention Voltage: 2V(Min)
Three state output and TTL Compatible
Package Type: 32-DIP-600, 32-SOP-525,
32-TSOP1-0820F/R
PIN DESCRIPTION
PRODUCT FAMILY
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
K6T1008C2C-L
Commercial(0~70
C)
4.5~5.5V
55/70ns
50
A
10
A
60mA
32-DIP, 32-SOP
32-TSOP1-F/R
K6T1008C2C-B
K6T1008C2C-P
Industrial(-40~85
C)
70ns
50
A
15
A
32-SOP
32-TSOP1-F/R
K6T1008C2C-F
FUNCTIONAL BLOCK DIAGRAM
32-TSOP
Type1 - Reverse
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-TSOP
Type1 - Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N.C
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
32-DIP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-SOP
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Precharge circuit.
Memory array
1024 rows
128
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A0
A1
A2
A3
A9
A11
A10
A4
A5
A6
A7
A8
A12
A14
I/O
1
Data
cont
I/O
8
A13
A15
A16
V
CC
V
SS
CS1
WE
OE
Control
logic
CS2
Data
cont
Name
Function
Name
Function
CS
1
,CS
2
Chip Select Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable
Vcc
Power
WE
Write Enable Input
Vss
Ground
A
0
~A
16
Address Inputs
N.C
No Connection
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
3
PRODUCT LIST
Commercial Temperature Products(0~70
C)
Industrial Temperature Products(-40~85
C)
Part Name
Function
Part Name
Function
K6T1008C2C-DL55
K6T1008C2C-DL70
K6T1008C2C-DB55
K6T1008C2C-DB70
K6T1008C2C-GL55
K6T1008C2C-GL70
K6T1008C2C-GB55
K6T1008C2C-GB70
K6T1008C2C-TB55
K6T1008C2C-TB70
K6T1008C2C-RB55
K6T1008C2C-RB70
32-DIP, 55ns, L-pwr
32-DIP, 70ns, L-pwr
32-DIP, 55ns, LL-pwr
32-DIP, 70ns, LL-pwr
32-SOP, 55ns, L-pwr
32-SOP, 70ns, L-pwr
32-SOP, 55ns, LL-pwr
32-SOP, 70ns, LL-pwr
32-TSOP1-F, 55ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
32-TSOP1-R, 55ns, LL-pwr
32-TSOP1-R, 70ns, LL-pwr
K6T1008C2C-GP70
K6T1008C2C-GF70
K6T1008C2C-TF70
K6T1008C2C-RF70
32-SOP, 70ns, L-pwr
32-SOP, 70ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
32-TSOP1-R, 70ns, LL-pwr
FUNCTIONAL DESCRIPTION
1. X means don
t care(Must be in high or low status.)
CS
1
CS
2
OE
WE
I/O
Pin
Mode
Power
H
X
1)
X
1)
X
1)
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disable
Active
L
H
L
H
Dout
Read
Active
L
H
X
1)
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 to 7.0
V
-
Voltage on Vcc supply relative to Vss
V
CC
-0.5 to 7.0
V
-
Power Dissipation
P
D
1.0
W
-
Storage temperature
T
STG
-65 to 150
C
-
Operating Temperature
T
A
0 to 70
C
K6T1008C2C-L
-40 to 85
C
K6T1008C2C-P
Soldering temperature and time
T
SOLDER
260
C, 10sec (Lead Only)
-
-
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
4
RECOMMENDED DC OPERATING CONDITIONS
1)
Note
1. Commercial Product : T
A
=0 to 70
C and Industrial Product :T
A
=-40 to 85
C, otherwise specified.
2. Overshoot : Vcc+3.0V for
30ns pulse width.
3. Undershoot : -3.0V for
30ns pulse width.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.5
2)
V
Input low voltage
V
IL
-0.5
3)
-
0.8
V
CAPACITANCE
1
)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled not, 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
6
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
8
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or
WE=V
IL,
V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IH
or V
IL
, Read
-
5
10
mA
Average operating current
I
CC1
Cycle time=1
s, 100% duty, I
IO
=0mA, CS
1
0.2V,
CS
2
V
CC
-0.2V, V
IN
0.2V or V
IN
V
CC
-0.2V
Read
-
2
5
mA
Write
20
35
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA, CS1=V
IL
, CS2=V
IH,
V
IN
=V
IL
or V
IH
-
45
60
mA
Output low voltage
V
OL
I
OL
=2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS
1
=V
IH,
CS
2
=V
IL,
Other input=V
IL
or V
IH
-
-
3
mA
Standby
Current
(CMOS)
K6T1008C2C-L
I
SB1
CS
1
Vcc-0.2V, CS2
Vcc-0.2V
or CS
2
0.2V
Other input =0~Vcc
Low Power
-
1
50
A
K6T1008C2C-B
Low Low Power
-
0.3
10
K6T1008C2C-P
Low power
-
1
50
K6T1008C2C-F
Low Low Power
-
0.3
15
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
5
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
AC CHARACTERISTICS
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO1,
t
CO2
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
25
ns
Output disable to high-Z output
t
OHZ
0
20
0
25
ns
Output hold from address change
t
OH
10
-
10
-
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
50
-
ns
Write recovery time
t
WR1,
t
WR2
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
1. CS
1
Vcc-0.2v, CS
2
Vcc-0.2V or CS
2
0.2V
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
1)
Vcc-0.2V, CS
2
Vcc-0.2V or CS
2
0.2V
2.0
-
5.5
V
Data retention current
I
DR
Vcc=3.0V, CS
1
Vcc-0.2V,
CS2
Vcc-0.2V or CS
2
0.2V
K6T1008C2C-L
-
1
20
A
K6T1008C2C-B
-
1
10
K6T1008C2C-P
-
-
25
K6T1008C2C-F
-
-
10
Data retention set-up
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
6
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS
1
=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
1
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ(1,2)
t
RC
t
CO2
t
OE
t
CO1
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
7
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
1
t
CW(2)
t
WR(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
CS
1
t
WC
t
WR(4)
t
AS(3)
CS
2
t
CW(2)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
CS
2
t
WC
t
AW
t
AS(3)
t
CW(2)
t
WP(1)
t
AW
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
8
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
4.5V
2.2V
V
DR
CS
1
GND
Data Retention Mode
CS
1
V
CC
-0.2V
t
SDR
t
RDR
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
2
Controlled)
Address
CS
1
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition among CS
1
goes low,
CS
2
going high and WE going low : A write end at the earliest transition among CS
1
going high, CS
2
going low and WE going high,
t
WP
is measured from the begining of write to the end of write.
2. t
CW
is measured from the CS
1
going low or CS
2
going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR(1)
applied in case a write ends as CS
1
or WE going high t
WR(2)
applied in case a write ends as CS
2
going to low.
CS
2
t
CW(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
AS(3)
t
WC
CS
2
controlled
V
CC
4.5V
0.4V
V
DR
CS
2
GND
Data Retention Mode
t
SDR
t
RDR
CS
2
0.2V
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
9
PACKAGE DIMENSIONS
Units: millimeter(inch)
0~15
1.91
#1
32 DUAL INLINE PACKAGE (600mil)
#32
13.60
0.20
0.535
0.008
41.91
0.20
1.650
0.008
( )
0.075
1
5
.
2
4
0
.
6
0
0
+0.10
MAX
42.31
1.666
0.25
-0.05
+0.004
0.010
-0.002
2.54
0.100
MAX
3.81
0.20
0.150
0.008
5.08
0.200
MIN
0.015
0.38
0.130
0.012
3.30
0.30
#16
#17
1.52
0.10
0.060
0.004
0.46
0.10
0.018
0.004
32 PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8
#32
20.47
0.20
0.806
0.008
MAX
20.87
0.822
MAX
2.74
0.20
0.108
0.008
3.00
0.118
MIN
0.002
0.05
0.004 MAX
0.10 MAX
#1
0.71
( )
0.028
1
3
.
3
4
0
.
5
2
5
11.43
0.20
0.450
0.008
0.80
0.20
0.031
0.008
+0.10
0.20
-0.05
+0.004
0.008
-0.002
14.12
0.30
0.556
0.012
#17
#16
1.27
0.050
+0.100
0.41
-0.050
+0.004
0.016
-0.002
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
10
32 THIN SMALL OUTLINE PACKAGE TYPE1 (0820F)
#32
1.00
0.10
0.039
0.004
MAX
8.40
0.331
0
.
1
0
0
.
0
0
4
#1
0.50
( )
0.020
18.40
0.10
0.724
0.004
0.45 ~0.75
0.018 ~0.030
20.00
0.20
0.787
0.008
#17
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
#16
PACKAGE DIMENSIONS
Units: millimeter(inch)
32 THIN SMALL OUTLINE PACKAGE TYPE1 (0820R)
#32
1.00
0.10
0.039
0.004
M
A
X
8
.
4
0
0
.
3
3
1
#1
0.50
( )
0.020
18.40
0.10
0.724
0.004
0.45 ~0.75
0.018 ~0.030
20.00
0.20
0.787
0.008
#17
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
#16
M
A
X
0
.
1
0
0
.
0
0
4
M
A
X
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