K6T1008V2C, K6T1008U2C Family

CMOS SRAM

Revision 2.0

November 1997

Document Title

128K x8 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Remark

Preliminary

Final

History

Initial draft

Finalize
- Increased I

, I

Commercial part = 10

Industrial part = 20

Revise
- Change speed bin
KM68V1000C Family: 70/85ns

70/100ns

KM68U1000C Family: 70/100ns

85/100ns

- Improved operating current: 40mA

35mA

- Improved power dissipation
P

: 0.7W

1.0W

- Improved standby current
Extended/Industrial: 20

- VIL: 0.4V

0.6V

Draft Data

July 3, 1996

December 16, 1996

November 25, 1997

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision No.

0.0

1.0

2.0

K6T1008V2C, K6T1008U2C Family

CMOS SRAM

Revision 2.0

November 1997

128K x8 bit Low Power and Low Voltage CMOS Static RAM

GENERAL DESCRIPTION

The K6T1008V2C and K6T1008U2C families are fabricated by
SAMSUNG

s advanced CMOS process technology. The fami-

lies support various operating temperature ranges and have

various package types for user flexibility of system design. The

families also supports low data retention voltage for battery

back-up operation with low data retention current.

FEATURES

Process Technology: 0.4

m CMOS

Organization: 128K x8

Power Supply Voltage:

K6T1008V2C family: 3.0~3.6V
K6T1008U2C family: 2.7~3.3V

Low Data Retention Voltage: 2V(Min)

Three state output and TTL Compatible

Package Type: 32-SOP-525, 32-TSOP1-0820F/R,

32-TSOP1-0813.4F/R

Name

Function

, CS

Chip Select Inputs

Output Enable Input

Write Enable Input

Address Inputs

I/O

~I/O

Data Inputs/Outputs

Vcc

Power

Vss

Ground

N.C

No Connection

PRODUCT FAMILY

Product Family

Operating Temperature

Vcc Range

Speed

Power Dissipation

PKG Type

Standby

SB1

, Max)

Operating

CC2

, Max)

K6T1008V2C-B

Commercial(0~70

3.0~3.6V

70/100ns

35mA

32-SOP
32-TSOP1-F/R
32-sTSOP1-F/R

K6T1008U2C-B

2.7~3.3V

85/100ns

K6T1008V2C-D

Extended(-25~85

3.0~3.6V

70/100ns

K6T1008U2C-D

2.7~3.3V

85/100ns

K6T1008V2C-F

Industrial(-40~85

3.0~3.6V

70/100ns

K6T1008U2C-F

2.7~3.3V

85/100ns

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTION

32-TSOP

Type1-Reverse

A11

A13

CS2

A15

VCC

A16

A14

A12

A7
A6
A5
A4

OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3

32-

TSOP

Type1-Forward

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

N.C

A16

A14

A12

I/O1

I/O2

I/O3

VSS

VCC

A15

CS2

A13

A11

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

32-SOP

A11

A13

CS2

VCC

A15

A16

A14

A12

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

32-TSOP

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array
1024 rows
128

8 columns

I/O Circuit

Column select

Clk gen.

Row
select

A10 A0

A11

I/O

Data
cont

I/O

A12

A14

A13

A15

A16

CS1

Control
logic

CS2

32-

TSOP

K6T1008V2C, K6T1008U2C Family

CMOS SRAM

Revision 2.0

November 1997

PRODUCT LIST

Commercial Temperature Products

(0~70

Extended Temperature Products

(-25~85

Industrial Temperature Products

(-40~85

Part Name

Function

Part Name

Function

Part Name

Function

K6T1008V2C-GB70
K6T1008V2C-GB10
K6T1008V2C-TB70
K6T1008V2C-TB10
K6T1008V2C-RB70
K6T1008V2C-RB10

K6T1008U2C-GB85
K6T1008U2C-GB10
K6T1008U2C-TB85
K6T1008U2C-TB10
K6T1008U2C-RB85
K6T1008U2C-RB10

K6T1008V2C-YB70
K6T1008V2C-YB10
K6T1008V2C-NB70
K6T1008V2C-NB10

K6T1008U2C-YB85
K6T1008U2C-YB10
K6T1008U2C-NB85
K6T1008U2C-NB10

32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-TSOP R, 100ns, 3.3V

32-SOP, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-TSOP R, 100ns, 3.0V

32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-sTSOP R, 70ns, 3.3V
32-sTSOP R, 100ns, 3.3V

32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V
32-sTSOP R, 85ns, 3.0V
32-sTSOP R, 100ns, 3.0V

K6T1008V2C-GD70
K6T1008V2C-GD10
K6T1008V2C-TD70
K6T1008V2C-TD10
K6T1008V2C-RD70
K6T1008V2C-RD10

K6T1008U2C-GD85
K6T1008U2C-GD10
K6T1008U2C-TD85
K6T1008U2C-TD10
K6T1008U2C-RD85
K6T1008U2C-RD10

K6T1008V2C-YD70
K6T1008V2C-YD10
K6T1008V2C-ND70
K6T1008V2C-ND10

K6T1008U2C-YD85
K6T1008U2C-YD10
K6T1008U2C-ND85
K6T1008U2C-ND10

32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-TSOP R, 100ns, 3.3V

32-SOP, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-TSOP R, 100ns, 3.0V

32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-sTSOP R, 70ns, 3.3V
32-sTSOP R, 100ns, 3.3V

32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V
32-sTSOP R, 85ns, 3.0V
32-sTSOP R, 100ns, 3.0V

K6T1008V2C-GF70
K6T1008V2C-GF10
K6T1008V2C-TF70
K6T1008V2C-TF10
K6T1008V2C-RF70
K6T1008V2C-RF10

K6T1008U2C-GF85
K6T1008U2C-GF10
K6T1008U2C-TF85
K6T1008U2C-TF10
K6T1008U2C-RF85
K6T1008U2C-RF10

K6T1008V2C-YF70
K6T1008V2C-YF10
K6T1008V2C-NF70
K6T1008V2C-NF10

K6T1008U2C-YF85
K6T1008U2C-YF10
K6T1008U2C-NF85
K6T1008U2C-NF10

32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-TSOP R, 100ns, 3.3V

32-SOP, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-TSOP R, 100ns, 3.0V

32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-sTSOP R, 70ns, 3.3V
32-sTSOP R, 100ns, 3.3V

32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V
32-sTSOP R, 85ns, 3.0V
32-sTSOP R, 100ns, 3.0V

FUNCTIONAL DESCRIPTION

1. X means don

t care(Must be in high or low status.)

I/O

Pin

Mode

Power

High-Z

Deselected

Standby

High-Z

Deselected

Standby

High-Z

Output Disabled

Active

Dout

Read

Active

Din

Write

Active

ABSOLUTE MAXIMUM RATINGS

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item

Symbol

Ratings

Unit

Remark

Voltage on any pin relative to Vss

OUT

-0.5 to V

+0.5

Voltage on Vcc supply relative to

-0.3 to 4.6

Power Dissipation

1.0

Storage temperature

STG

-65 to 150

Operating Temperature

0 to 70

K6T1008V2C-B/K6T1008U2C-B

-25 to 85

K6T1008V2C-D/K6T1008U2C-D

-40 to 85

K6T1008V2C-F/K6T1008U2C-F

Soldering temperature and time

SOLDER

260

C, 10sec (Lead Only)

K6T1008V2C, K6T1008U2C Family

CMOS SRAM

Revision 2.0

November 1997

CAPACITANCE

(f=1MHz, TA=25

. Capacitance is sampled, not 100% tested

Item

Symbol

Test Condition

Min

Max

Unit

Input capacitance

=0V

Input/Output capacitance

=0V

RECOMMENDED DC OPERATING CONDITIONS

1. Commercial Product: T

=0 to 70

C, unless otherwise specified

Extended Product: T

=-25 to 85

C, unless otherwise specified

Industrial Product: T

=-40 to 85

C, unless otherwise specified

2. Overshoot: V

+3.0V in case of pulse width

30ns

3. Undershoot: -3.0V in case of pulse width

30ns

4. Overshoot and undershoot is sampled, not 100% tested.

Item

Symbol

Product

Min

Typ

Max

Unit

Supply voltage

Vcc

K6T1008V2C Family
K6T1008U2C Family

3.0
2.7

3.3
3.0

3.6
3.3

Ground

Vss

All Family

Input high voltage

K6T1008V2C, K6T1008U2C Family

2.2

Vcc+0.3

Input low voltage

K6T1008V2C, K6T1008U2C Family

-0.3

0.6

DC AND OPERATING CHARACTERISTICS

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Input leakage current

=Vss to Vcc

-1

Output leakage current

or CS

or OE=V

or WE=V

IL,

=Vss to Vcc

-1

Operating power supply

=0mA, CS

, CS

, V

or V

, Read

Average operating current

CC1

Cycle time=1

s, 100% duty, I

=0mA,

0.2V, CS

-0.2V, V

0.2V or V

-0.2V

Read

1.5

Write

CC2

Cycle time=Min, 100% duty, I

=0mA, CS

, CS

, V

or V

Output low voltage

=2.1mA

0.4

Output high voltage

=-1.0mA

2.2

Standby Current(TTL)

IH,

Other inputs=V

or V

0.3

Standby Current(CMOS)

SB1

Vcc-0.2V, CS

Vcc-0.2V or CS

0.2V, Other inputs=0~Vcc

0.3

K6T1008V2C, K6T1008U2C Family

CMOS SRAM

Revision 2.0

November 1997

1. Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS

(Test Load and Input/Output Reference)

Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C

=100pF+1TTL

AC CHARACTERISTICS

(Commercial product:T

=0 to 70

C, Extended product:T

=-25 to 85

C, Industrial product: T

=-40 to 85

K6T1008V2C Family: Vcc=3.0~3.6V, K6T1008U2C Family: Vcc=2.7~3.3V)

Parameter List

Symbol

Speed Bins

Units

70ns

85ns

100ns

Min

Max

Min

Max

Min

Max

Read

Read cycle time

100

Address access time

100

Chip select to output

CO1

, t

CO2

100

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

OLZ

Chip disable to high-Z output

Output disable to high-Z output

OHZ

Output hold from address change

Write

Write cycle time

100

Chip select to end of write

Address set-up time

Address valid to end of write

Write pulse width

Write recovery time

Write to output high-Z

WHZ

Data to write time overlap

Data hold from write time

End write to output low-Z

DATA RETENTION CHARACTERISTICS

1. CS

Vcc-0.2V

-0.2V, or CS

0.2V

Item

Symbol

Test Condition

Min

Typ

Max

Unit

Vcc for data retention

Vcc-0.2V

2.0

3.6

Data retention current

Vcc=3.0V, CS

Vcc-0.2V

-0.2V, or CS

0.2V

0.3

Data retention set-up time

SDR

See data retention waveform

Recovery time

RDR

K6T1008V2C, K6T1008U2C Family

CMOS SRAM

Revision 2.0

November 1997

Address

Data Out

Previous Data Valid

Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1)

(Address Controlled

CS=OE=V

, WE=V

)

TIMING WAVEFORM OF READ CYCLE(2)

(WE=V

)

Data Valid

High-Z

Address

Data out

NOTES (READ CYCLE)

and

OHZ

are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition,

(Max.) is less than

(Min.) both for a given device and from device to device

interconnection.

OLZ

OHZ

HZ(1,2)

CO2

CO1

K6T1008V2C, K6T1008U2C Family

CMOS SRAM

Revision 2.0

November 1997

DATA RETENTION WAVE FORM

controlled

3.0/2.7V

2.2V

GND

Data Retention Mode

-0.2V

SDR

RDR

TIMING WAVEFORM OF WRITE CYCLE(3)

(CS

Controlled)

Address

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS

, a high CS

and a low WE. A write begins at the latest transition among CS

goes low,

going high and WE going low: A write end at the earliest transition among CS

going high, CS

going low and WE going high,

is measured from the beginning of write to the end of write.

2. t

is measured from the CS

going low or CS

going high to the end of write.

3. t

is measured from the address valid to the beginning of write.

4. t

is measured from the end of write to the address change. t

WR(1)

applied in case a write ends as CS

or WE going high t

WR(2)

applied in case a write ends as CS

going to low.

CW(2)

Data in

Data Valid

Data out

High-Z

CW(2)

WR(4)

WP(1)

AS(3)

controlled

3.0/2.7V

0.4V

GND

Data Retention Mode

SDR

RDR

1. 3.0V for K6T1008V2C Family, 2.7V for K6T1008U2C Family

0.2V

K6T1008V2C, K6T1008U2C Family

CMOS SRAM

Revision 2.0

November 1997

#32

1.00

0.10

0.039

0.004

.
4

.
3

.
0

.
1

13.40

0.20

0.528

0.008

#17

#16

+0.10

0.20

-0.05

+0.004

0.008

-0.002

0.50

0.0197

0.25

( )

0.010

MIN

0.05

0.002

MAX

1.20

0.047

.
0

.
3

#32

1.00

0.10

0.039

0.004

.
4

.
3

0.50

( )

0.020

11.80

0.10

0.465

0.004

0.45~0.75

0.018~0.030

13.40

0.20

0.528

0.008

#17

#16

+0.10

0.15

-0.05

+0.004

0.006

-0.002

0~8

+0.10

0.20

-0.05

+0.004

0.008

-0.002

0.50

0.0197

0.25

( )

0.010

MIN

0.05

0.002

MAX

1.20

0.047

.
0

.
3

TYP

0.25

0.010

.
0

.
1

0.50

( )

0.020

11.80

0.10

0.465

0.004

0.45~0.75

0.018~0.030

+0.10

0.15

-0.05

+0.004

0.006

-0.002

0~8

TYP

0.25

0.010

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)

PACKAGE DIMENSIONS

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)

Units: millimeter(inch)

K6T1008V2C, K6T1008U2C Family

CMOS SRAM

Revision 2.0

November 1997

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

#32

1.00

0.10

0.039

0.004

MAX

8.40

0.331

.
1

.
0

0.50

( )

0.020

18.40

0.10

0.724

0.004

0.45 ~0.75

0.018 ~0.030

20.00

0.20

0.787

0.008

#17

+0.10

0.15

-0.05

+0.004

0.006

-0.002

0~8

+0.10

0.20

-0.05

+0.004

0.008

-0.002

0.50

0.0197

0.25

( )

0.010

MIN

0.05

0.002

MAX

1.20

0.047

.
0

.
3

TYP

0.25

0.010

#16

PACKAGE DIMENSIONS

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820R)

#32

1.00

0.10

0.039

0.004

.
4

.
3

.
0

.
1

0.50

( )

0.020

18.40

0.10

0.724

0.004

0.45 ~0.75

0.018 ~0.030

20.00

0.20

0.787

0.008

#17

+0.10

0.15

-0.05

+0.004

0.006

-0.002

0~8

+0.10

0.20

-0.05

+0.004

0.008

-0.002

0.50

0.0197

0.25

( )

0.010

MIN

0.05

0.002

MAX

1.20

0.047

.
0

.
3

TYP

0.25

0.010

#16

Units: millimeter(inch)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K6T1008V2C-RB70

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K6T1008V2C-RB70