CMOS SRAM
K6T2008S2M Family
Revision 1.0
August 1998
Document Title
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0.0
1.0
Remark
Preliminary
Final
History
Initial draft
Finalize
Draft Date
September 30, 1997
August 27, 1998
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
CMOS SRAM
K6T2008S2M Family
Revision 1.0
August 1998
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The K6T2008S2M families are fabricated by SAMSUNG
s
advanced CMOS process technology. The families support
various operating temperature ranges and various package
type for user flexibility of system design. The families also sup-
port low data retention voltage for battery back-up operation
with low data retention current.
FEATURES
Process Technology: TFT
Organization: 256Kx8
Power Supply Voltage
K6T2008S2M Family: 2.3~2.7V
Low Data Retention Voltage: 2V(Min)
Three state output and TTL Compatible
Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F
PIN DESCRIPTION
Name
Function
Name
Function
CS
1
,CS
2
Chip Select Input
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
A
0
~A
17
Address Inputs
N.C.
No Connection
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
K6T2008S2M-B
Commercial(0~70
C)
2.3~2.7V
120
1)
/150ns
10
A
25mA
32-TSOP1-F
32-sTSOP1-F
K6T2008S2M-F
Industrial(-40~85
C)
15
A
FUNCTIONAL BLOCK DIAGRAM
A11
A9
A8
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-
S
TSOP
Type1 - Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-TSOP
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
A12
Precharge circuit.
Memory array
1024 rows
256
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A0 A1 A2 A4 A5
A7
A6
A3
A8
A9
A10
A11
A13
A15
CS1
CS2
WE
I/O
1
Data
cont
Data
cont
OE
I/O
8
A14
A17
A16
Control
Logic
Vcc
Vss
CMOS SRAM
K6T2008S2M Family
Revision 1.0
August 1998
PRODUCT LIST
Note : LL - Low Low Standby Current
Commercial Temperature Products(0~70
C)
Industrial Temperture Products(-40~85
C)
Part Name
Function
Part Name
Function
K6T2008S2M-TB12
K6T2008S2M-TB15
K6T2008S2M-YB12
K6T2008S2M-YB15
32-TSOP F, 120ns, 2.3~2.7V, LL
32-TSOP F, 150ns, 2.3~2.7V, LL
32-sTSOP F, 120ns, 2.3~2.7V, LL
32-sTSOP F, 150ns, 2.3~2.7V, LL
K6T2008S2M-TF12
K6T2008S2M-TF15
K6T2008S2M-YF12
K6T2008S2M-YF15
32-TSOP F, 120ns, 2.3~2.7V, LL
32-TSOP F, 150ns, 2.3~2.7V, LL
32-sTSOP F, 120ns, 2.3~2.7V, LL
32-sTSOP F, 150ns, 2.3~2.7V, LL
FUNCTIONAL DESCRIPTION
1. X means don
t care (Must be in high or low states)
CS
1
CS
2
OE
WE
I/O
Mode
Power
H
X
1)
X
1)
X
1)
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
X
1)
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1
)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.5 to V
CC
+0.5
V
-
Voltage on Vcc supply relative to Vss
V
CC
-0.3 to 4.6
V
-
Power Dissipation
P
D
1
W
-
Storage temperature
T
STG
-65 to 150
C
-
Operating Temperature
T
A
0 to 70
C
K6T2008S2M-L
-40 to 85
C
K6T2008S2M-P
Soldering temperature and time
T
SOLDER
260
C, 10sec (Lead Only)
-
-
CMOS SRAM
K6T2008S2M Family
Revision 1.0
August 1998
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. Commercial Product : T
A
=0 to 70
C, otherwise specified
Industrial Product : T
A
=-40 to 85
C, otherwise specified
2. Overshoot : Vcc+1.0V in case of pulse width
20ns
3. Undershoot : -1.0V in case of pulse width
20ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Product
Min
Typ
Max
Unit
Supply voltage
Vcc
K6T2008S2M Family
2.3
2.5
2.7
V
Ground
Vss
All Family
0
0
0
V
Input high voltage
V
IH
K6T2008S2M Family
2.0
-
Vcc+0.3
2)
V
Input low voltage
V
IL
K6T2008S2M Family
-0.3
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
1. Industrial product=15
A
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply
I
CC
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL,
Read
-
-
2
mA
Average operating current
I
CC1
Cycle time=1
s, 100% duty, I
IO
=0mA
CS
1
0.2V, CS
2
Vcc-0.2V, V
IN
0.2V or V
IN
Vcc-0.2V
Read
-
-
3
mA
Write
-
-
10
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IL
or V
IH
-
-
25
mA
Output low voltage
V
OL
I
OL
=0.5mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-0.5mA
2.0
-
-
V
Standby Current(TTL)
I
SB
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs=V
IL
or V
IH
-
-
0.3
mA
Standby Current (CMOS)
I
SB1
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V or CS
2
0
.2V, Other inputs=0~Vcc
-
-
10
1)
A
CMOS SRAM
K6T2008S2M Family
Revision 1.0
August 1998
AC CHARACTERISTICS
(Vcc=2.3~2.7V, Commercial products:T
A
=0 to 70
C, Industrial products:T
A
=-40 to 85
C)
1. The parameter is measured with 30pF test load.
Parameter List
Symbol
Speed Bins
Units
120ns
1)
150ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
120
-
150
-
ns
Address access time
t
AA
-
120
-
150
ns
Chip select to output
t
CO1,
t
CO2
-
120
-
150
ns
Output enable to valid output
t
OE
-
60
-
75
ns
Chip select to low-Z output
t
LZ
20
-
20
-
ns
Output enable to low-Z output
t
OLZ
20
-
20
-
ns
Chip disable to high-Z output
t
HZ
-
35
0
40
ns
Output disable to high-Z output
t
OHZ
-
35
0
40
ns
Output hold from address change
t
OH
15
-
15
-
ns
Write
Write cycle time
t
WC
120
-
150
-
ns
Chip select to end of write
t
CW1,
t
CW2
100
-
120
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
100
-
120
-
ns
Write pulse width
t
WP
80
-
100
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
30
0
40
ns
Data to write time overlap
t
DW
50
-
60
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) : C
L
=100pF+1TTL
C
L
=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1. CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
Contrlled) or CS
2
0.2V(CS
2
Controlled)
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
Vcc-0.2V
1)
2.0
-
3.3
V
Data retention current
I
DR
Vcc=2.0V, CS
1
Vcc-0.2V or CS
2
0.2V
-
-
10
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
CMOS SRAM
K6T2008S2M Family
Revision 1.0
August 1998
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL,
WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
1
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ(1,2)
t
RC
t
CO2
t
OE
t
CO1
CMOS SRAM
K6T2008S2M Family
Revision 1.0
August 1998
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
1
t
CW(2)
t
WR(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
CS
1
t
WC
t
WR(4)
t
AS(3)
CS
2
t
CW(2)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
CS
2
t
WC
t
AW
t
AS(3)
t
CW(2)
t
WP(1)
t
AW
CMOS SRAM
K6T2008S2M Family
Revision 1.0
August 1998
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
2.3V
2.2V
V
DR
CS
1
GND
Data Retention Mode
CS
1
V
CC
- 0.2V
t
SDR
t
RDR
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
1
Controlled)
Address
CS
1
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition among CS
1
goes low,
CS
2
going high and WE going low : A write end at the earliest transition among CS
1
going high, CS
2
going low and WE going high,
t
WP
is measured from the begining of write to the end of write.
2. t
CW
is measured from the CS
1
going low or CS
2
going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR(1)
applied in case a write ends as CS
1
or WE going high t
WR(2)
applied in case a write ends as CS
2
going to low.
CS
2
t
CW(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
AS(3)
t
WC
CS
2
controlled
V
CC
2.3V
0.4V
V
DR
CS
2
GND
Data Retention Mode
t
SDR
t
RDR
CS
2
0.2V
CMOS SRAM
K6T2008S2M Family
Revision 1.0
August 1998
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
#32
1.00
0.10
0.039
0.004
MAX
8.40
0.331
0
.
1
0
0
.
0
0
4
#1
0.50
( )
0.020
18.40
0.10
0.724
0.004
0.45 ~0.75
0.018 ~0.030
20.00
0.20
0.787
0.008
#17
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
#16
PACKAGE DIMENSIONS
Units: millimeter(Inch)
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
1.00
0.10
0.039
0.004
MAX
8.40
0.331
0
.
1
0
0
.
0
0
4
#1
0.50
( )
0.020
11.80
0.10
0.465
0.004
0.45 ~0.75
0.018 ~0.030
13.40
0.10
0.528
0.008
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
#16
#32
#17
M
A
X
M
A
X
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