CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
Document Title
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0.0
1.0
2.0
2.01
Remark
Advance
Final
Final
Final
History
Design target
Finalize
Revised
- Add FBGA type package
Errata correction
- Removed 'TTL Compatible' from Features
Draft Data
May 26, 1998
October 8, 1998
July 21, 1999
October 24, 2001
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The K6T2008V2A and K6T2008U2A families are fabricated by
SAMSUNG
s advanced CMOS process technology. The fam-
ily support various operating temperature ranges and have
various package types for user flexibility of system design. The
family also support low data retention voltage for battery back-
up operation with low data retention current.
FEATURES
Process Technology: TFT
Organization: 256Kx8
Power Supply Voltage
K6T2008V2A Family: 3.0V~3.6V
K6T2008U2A Family: 2.7V~3.3V
Low Data Retention Voltage: 2V(Min)
Three State Outputs
Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F
48-FBGA-6.00x7.00
PIN DESCRIPTION
Name
Function
Name
Function
CS
1
,CS
2
Chip Select Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
A
0
~A
17
Address Inputs
NC
No Connection
PRODUCT FAMILY
1. The parameters are tested with 30pF test load
2. K6T2008V2A Family = 35mA
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(I
CC2,
Max)
K6T2008V2A-B
Commercial(0~70
C)
3.0~3.6V
70/85ns
10
A
30mA
2)
32-TSOP1-0820F
32-TSOP1-0813.4F
48-FBGA-6.00x7.00
K6T2008U2A-B
2.7~3.3V
70
1)
/85/100ns
K6T2008V2A-F
Industrial(-40~85
C)
3.0~3.6V
70
1)
/85/100ns
15
A
K6T2008U2A-F
2.7~3.3V
FUNCTIONAL BLOCK DIAGRAM
A11
A9
A8
A13
WE
CS2
A15
V
CC
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-sTSOP1
Type - Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
A2
Precharge circuit.
Memory array
1024 rows
256
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A0
A1 A17 A6 A5
A3
A4
A16
A15
A14
A13
A12
A11
A9
I/O
1
Data
cont
Data
cont
I/O
8
A10
A8
A7
CS
1
WE
OE
CS
2
Control
logic
32-TSOP1
48-FBGA: Top View (Ball Down)
A0
A1
CS2
A3
A6
A8
I/O5
A2
WE
A4
A7
I/O1
I/O6
NC
A5
I/O2
Vss
Vcc
Vcc
Vss
I/O7
NC
A17
I/O3
I/O8
OE
CS1
A16
A15
I/O4
A9
A10
A11
A12
A13
A14
1
2
3
4
5
6
A
B
C
D
E
F
G
H
CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
PRODUCT LIST
Commercial Temperature Products(0~70
C)
Industrial Temperature Products(-40~85
C)
Part Name
Function
Part Name
Function
K6T2008V2A-TB70
K6T2008V2A-TB85
K6T2008U2A-TB70
K6T2008U2A-TB85
K6T2008U2A-TB10
K6T2008V2A-YB70
K6T2008V2A-YB85
K6T2008U2A-YB70
K6T2008U2A-YB85
K6T2008U2A-YB10
32-TSOP1-F, 70ns, 3.3V,LL
32-TSOP1-F, 85ns, 3.3V,LL
32-TSOP1-F, 70ns, 3.0V, LL
32-TSOP1-F, 85ns, 3.0V, LL
32-TSOP1-F, 100ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.3V,LL
32-sTSOP1-F, 85ns, 3.3V,LL
32-sTSOP1-F, 70ns, 3.0V, LL
32-sTSOP1-F, 85ns, 3.0V, LL
32-sTSOP1-F, 100ns, 3.0V, LL
K6T2008V2A-TF70
K6T2008V2A-TF85
K6T2008V2A-TF10
K6T2008U2A-TF70
K6T2008U2A-TF85
K6T2008U2A-TF10
K6T2008V2A-YF70
K6T2008V2A-YF85
K6T2008V2A-YF10
K6T2008U2A-YF70
K6T2008U2A-YF85
K6T2008U2A-YF10
K6T2008V2A-FF70
K6T2008V2A-FF85
K6T2008U2A-FF70
K6T2008U2A-FF85
32-TSOP1-F, 70ns, 3.3V, LL
32-TSOP1-F, 85ns, 3.3V, LL
32-TSOP1-F, 100ns, 3.3V, LL
32-TSOP1-F, 70ns, 3.0V, LL
32-TSOP1-F, 85ns, 3.0V, LL
32-TSOP1-F, 100ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.3V, LL
32-sTSOP1-F, 85ns, 3.3V, LL
32-sTSOP1-F, 100ns, 3.3V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
32-sTSOP1-F, 85ns, 3.0V, LL
32-sTSOP1-F, 100ns, 3.0V, LL
48-FBGA, 70ns, 3.3V, LL
48-FBGA, 85ns, 3.3V, LL
48-FBGA, 70ns, 3.0V, LL
48-FBGA, 85ns, 3.0V, LL
FUNCTIONAL DESCRIPTION
1. X means don
t care (Must be in high or low states)
CS
1
CS
2
OE
WE
I/O
Mode
Power
H
X
1)
X
1)
X
1)
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
X
1)
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.5 to V
CC
+0.5
V
-
Voltage on Vcc supply relative to Vss
V
CC
-0.3 to 4.6
V
-
Power Dissipation
P
D
1.0
W
-
Storage temperature
T
STG
-65 to 150
C
-
Operating Temperature
T
A
0 to 70
C
K6T2008V2A-B, K6T2008U2A-B
-40 to 85
C
K6T2008V2A-F, K6T2008U2A-F
CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. Commercial Product: T
A
=0 to 70
C, otherwise specified
Industrial Produc t: T
A
=-40 to 85
C, otherwise specified
2. Overshoot: Vcc+2.0V in case of pulse width
30ns
3. Undershoot: -2.0V in case of pulse width
30ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Product
Min
Typ
Max
Unit
Supply voltage
Vcc
K6T2008V2A Family
K6T2008U2A Family
3.0
2.7
3.3
3.0
3.6
3.3
V
Ground
Vss
All Family
0
0
0
V
Input high voltage
V
IH
K6T2008V2A, K6T2008U2A Family
2.2
-
Vcc+0.3
V
Input low voltage
V
IL
K6T2008V2A, K6T2008U2A Family
-0.3
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
1. K6T2008V2A Family = 35mA
2. Industrial product = 15
A
Item
Symbol
Test Conditions
Min
Typ Max Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
-
-
5
mA
Average operating current
I
CC1
Cycle time=1
s,
100%duty, I
IO
=0mA, CS
1
0.2V, CS
2
Vcc-0.2V, V
IN
0.2V
or V
IN
V
CC
-0.2V
-
-
4
mA
I
CC2
Cycle time=Min, 100% duty,
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
-
25
30
1)
mA
Output low voltage
V
OL
I
OL
=2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs = V
IH
or V
IL
-
-
0.3
mA
Standby Current(CMOS)
I
SB1
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V or CS
2
0.2V, Other inputs=0~Vcc
-
0.2
10
2)
A
CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
AC CHARACTERISTICS
(K6T2008V2A Family: V
CC
=3.0~3.6V, K6T2008U2A Family: V
CC
=2.7~3.3V
Commercial Product: T
A
=0 to 70
C, Industrial Product: T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
70ns
85ns
100ns
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
85
-
100
-
ns
Address access time
t
AA
-
70
-
85
-
100
ns
Chip select to output
t
CO1
, t
CO2
-
70
-
85
-
100
ns
Output enable to valid output
t
OE
-
35
-
40
-
50
ns
Chip select to low-Z output
t
LZ
10
-
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
25
0
25
0
30
ns
Output disable to high-Z output
t
OHZ
0
25
0
25
0
30
ns
Output hold from address change
t
OH
10
-
15
-
15
-
ns
Write
Write cycle time
t
WC
70
-
85
-
100
-
ns
Chip select to end of write
t
CW
60
-
70
-
80
-
ns
Address set-up time
t
AS
0
-
0
-
0
-
ns
Address valid to end of write
t
AW
60
-
70
-
80
-
ns
Write pulse width
t
WP
55
-
60
-
70
-
ns
Write recovery time
t
WR
0
-
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
30
0
30
ns
Data to write time overlap
t
DW
30
-
35
-
40
-
ns
Data hold from write time
t
DH
0
-
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
5
-
ns
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1. CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or CS
2
0.2V(CS
2
controlled)
2. Industrial Prod
ucts = 15
A
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
Vcc-0.2V
1)
2.0
-
3.6
V
Data retention current
I
DR
Vcc=3.0V, CS
1
Vcc-0.2V
1)
-
0.2
10
2)
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS
1
=OE=V
IL
, CS
2
=WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
1
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ(1,2)
t
RC
t
CO2
t
OE
t
CO1
CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
CS
1
t
WC
t
WR(4)
t
AS(3)
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
CS
2
t
CW(2)
t
WP(1)
t
AW
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
1
t
CW(2)
t
WR(4)
CS
2
t
CW(2)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
WC
t
AW
t
AS(3)
CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
3.0/2.7V
1)
2.2V
V
DR
CS
1
GND
Data Retention Mode
CS
1
V
CC
- 0.2V
t
SDR
t
RDR
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
2
Controlled)
Address
CS
1
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition among CS
1
goes low,
CS
2
going high and WE going low : A write end at the earliest transition among CS
1
going high, CS
2
going low and WE going high,
t
WP
is measured from the begining of write to the end of write.
2. t
CW
is measured from the CS
1
going low or CS
2
going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
is applied in case a write ends with CS
1
or WE going high.
t
WR2
is applied in case a write ends with CS
2
going low.
CS
2
t
CW(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
AS(3)
t
WC
CS
2
controlled
V
CC
3.0/2.7V
1)
0.4V
V
DR
CS
2
GND
Data Retention Mode
t
SDR
t
RDR
1. 3.0V for K6T2008V2A Family, 2.7V for K6T2008U2A Family
CS
2
0.2V
CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
#32
1.00
0.10
0.039
0.004
MAX
8.40
0.331
0
.
1
0
M
A
X
0
.
0
0
4
M
A
X
#1
0.50
( )
0.020
18.40
0.10
0.724
0.004
0.45 ~0.75
0.018 ~0.030
20.00
0.20
0.787
0.008
#17
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
#16
PACKAGE DIMENSIONS
Units: millimeter(inch)
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
1.00
0.10
0.039
0.004
MAX
8.40
0.331
1
.
1
0
M
A
X
0
.
0
0
4
M
A
X
#1
0.50
( )
0.020
11.80
0.10
0.465
0.004
0.45 ~0.75
0.018 ~0.030
13.40
0.20
0.528
0.008
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
#16
#32
#17
CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
PACKAGE DIMENSIONS
Units: millimeters
C
1
/
2
6
5
4
3
2
1
A
B
C
D
E
F
G
H
C
B/2
B
C
1
B
C
Bottom View
Top View
D
E
2
E
1
E
C
Side View
0
.
8
5
/
T
y
p
.
0
.
2
5
/
T
y
p
.
A
Y
Detail A
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
B1
-
3.75
-
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.30
0.35
0.40
E
-
1.10
1.20
E1
-
0.85
-
E2
0.20
0.25
0.30
Y
-
-
0.08
0.50
0.50
B1
#A1
0
.
3
0
A1 INDEX MARK
Notes.
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.08(Max)
48 BALL FINE PITCH BALL GRID ARRAY(6.00X7.00)
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