K6T4008C1B Family
CMOS SRAM
Revision 3.0
September 1998
1
Document Title
512Kx8 bit Low Power CMOS Static RAM
Revision History
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision No.
0.0
0.1
1.0
2.0
3.0
Remark
Advance
Preliminary
Final
Final
Final
History
Initial Draft
Revise
- Changed Operating current by reticle revision
I
CC
at write : 35mA
45mA
I
CC1
at read/write : 15/35mA
10/45mA
Finalize
- Changed Operating current
I
CC1
at write : 45mA
40mA
I
CC
2; 90mA
80mA
- Change test load at 55ns : 100pF
50pF
Revise
- Change datasheet format
Revise
- Industrial product speed bin change:70/100ns
55/70ns
Draft Date
December 7, 1996
March 6, 1997
October 9, 1997
February 17, 1998
September 8, 1998
K6T4008C1B Family
CMOS SRAM
Revision 3.0
September 1998
2
512Kx8 bit Low Power CMOS Static RAM
GENERAL DESCRIPTION
The K6T4008C1B families are fabricated by SAMSUNG
s
advanced CMOS process technology. The families support
various operating temperature ranges and various package
types for user flexibility of system design. The family also
support low data retention voltage for battery back-up oper-
ation with low data retention current.
FEATURES
Process Technology: TFT
Organization: 512Kx8
Power Supply Voltage: 4.5~5.5V
Low Data Retention Voltage: 2V(Min)
Three state output and TTL Compatible
Package Type: 32-DIP-600, 32-SOP-525
32-TSOP2-400F/R
PIN DESCRIPTION
Pin Name
Function
WE
Write Enable Input
CS
Chip Select Input
OE
Output Enable Input
A
0
~A
18
Address Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
Vcc
Power
Vss
Ground
PRODUCT FAMILY
1. The parameter is measured with 50pF test load.
Product Family Operating Temperature Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
K6T4008C1B-L
Commercial (0~70
C
)
4.5~5.5V
55
1)
/70ns
100
A
20
A
80mA
32-DIP-600, 32-SOP-525
32-TSOP2-400F/R
K6T4008C1B-B
K6T4008C1B-P
Inderstrial (-40~85
C
)
100
A
50
A
32-SOP-525
32-TSOP2-400F/R
K6T4008C1B-F
FUNCTIONAL BLOCK DIAGRAM
32-DIP
32-SOP
(Forward)
32-TSOP2
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-TSOP2
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Reverse)
A18
A17
A17
A18
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
A3
Precharge circuit.
Memory array
1024 rows
512
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A9 A8 A13A17 A15
A11
A10
A18
A16
A14
A12
A7
A6
A4
I/O
1
Data
cont
Data
cont
I/O
8
A5
A1
A0
A2
CS
WE
OE
Control
logic
K6T4008C1B Family
CMOS SRAM
Revision 3.0
September 1998
3
PRODUCT LIST
Commercial Temperature Products(0~70
C)
Industrial Temperature Products(-40~85
C)
Part Name
Function
Part Name
Function
K6T4008C1B-DL55
K6T4008C1B-DB55
K6T4008C1B-DL70
K6T4008C1B-DB70
K6T4008C1B-GL55
K6T4008C1B-GB55
K6T4008C1B-GL70
K6T4008C1B-GB70
K6T4008C1B-VB55
K6T4008C1B-VB70
K6T4008C1B-MB55
K6T4008C1B-MB70
32-DIP, 55ns, L-pwr
32-DIP, 55ns, LL-pwr
32-DIP, 70ns, L-pwr
32-DIP, 70ns, LL-pwr
32-SOP, 55ns, L-pwr
32-SOP, 55ns, LL-pwr
32-SOP, 70ns, L-pwr
32-SOP, 70ns, LL-pwr
32-TSOP2-F, 55ns, LL-pwr
32-TSOP2-F, 70ns, LL-pwr
32-TSOP2-R, 55ns, LL-pwr
32-TSOP2-R, 70ns, LL-pwr
K6T4008C1B-GP55
K6T4008C1B-GF55
K6T4008C1B-GP70
K6T4008C1B-GF70
K6T4008C1B-VF55
K6T4008C1B-VF70
K6T4008C1B-MF55
K6T4008C1B-MF70
32-SOP, 55ns, L-pwr
32-SOP, 55ns, LL-pwr
32-SOP, 70ns, L-pwr
32-SOP, 70ns, LL-pwr
32-TSOP2-F, 55ns, LL-pwr
32-TSOP2-F, 70ns, LL-pwr
32-TSOP2-R, 55ns, LL-pwr
32-TSOP2-R, 70ns, LL-pwr
FUNCTIONAL DESCRIPTION
1. X means don
t care.( Must be in low or high state.)
CS
OE
WE
I/O Pin
Mode
Power
H
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
High-Z
Output disbaled
Active
L
L
H
Dout
Read
Active
L
X
1)
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.5 to 7.0
V
-
Voltage on Vcc supply relative to Vss
V
CC
-0.5 to 7.0
V
-
Power Dissipation
P
D
1.0
W
-
Storage temperature
T
STG
-65 to 150
C
-
Operating Temperature
T
A
0 to 70
C
K6T4008C1B-L/-B
-40 to 85
C
K6T4008C1B-P/-F
Soldering temperature and time
T
SOLDER
260
C, 10sec(Lead Only)
-
-
K6T4008C1B Family
CMOS SRAM
Revision 3.0
September 1998
4
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. Commercial Product: T
A
=0 to 70
C, otherwise specified
Industrial Product: T
A
=-40 to 85
C, otherwise specified
2. Overshoot: V
CC
+3.0V in case of pulse width
30ns
3. Undershoot: -3.0V in case of pulse width
30ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.5
2)
V
Input low voltage
V
IL
-0.5
3)
-
0.8
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS=V
IH
or OE=V
IH
or
WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply
I
CC
I
IO
=0mA, CS=V
IL
, V
IN
=V
IL
or V
IH
, Read
-
7.5
15
mA
Average operating current
I
CC1
Cycle time=1
s, 100% duty, I
IO
=0mA
CS
0.2V, V
IN
0.2V or V
IN
Vcc-0.2V
Read
-
4
10
mA
Write
-
27
40
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
-
65
80
mA
Output low voltage
V
OL
I
OL
=2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS=V
IH
, Other inputs = V
IL
or V
IH
-
-
3
mA
Standby Current(CMOS)
I
SB1
CS
Vcc-0.2V, Other inputs=0~Vcc
K6T4008C1B-L
-
2
100
A
K6T4008C1B-B
-
1
20
A
K6T4008C1B-P
-
2
100
A
K6T4008C1B-F
-
1
50
A
K6T4008C1B Family
CMOS SRAM
Revision 3.0
September 1998
5
AC CHARACTERISTICS
(Vcc=4.5~5.5V, Commercial product: T
A
=0 to 70
C, Industrial product: T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
55*ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
25
ns
Output disable to high-Z output
t
OHZ
0
20
0
25
ns
Output hold from address change
t
OH
10
-
10
-
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
50
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): C
L
=100pF+1TTL
C
L
=50pF+1TTL
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
Vcc-0.2V
2.0
-
5.5
V
Data retention current
I
DR
Vcc=3.0V, CS
Vcc-0.2V
K6T4008C1B-L
-
-
50
A
K6T4008C1B-B
-
-
15
K6T4008C1B-P
-
-
50
K6T4008C1B-F
-
-
20
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
K6T4008C1B Family
CMOS SRAM
Revision 3.0
September 1998
6
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ
t
RC
t
OE
t
CO1
K6T4008C1B Family
CMOS SRAM
Revision 3.0
September 1998
7
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
Controlled)
Address
CS
t
WC
t
WR(4)
t
AS(3)
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
t
CW(2)
t
WP(1)
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, t
WP
is measured from the begining of write
to the end of write.
2. t
CW
is measured from the CS going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
V
CC
4.5V
2.2V
V
DR
CS
GND
Data Retention Mode
CS
V
CC
- 0.2V
t
SDR
t
RDR
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
WC
t
AW
t
AS(3)
K6T4008C1B Family
CMOS SRAM
Revision 3.0
September 1998
8
PACKAGE DIMENSIONS
Units: millimeter(Inch)
0~15
1.91
#1
32 PIN DUAL INLINE PACKAGE (600mil)
#32
13.60
0.20
0.535
0.008
41.91
0.20
1.650
0.008
( )
0.075
1
5
.
2
4
0
.
6
0
0
+0.10
MAX
42.31
1.666
0.25
-0.05
+0.004
0.010
-0.002
2.54
0.100
MAX
3.81
0.20
0.150
0.008
5.08
0.200
MIN
0.015
0.38
0.130
0.012
3.30
0.30
#16
#17
1.52
0.10
0.060
0.004
0.46
0.10
0.018
0.004
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8
#32
20.47
0.20
0.806
0.008
MAX
20.87
0.822
MAX
2.74
0.20
0.108
0.008
3.00
0.118
MIN
0.002
0.05
0.004 MAX
0.10 MAX
#1
0.71
( )
0.028
1
3
.
3
4
0
.
5
2
5
11.43
0.20
0.450
0.008
0.80
0.20
0.031
0.008
+0.10
0.20
-0.05
+0.004
0.008
-0.002
14.12
0.30
0.556
0.012
#17
#16
1.27
0.050
+0.100
0.41
-0.050
+0.004
0.016
-0.002
K6T4008C1B Family
CMOS SRAM
Revision 3.0
September 1998
9
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8
#32
20.95
0.10
0.825
0.004
MAX
21.35
0.841
MAX
1.00
0.10
0.039
0.004
1.20
0.047
MIN
0.002
0.05
0.004 MAX
0.10 MAX
#1
0.95
( )
0.037
1
0
.
1
6
0
.
4
0
0
+0.10
0.15
-0.05
+0.004
0.006
-0.002
11.76
0.20
0.463
0.008
#17
#16
0.50
( )
0.020
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
1.27
0.050
0.40
0.10
0.016
0.004
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0~8
#32
#1
1
0
.
1
6
0
.
4
0
0
+0.10
0.15
-0.05
+0.004
0.006
-0.002
11.76
0.20
0.463
0.008
#17
#16
0.50
( )
0.020
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
20.95
0.10
0.825
0.004
MAX
21.35
0.841
MAX
1.00
0.10
0.039
0.004
1.20
0.047
MIN
0.002
0.05
0.004 MAX
0.10 MAX
0.95
( )
0.037
1.27
0.050
0.40
0.10
0.016
0.004
Units: millimeter(Inch)
PDF 
ZIP