K6T4008S1C Family
CMOS SRAM
Revision 1.0
April 1999
1
Document Title
512Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0.0
1.0
Remark
Preliminary
Final
History
Initial Draft
Finalize
Draft Data
June 15, 1998
April 17, 1999
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
K6T4008S1C Family
CMOS SRAM
Revision 1.0
April 1999
2
512Kx8 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The K6T4008S1C families are fabricated by SAMSUNG
s
advanced CMOS process technology. The families support
industrial operating temperature range and have various
package type for user flexibility of system design. The fami-
lies also support low data retention voltage for battery back-
up operation with low data retention current.
FEATURES
Process Technology: TFT
Organization: 512K
8
Power Supply Voltage
K6T4008S1C Family: 2.3~2.7V
Low Data Retention Voltage: 2V(Min)
Three state output and TTL Compatible
Package Type: 32-TSOP2-400F/R
32-TSOP1-0820F, 32-TSOP1-0813.4F
PIN DESCRIPTION
Name
Function
Name
Function
A
0
~A
18
Address Inputs
Vcc
Power
WE
Write Enable Input
Vss
Ground
CS
Chip Select Input
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable Input
PRODUCT FAMILY
1. The paramerter is measured with 30pF test load.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
K6T4008S1C-F
Industrial(-40~85
C)
2.3~2.7V
100*/120ns
15
A
16mA
32-TSOP2-F/R
32-TSOP1-F
32-sTSOP1-F
FUNCTIONAL BLOCK DIAGRAM
(Forward)
32-TSOP2
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-TSOP2
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Reverse)
A18
A17
A17
A18
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
A15
Precharge circuit.
Memory array
1024 rows
512
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A2 A3 A8 A9 A10
A13
A11
A0
A1
A4
A5
A6
A7
A14
CS
WE
I/O
1
Data
cont
Data
cont
OE
I/O
8
A12
A16
A18
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-TSOP1
32-
S
TSOP1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A17
Control
logic
(Forward)
K6T4008S1C Family
CMOS SRAM
Revision 1.0
April 1999
3
PRODUCT LIST
Industrial Temp Products(-40~85
C)
Part Name
Function
K6T4008S1C-VF10
K6T4008S1C-VF12
K6T4008S1C-MF10
K6T4008S1C-MF12
K6T4008S1C-TF10
K6T4008S1C-TF12
K6T4008S1C-YF10
K6T4008S1C-YF12
32-TSOP2-F, 100ns, 2.5V, LL
32-TSOP2-F, 120ns, 2.5V, LL
32-TSOP2-R, 100ns, 2.5V, LL
32-TSOP2-R, 120ns, 2.5V, LL
32-TSOP1-F, 100ns, 2.5V, LL
32-TSOP1-F, 120ns, 2.5V, LL
32-sTSOP1-F, 100ns, 2.5V, LL
32-sTSOP1-F, 120ns, 2.5V, LL
FUNCTIONAL DESCRIPTION
1. X means don
t care (Must be in low or high state)
CS
OE
WE
I/O
Mode
Power
H
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
High-Z
Output Disabled
Active
L
L
H
Dout
Read
Active
L
X
1)
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.5 to V
CC
+0.5
V
-
Voltage on Vcc supply relative to Vss
V
CC
-0.3 to 4.6
V
-
Power Dissipation
P
D
1.0
W
-
Storage temperature
T
STG
-65 to 150
C
-
Operating Temperature
T
A
-40 to 85
C
Industrial Product
K6T4008S1C Family
CMOS SRAM
Revision 1.0
April 1999
4
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. T
A
=-40 to 85
C, otherwise specified
2. Overshoot : V
CC
+1.0V in case of pulse width
20ns
3. Undershoot : -1.0V in case of pulse width
20ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Product
Min
Typ
Max
Unit
Supply voltage
Vcc
K6T4008S1C Family
2.3
2.5
2.7
V
Ground
Vss
All Family
0
0
0
V
Input high voltage
V
IH
All Family
2.0
-
Vcc+0.3
2)
V
Input low voltage
V
IL
All Family
-0.3
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS=V
IL
, V
IN
=V
IL
or V
IH
, read
-
-
1
mA
Average operating current
I
CC1
Cycle time=1
s, 100% duty, I
IO
=0mA CS
0.2V,V
IN
0.2V or V
IN
Vcc-0.2V
-
-
3
mA
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA, CS=V
IL
, V
IN
=V
IH
or V
IL
-
-
16
mA
Output low voltage
V
OL
I
OL
=0.5mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-0.5mA
2.0
-
-
V
Standby Current(TTL)
I
SB
CS=V
IH
, Other inputs = V
IL
or V
IH
-
-
0.3
mA
Standby Current (CMOS)
I
SB1
CS
Vcc-0.2V, Other inputs=0~Vcc
-
-
15
A
K6T4008S1C Family
CMOS SRAM
Revision 1.0
April 1999
5
AC CHARACTERISTICS
(V
CC
=2.3~2.7V, T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
100ns
120ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
100
-
120
-
ns
Address access time
t
AA
-
100
-
120
ns
Chip select to output
t
CO
-
100
-
120
ns
Output enable to valid output
t
OE
-
50
-
60
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
30
0
35
ns
Output disable to high-Z output
t
OHZ
0
30
0
35
ns
Output hold from address change
t
OH
15
-
15
-
ns
Write
Write cycle time
t
WC
100
-
120
-
ns
Chip select to end of write
t
CW
80
-
100
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
80
-
100
-
ns
Write pulse width
t
WP
70
-
80
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
30
0
35
ns
Data to write time overlap
t
DW
40
-
50
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage : 1.1V
Output load(see right) : C
L
=100pF+1TTL
C
L
=30pF
1)
+1TTL
1. K6T4008S1C-10 Family
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
Vcc-0.2V
2.0
-
3.6
V
Data retention current
I
DR
Vcc=2.5V, CS
Vcc-0.2V
-
0.5
15
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
K6T4008S1C Family
CMOS SRAM
Revision 1.0
April 1999
6
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
Address
OE
Data out
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ
t
RC
t
OE
t
CO
K6T4008S1C Family
CMOS SRAM
Revision 1.0
April 1999
7
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
t
CW(2)
t
WR(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
Controlled)
Address
CS
t
WC
t
WR(4)
t
AS(3)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
t
WC
t
AW
t
AS(3)
t
CW(2)
t
WP(1)
t
AW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, t
WP
is measured from the begining of write
to the end of write.
2. t
CW
is measured from the CS going low to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
V
CC
2.3V
2.2V
V
DR
CS
GND
Data Retention Mode
CS
V
CC
- 0.2V
t
SDR
t
RDR
K6T4008S1C Family
CMOS SRAM
Revision 1.0
April 1999
8
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
1.00
0.10
0.039
0.004
MAX
8.40
0.331
1
.
1
0
M
A
X
0
.
0
0
4
M
A
X
#1
0.50
( )
0.020
11.80
0.10
0.465
0.004
0.45 ~0.75
0.018 ~0.030
13.40
0.10
0.528
0.008
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
#16
#32
#17
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
#32
1.00
0.10
0.039
0.004
MAX
8.40
0.331
0
.
1
0
M
A
X
0
.
0
0
4
M
A
X
#1
0.50
( )
0.020
18.40
0.10
0.724
0.004
0.45 ~0.75
0.018 ~0.030
20.00
0.20
0.787
0.008
#17
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8
.
0
0
0
.
3
1
5
TYP
0.25
0.010
#16
K6T4008S1C Family
CMOS SRAM
Revision 1.0
April 1999
9
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8
#32
20.95
0.10
0.825
0.004
MAX
21.35
0.841
MAX
1.00
0.10
0.039
0.004
1.20
0.047
MIN
0.002
0.05
0.004 MAX
0.10 MAX
#1
0.95
( )
0.037
1
0
.
1
6
0
.
4
0
0
+0.10
0.15
-0.05
+0.004
0.006
-0.002
11.76
0.20
0.463
0.008
#17
#16
0.50
( )
0.020
0.45~0.75
0.018 ~ 0.030
0.25
( )
0.010
1.27
0.050
0.40
0.10
0.016
0.004
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0~8
#32
#1
1
0
.
1
6
0
.
4
0
0
+0.10
0.15
-0.05
+0.004
0.006
-0.002
11.76
0.20
0.463
0.008
#17
#16
0.50
( )
0.020
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
20.95
0.10
0.825
0.004
MAX
21.35
0.841
MAX
1.00
0.10
0.039
0.004
1.20
0.047
MIN
0.002
0.05
0.004 MAX
0.10 MAX
0.95
( )
0.037
1.27
0.050
0.40
0.10
0.016
0.004
PDF 
ZIP