616V4000B.PDF

K6T4016V3B, K6T4016U3B Family

CMOS SRAM

Revision 3.01

January 1998

Document Title

256Kx16 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No.

0.0

0.1

1.0

2.0

3.0

3.01

Remark

Advance

Preliminary

Final

History

Initial draft

Revise
- Die name change ; A to B

Finalize

Revise
- Operating current update and release.
I

(Read/Write) = 20/40

10/45mA

CC1

(Read/Write) = 20/40

10/45mA

CC2

= 90

70mA

Revise
- Change datasheet format
- Erase 70ns part from KM616V4000BI, KM616U4000B and
KM616U4000BI Family
- Power dissipation improved 0.7 to 1.0W
- V

(MAX) improved 0.4 to 0.6V.

- I

CC2

decreased 70 to 60mA.

- Erase 100ns from KM616V4000B commercial product
Error correction

Draft Data

June 28, 1996

September 19, 1996

December 17, 1996

February 17, 1997

January 14, 1998

August 7, 1998

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

K6T4016V3B, K6T4016U3B Family

CMOS SRAM

Revision 3.01

January 1998

256Kx16 bit Low Power and Low Voltage CMOS Static RAM

GENERAL DESCRIPTION

The K6T4016V3B and K6T4016U3B families are fabricated by

SAMSUNG

s advanced CMOS process technology. The fami-

lies support various operating temperature range and have

small package types for user flexibility of system design. The

families also support low data retention voltage for battery

back-up operation with low data retention current.

FEATURES

Process Technology: TFT

Organization: 256K x16

Power Supply Voltage

KM68V4000B Family: 3.0~3.6V
KM68U4000B Family: 2.7~3.3V

Low Data Retention Voltage: 2V(Min)

Three state output and TTL Compatible

Package Type: 44-TSOP2-400F/R

PIN DESCRIPTION

Name

Function

Name

Function

Chip Select Input

Lower Byte (I/O

1~8

)

Output Enable Input

Upper Byte(I/O

9~16

)

Write Enable Input

Vcc

Power

Address Inputs

Vss

Ground

I/O

~I/O

Data Inputs/Outputs

N.C

No Connection

PRODUCT FAMILY

1. The parameter is measured with 30pF test load.

Product Family

Operating Tempera-

ture

Vcc Range

Speed

Power Dissipation

PKG Type

Standby

SB1

, Max)

Operating

CC2

, Max)

K6T4016V3B-B

Commercial(0~70

3.0~3.6V

/85

60mA

44-TSOP2-F/R

K6T4016U3B-B

2.7~3.3V

/100ns

K6T4016V3B-F

Industrial(-40~85

3.0~3.6V

/100ns

K6T4016U3B-F

2.7~3.3V

I/O1

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A17

A16

A15

A14

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

N.C

A10

44-TSOP2

Forward

44-TSOP2

Reverse

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

N.C

A10

A11

A13

A12

A11

A12

I/OI

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A17

A16

A15

A14

A13

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

Row
select

A8 A9 A10 A5 A6

A13

A14

A15

A16

A17

I/O

~I/O

Data
cont

I/O

~I/O

Vcc
Vss

A12

Precharge circuit.

Memory array
1024 rows
256

16 columns

I/O Circuit

Column select

Control
logic

K6T4016V3B, K6T4016U3B Family

CMOS SRAM

Revision 3.01

January 1998

PRODUCT LIST

Commercial Temperature Product(0~70

Industrial Temperature Products(-40~85

Part Name

Function

Part Name

Function

K6T4016V3B-TB70
K6T4016V3B-TB85
K6T4016V3B-RB70
K6T4016V3B-RB85

K6T4016U3B-TB85
K6T4016U3B-TB10
K6T4016U3B-RB85
K6T4016U3B-RB10

44-TSOP2-F, 70ns, 3.3V,LL
44-TSOP2-F, 85ns, 3.3V,LL
44-TSOP2-R, 70ns, 3.3V,LL
44-TSOP2-R, 85ns, 3.3V,LL

44-TSOP2-F, 85ns, 3.0V,LL
44-TSOP2-F, 100ns, 3.0V,LL
44-TSOP2-R, 85ns, 3.0V,LL
44-TSOP2-R, 100ns, 3.0V,LL

K6T4016V3B-TF85
K6T4016V3B-TF10
K6T4016V3B-RF85
K6T4016V3B-RF10

K6T4016U3B-TF85
K6T4016U3B-TF10
K6T4016U3B-RF85
K6T4016U3B-RF10

44-TSOP2-F, 85ns, 3.3V,LL
44-TSOP2-F, 100ns, 3.3V,LL
44-TSOP2-R, 85ns, 3.3V,LL
44-TSOP2-R, 100ns, 3.3V,LL

44-TSOP2-F, 85ns, 3.0V,LL
44-TSOP2-F, 100ns, 3.0V,LL
44-TSOP2-R, 85ns, 3.0V,LL
44-TSOP2-R, 100ns, 3.0V,LL

ABSOLUTE MAXIMUM RATINGS

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item

Symbol

Ratings

Unit

Remark

Voltage on any pin relative to Vss

OUT

-0.5 to V

+0.5

Voltage on Vcc supply relative to Vss

-0.3 to 4.6

Power Dissipation

1.0

Storage temperature

STG

-65 to 150

Operating Temperature

0 to 70

Commercial

-40 to 85

Industrial

Soldering temperature and time

SOLDER

260

C, 10sec (Lead Only)

FUNCTIONAL DESCRIPTION

1. X means don

t care. (Must be in low or high state)

I/O

1~8

I/O

9~16

Mode

Power

High-Z

Deselected

Standby

High-Z

Output Disabled

Active

High-Z

Output Disabled

Active

Dout

High-Z

Lower Byte Read

Active

High-Z

Dout

Upper Byte Read

Active

Dout

Word Read

Active

Din

High-Z

Lower Byte Write

Active

High-Z

Din

Upper Byte Write

Active

Din

Word Write

Active

K6T4016V3B, K6T4016U3B Family

CMOS SRAM

Revision 3.01

January 1998

RECOMMENDED DC OPERATING CONDITIONS

Note:
1. Commercial Product : T

=0 to 70

C, otherwise specified

Industrial Product : T

=-40 to 85

C, otherwise specified

2. Overshoot : V

+3.0V in case of pulse width

30ns

3. Undershoot : -3.0V in case of pulse width

30ns

4. Overshoot and undershoot are sampled, not 100% tested.

Item

Symbol

Product

Min

Typ

Max

Unit

Supply voltage

Vcc

K6T4016V3B Family
K6T4016U3B Family

3.0
2.7

3.3
3.0

3.6
3.3

Ground

Vss

All Family

Input high voltage

K6T4016V3B, K6T4016U3B Family

2.2

Vcc+0.3

Input low voltage

K6T4016V3B, K6T4016U3B Family

-0.3

0.6

CAPACITANCE

(f=1MHz, T

=25

1. Capacitance is sampled, not 100% tested

Item

Symbol

Test Condition

Min

Max

Unit

Input capacitance

=0V

Input/Output capacitance

=0V

DC AND OPERATING CHARACTERISTICS

1. Industrial product = 20

Item

Symbol

Test Conditions

Min

Typ

Max

Unit

Input leakage current

=Vss to Vcc

-1

Output leakage current

CS=V

or OE=V

or WE=V

=Vss to Vcc

-1

Operating power supply current

=0mA, CS=V

, V

or V

, Read

Average operating current

CC1

Cycle time=1

s, 100% duty, I

=0mA

0.2V, V

0.2V or V

Vcc-0.2V

Read

Write

CC2

Cycle time=Min, 100% duty, I

=0mA, CS=V

IL,

or V

Output low voltage

=2.1mA

0.4

Output high voltage

=-1.0mA

2.2

Standby Current(TTL)

CS=V

IH,

Other inputs=V

or V

0.5

Standby Current(CMOS)

SB1

Vcc-0.2V, Others inputs = 0~Vcc

K6T4016V3B, K6T4016U3B Family

CMOS SRAM

Revision 3.01

January 1998

)

1.Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS

(Test Load and Input/Output Reference)

Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : C

=100pF+1TTL

=30pF+1TTL

AC CHARACTERISTICS

(K6T4016V3B Family: Vcc=3.0~3.6V, K6T4016U3B Family: Vcc=2.7~3.3V,

Commercial product : T

0 to 70

C, Industrial product : T

=-40 to 85

1. The parameter is measured with 30pF test load

Parameter List

Symbol

Speed Bins

Units

70ns

85ns

100ns

Min

Max

Min

Max

Min

Max

Read

Read cycle time

100

Address access time

100

Chip select to output

100

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

OLZ

UB, LB enable to low-Z output

BLZ

Chip disable to high-Z output

OE disable to high-Z output

OHZ

Output hold from address change

LB, UB valid to data output

UB, LB disable to high-Z output

BHZ

Write

Write cycle time

100

Chip select to end of write

Address set-up time

Address valid to end of write

Write pulse width

Write recovery time

Write to output high-Z

WHZ

Data to write time overlap

Data hold from write time

End write to output low-Z

LB, UB valid to end of write

DATA RETENTION CHARACTERISTICS

1. Industrial product = 20

Item

Symbol

Test Condition

Min

Typ

Max

Unit

Vcc for data retention

Vcc-0.2V

2.0

3.6

Data retention current

Vcc=3.0V, CS

Vcc-0.2V

0.5

Data retention set-up time

SDR

See data retention waveform

Recovery time

RDR

K6T4016V3B, K6T4016U3B Family

CMOS SRAM

Revision 3.01

January 1998

Address

Data Out

Previous Data Valid

Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1)

(Address Controlled

CS=OE=V

, WE=V

, UB or/and LB=V

)

TIMING WAVEFORM OF READ CYCLE(2)

(WE=V

)

Data Valid

High-Z

Address

UB, LB

Data out

OLZ

BLZ

OHZ

BHZ

NOTES (READ CYCLE)

and

OHZ

are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition,

(Max.) is less than

(Min.) both for a given device and from device to device

interconnection.

K6T4016V3B, K6T4016U3B Family

CMOS SRAM

Revision 3.01

January 1998

Address

Data Valid

UB, LB

Data in

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(3)

(UB, LB Controlled)

NOTES

(WRITE CYCLE)

1. A wri

e occurs during the overlap(t

) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The

is measured from the beginning of write to the end of write.

is measured from the CS going low to end of write.

is measured from the address valid to the beginning of write.

is measured from the end or write to the address change.

applied in case a write ends as CS or WE going high.

CW(2)

WP(1)

WR(4)

DATA RETENTION WAVE FORM

CS controlled

3.0/2.7V

2.2V

CS
GND

Data Retention Mode

- 0.2V

SDR

RDR

AS(3)

K6T4016V3B, K6T4016U3B Family

CMOS SRAM

Revision 3.01

January 1998

Unit: millimeters(inches)

PACKAGE DIMENSIONS

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)

.
0

#22

#44

#23

0.35

0.10

0.014

0.004

0.80

0.0315

I
N

0.047

1.20

MAX.

0.741

18.81

MAX.

18.41

0.10

0.725

0.004

11.76

0.20

0.463

0.008

+ 0.

- 0.0

0.50

+ 0.0

- 0.0

0.15

0.00

0.020

.
1

.
4

0.10

0.004

0~8

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

( )

0.805
0.032

( )

MAX

1.00

0.10

0.039

0.004

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

.
0

#22

#44

#23

0.35

0.10

0.014

0.004

0.80

0.0315

I
N

0.047

1.20

MAX.

0.741

18.81

MAX.

18.41

0.10

0.725

0.004

11.76

0.20

0.463

0.008

+ 0

.10

- 0.0

0.50

+ 0.0

- 0.0

0.15

0.00

0.020

.
1

.
4

0.10

0.004

0~8

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

( )

0.805

0.032

( )

MAX

1.00

0.10

0.039

0.004

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