K6T4016U6C.PDF
K6T4016U6C Family
CMOS SRAM
Revision 1.0
November 1998
1
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0.0
0.01
1.0
Remark
Preliminary
Final
History
Initial draft
Errata correction
Finalize
- Specified CSP type.
- Errata correction
Draft Date
July 4, 1998
August 17, 1998
November 16, 1998
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branchoffices.
K6T4016U6C Family
CMOS SRAM
Revision 1.0
November 1998
2
256Kx16 bit Low Power and Low Voltage CMOS StaticRAM
GENERAL DESCRIPTION
The K6T4016U6C families are fabricated by SAMSUNG
s
advanced CMOS process technology. The families support
industrial operating temperature ranges and have chip scale
package for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.
FEATURES
Process Technology: TFT
Organization: 256K x16
Power Supply Voltage
K6T4016U6C Family: 2.7~3.3V
Low Data Retention Voltage: 2.0V(Min)
Three State Outputs
Dual CS and standby control by UB, LB
Package Type: 48-
BGA-6.10x8.90
Name
Function
Name
Function
CS
1
,CS
2
Chip Select Inputs
Vcc
Power
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
UB
Upper Byte(I/O
9
~
16
)
A
0
~A
17
Address Inputs
LB
Lower Byte(I/O
1
~
8
)
I/O
1
~I/O
16
Data Inputs/Outputs
NC
No Connection
PRO
DUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
K6T4016U6C-F
Industrial(-40~85
C)
2.7~3.3V
70
1)
/85/100ns
20
A
45mA
48-
BGA-6.10x8.90
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Row
select
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
I/O
9
~I/O
16
Vcc
Vss
Precharge circuit.
Memory array
1024 rows
256
16 columns
I/O Circuit
Column select
PIN DESCRIPTION
48-ball CSP - Top View (Ball Down)
LB
OE
A0
A1
A2
CS2
I/O9
UB
A3
A4
CS1
I/O1
I/O10
I/O11
A5
A6
I/O2
I/O3
Vss
I/O12
A17
A7
I/O4
Vcc
Vcc
I/O13
NC
A16
I/O5
Vss
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O16
NC
A12
A13
WE
I/O8
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
A
B
C
D
E
F
G
H
WE
OE
UB
CS1
LB
Control Logic
CS2
Row
Addresses
Column Addresses
K6T4016U6C Family
CMOS SRAM
Revision 1.0
November 1998
3
PRODUCT LIST
Industrial Temperature Products(-40~85
C)
Part Name
Function
K6T4016U6C-ZF70
K6T4016U6C-ZF85
K6T4016U6C-ZF10
48-
BGA, 70ns, 3.0V, LL
48-
BGA, 85ns, 3.0V, LL
48-
BGA, 100ns, 3.0V, LL
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.5 to V
CC
+0.5
V
Voltage on Vcc supply relative to Vss
V
CC
-0.3 to 4.6
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
-40 to 85
C
FUNCTIONAL DESCRIPTION
1. X means don
t care. (Must be low or high state)
CS
1
CS
2
OE
WE
LB
UB
I/O
1~8
I/O
9~16
Mode
Power
H
X
1)
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
X
1)
X
1)
X
1)
X
1)
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
H
L
X
1)
High-Z
High-Z
Output Disabled
Active
L
H
H
H
X
1)
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
H
L
H
L
L
Dout
Dout
Word Read
Active
L
H
X
1)
L
L
H
Din
High-Z
Lower Byte Write
Active
L
H
X
1)
L
H
L
High-Z
Din
Upper Byte Write
Active
L
H
X
1)
L
L
L
Din
Din
Word Write
Active
K6T4016U6C Family
CMOS SRAM
Revision 1.0
November 1998
4
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. T
A
=-40 to 85
C, otherwise specified
2. Overshoot: V
CC
+2.0V in case of pulse width
30ns.
3. Undershoot: -2.0V in case of pulse width
30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Product
Min
Typ
Max
Unit
Supply voltage
Vcc
K6T4016U6C Family
2.7
3.0
3.3
V
Ground
Vss
K6T4016U6C Family
0
0
0
V
Input high voltage
V
IH
K6T4016U6C Family
2.2
-
Vcc+0.3
2)
V
Input low voltage
V
IL
K6T4016U6C Family
-0.3
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH,
CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS
1
=V
IL,
CS
2
=V
IH
, V
IN
=V
IH
or V
IL
-
-
4
mA
Average operating current
I
CC1
Cycle time=1
s, 100%duty, I
IO
=0mA, CS
1
0.2V, CS
2
Vcc-
0.2V, V
IN
0.2V or V
IN
VCC-0.2V
-
-
6
mA
I
CC2
Cycle time=Min, I
IO
=0mA, 100% duty,
CS
1
=V
IL
, CS
2
=V
IH,
VIN=V
IL
or V
IH
-
-
45
mA
Output low voltage
V
OL
I
OL
= 2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
= -1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs=V
IH
or V
IL
-
-
0.3
mA
Standby Current(CMOS)
I
SB1
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled)
or CS
2
0.2V(CS
2
controlled), Other inputs=0~Vcc
-
-
20
A
K6T4016U6C Family
CMOS SRAM
Revision 1.0
November 1998
5
C
L
1
)
1.Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1.
CS
1
Vcc-0.2V,CS
2
Vcc-0.2V(CS
1
controlled) or CS
2
Vcc-0.2V(CS
2
controlled)
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
Vcc-0.2V
1)
2.0
-
3.3
V
Data retention current
I
DR
Vcc=3.0V, CS
1
Vcc-0.2V
1)
-
0.5
20
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
AC CHARACTERISTICS
(Vcc=2.7~3.3V, Industrial product: T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
70ns
85ns
100ns
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
85
-
100
-
ns
Address access time
t
AA
-
70
-
85
-
100
ns
Chip select to output
t
CO
-
70
-
85
-
100
ns
Output enable to valid output
t
OE
-
35
-
40
-
50
ns
LB, UB valid to data output
t
BA
-
70
-
85
-
100
ns
Chip select to low-Z output
t
LZ
10
-
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
5
-
ns
LB, UB enable to low-Z output
t
BLZ
10
-
10
-
10
-
ns
Output hold from address change
t
OH
10
-
10
-
15
-
ns
Chip disable to high-Z output
t
HZ
0
25
0
25
0
30
ns
OE disable to high-Z output
t
OHZ
0
25
0
25
0
30
ns
UB, LB disable to high-Z output
t
BHZ
0
25
0
25
0
30
ns
Write
Write cycle time
t
WC
70
-
85
-
100
-
ns
Chip select to end of write
t
CW
60
-
70
-
80
-
ns
Address set-up time
t
AS
0
-
0
-
0
-
ns
Address valid to end of write
t
AW
60
-
70
-
80
-
ns
Write pulse width
t
WP
55
-
60
-
70
-
ns
Write recovery time
t
WR
0
-
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
25
0
30
ns
Data to write time overlap
t
DW
30
-
35
-
40
-
ns
Data hold from write time
t
DH
0
-
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
5
-
ns
LB, UB valid to end of write
t
BW
60
-
70
-
80
-
ns
K6T4016U6C Family
CMOS SRAM
Revision 1.0
November 1998
6
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS
1
=OE=V
IL
, CS
2
=WE=V
IH
, UB or/and LB=V
IL
)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
t
RC
CS
1
Address
UB, LB
OE
Data out
t
AA
t
RC
t
OH
t
OH
t
AA
t
CO
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
BHZ
t
HZ
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
K6T4016U6C Family
CMOS SRAM
Revision 1.0
November 1998
7
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
t
WC
t
CW(2)
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AS(3)
CS
1
CS
2
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
1
Data Undefined
UB, LB
WE
Data in
Data out
t
WC
t
CW(2)
t
WR(4)
t
AW
t
BW
t
WP(1)
t
AS(3)
t
DH
t
DW
t
WHZ
t
OW
High-Z
High-Z
Data Valid
CS
2
K6T4016U6C Family
CMOS SRAM
Revision 1.0
November 1998
8
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled)
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS
1
and low WE. A write begins when CS
1
goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS
1
goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS
1
going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
t
WR
applied in case a write ends as CS
1
or WE going high.
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
2.7V
2.2V
V
DR
CS, LB/UB
GND
Data Retention Mode
CS1
V
CC
- 0.2V
t
SDR
t
RDR
t
AS(3)
CS
1
CS
2
CS
2
controlled
V
CC
2.7V
0.4V
V
DR
CS
2
GND
Data Retention Mode
t
SDR
t
RDR
CS
2
0.2V
K6T4016U6C Family
CMOS SRAM
Revision 1.0
November 1998
9
PACKAGE DIMENSIONS
6
5
4
3
2
1
A
B
C
D
E
F
G
H
C
/
2
B/2
C
B
B1
C
1
Ball #A1
B
B/2
Elastomer
SRAM Die
C
Ball #A1
C
/
2
Bottom View
Top View
D
E
2
E
1
E
C
Detail A
Side View
0
.
6
8
/
T
y
p
.
0
.
4
5
/
T
y
p
.
0
.
2
5
/
T
y
p
.
A
Y
Elastomer
0.3/Typ.
Die
Detail A
Notes.
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.08(Max)
Min
Typ
Max
A
-
0.75
-
B
6.00
6.10
6.20
B1
-
3.75
-
C
8.80
8.90
9.00
C1
-
5.25
-
D
0.30
0.35
0.40
E
-
0.93
0.94
E1
-
0.68
-
E2
-
0.25
-
Y
-
-
0.08
Units: millimeters
48 BALL MICRO BALL GRID ARRAY- 0.75mm ball pitch
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