K6X4016C3F Family
CMOS SRAM
Revision 1.0
September 2003
1
Document Title
256Kx16 bit Low Power full CMOS Static RAM
Revision History
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision No.
0.0
0.1
1.0
Remark
Preliminary
Preliminary
final
History
Initial draft
Revised
Added Commercial Product.
Deleted
44-TSOP2-400R Package Type.
Finalized
- Changed I
CC
from 10mA to 5mA
- Changed I
CC
1 from 10mA to 7mA
- Changed I
CC
2 from 50mA to 30mA
- Changed I
SB
from 3mA to 0.4mA
- Changed I
DR
(Commercial)
from 15
A to 12
A
- Changed I
DR
(industrial)
from 20
A to 12
A
- Changed I
DR
(Automotive)
from 30
A to 25
A
Draft Date
July 26, 2002
November 29, 2002
September 16, 2003
K6X4016C3F Family
CMOS SRAM
Revision 1.0
September 2003
2
256Kx16 bit Low Power full CMOS Static RAM
GENERAL DESCRIPTION
The K6X4016C3F families are fabricated by SAMSUNG
s
advanced full CMOS process technology. The families sup-
port various operating temperature range and small pack-
age types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
FEATURES
Process Technology: Full CMOS
Organization: 256Kx16
Power Supply Voltage: 4.5~5.5V
Low Data Retention Voltage: 2V(Min)
Three state output and TTL compatible
Package Type: 44-TSOP2-400F
PRODUCT FAMILY
1. The parameter is measured with 50pF test load.
Product Family Operating Temperature Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
K6X4016C3F-B
Commercial(
0~70
C)
4.5~5.5V
55
1)
/70ns
20
A
30 mA
44-TSOP2-400F
K6X4016C3F-F
Industrial (-40~85
C)
K6X4016C3F-Q
Automotive (-40~125
C)
30
A
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
PIN DESCRIPTION
Name
Function
Name
Function
CS
Chip Select Input
LB
Lower Byte (I/O
1~8
)
OE
Output Enable Input
UB
Upper Byte(I/O
9~16
)
WE
Write Enable Input
Vcc
Power
A
0
~A
17
Address Inputs
Vss
Ground
I/O
1
~I/O
16
Data Inputs/Outputs
NC
No Connection
A4
A3
A2
A1
A0
CS
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
A9
A10
44-TSOP2
Forward
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A13
A12
A11
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Row
select
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
I/O
9
~I/O
16
Vcc
Vss
Precharge circuit.
Memory array
I/O Circuit
Column select
WE
OE
UB
CS
LB
Control
logic
Row
Addresses
Column Addresses
K6X4016C3F Family
CMOS SRAM
Revision 1.0
September 2003
3
PRODUCT LIST
Commercial Products(0~70
C)
Industrial Products(-40~85
C)
Automotive Products(-40~125
C)
Part Name
Function
Part Name
Function
Part Name
Function
K6X4016C3F-TB55
K6X4016C3F-TB70
44-TSOP2-F, 55ns, LL
44-TSOP2-F, 70ns, LL
K6X4016C3F-TF55
K6X4016C3F-TF70
44-TSOP2-F, 55ns, LL
44-TSOP2-F, 70ns, LL
K6X4016C3F-TQ55
K6X4016C3F-TQ70
44-TSOP2-F, 55ns, L
44-TSOP2-F, 70ns, L
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.5 to V
CC
+0.5V(max. 7.0V)
V
-
Voltage on Vcc supply relative to Vss
V
CC
-0.3 to 7.0
V
-
Power Dissipation
P
D
1.0
W
-
Storage temperature
T
STG
-65 to 150
C
-
Operating Temperature
T
A
0 to 70
C
K6X4016C3F-B
-40 to 85
K6X4016C3F-F
-40 to 125
K6X4016C3F-Q
FUNCTIONAL DESCRIPTION
1. X means don
t care. (Must be in low or high state)
CS
OE
WE
LB
UB
I/O
1~8
I/O
9~16
Mode
Power
H
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
L
H
H
X
1)
X
1)
High-Z
High-Z
Output Disabled
Active
L
X
1)
X
1)
H
H
High-Z
High-Z
Output Disabled
Active
L
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
L
H
L
L
Dout
Dout
Word Read
Active
L
X
1)
L
L
H
Din
High-Z
Lower Byte Write
Active
L
X
1)
L
H
L
High-Z
Din
Upper Byte Write
Active
L
X
1)
L
L
L
Din
Din
Word Write
Active
K6X4016C3F Family
CMOS SRAM
Revision 1.0
September 2003
4
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. Commercial Product: T
A
=0 to 70
C, otherwise specified
Industrial Product: T
A
=-40 to 85
C, otherwise specified
Automotive Product T
A
=-40 to 125
C, otherwise specified
2. Overshoot: V
CC
+3.0V in case of pulse width
30ns
3. Undershoot: -3.0V in case of pulse width
30ns
4. Overshoot and undershoot are sampled, not 100% tested
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.5
2)
V
Input low voltage
V
IL
-0.5
3)
-
0.8
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS=V
IH
or OE=V
IH
or
WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS=V
IL
, V
IN
=V
IL
or V
IH
, Read
-
-
5
mA
Average operating current
I
CC1
Cycle time=1
s, 100% duty, I
IO
=0mA
CS
0.2V, V
IN
0.2V or V
IN
Vcc-0.2V
-
-
7
mA
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
-
-
30
mA
Output low voltage
V
OL
I
OL
=2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS=V
IH
, Other inputs = V
IL
or V
IH
-
-
0.4
mA
Standby Current(CMOS)
I
SB1
CS
Vcc-0.2V, Other inputs=0~Vcc
K6X4016C3F-B
-
-
20
A
K6X4016C3F-F
-
-
K6X4016C3F-Q
-
-
30
A
K6X4016C3F Family
CMOS SRAM
Revision 1.0
September 2003
5
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): C
L
=100pF+1TTL
C
L
=50pF+1TTL
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
Vcc-0.2V
2.0
-
5.5
V
Data retention current
I
DR
Vcc=3.0V, CS
Vcc-0.2V
K6X4016C3F-B
-
12
A
K6X4016C3F-F
12
K6X4016C3F-Q
25
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
AC CHARACTERISTICS
( Vcc=4.5~5.5V, Commercial Product: T
A
=0 to 70
C, Industrial Product: T
A
=-40 to 85
C, Automotive Product : T
A=
-40 to 125
C, )
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
LB, UB enable to low-Z output
t
BLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
25
ns
OE disable to high-Z output
t
OHZ
0
20
0
25
ns
Output hold from address change
t
OH
10
-
10
-
ns
LB, UB valid to data output
t
BA
-
25
-
35
ns
UB, LB disable to high-Z output
t
BHZ
0
20
0
25
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
45
-
55
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
LB, UB valid to end of write
t
BW
45
-
60
-
ns
K6X4016C3F Family
CMOS SRAM
Revision 1.0
September 2003
6
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB or/and LB=V
IL
)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
t
RC
CS
Address
UB, LB
OE
Data out
t
AA
t
RC
t
OH
t
OH
t
AA
t
CO
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
BHZ
t
HZ
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
K6X4016C3F Family
CMOS SRAM
Revision 1.0
September 2003
7
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS Controlled)
Address
CS
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
t
WC
t
CW(2)
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AS(3)
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
Data Undefined
UB, LB
WE
Data in
Data out
t
WC
t
CW(2)
t
WR(4)
t
AW
t
BW
t
WP(1)
t
AS(3)
t
DH
t
DW
t
WHZ
t
OW
High-Z
High-Z
Data Valid
K6X4016C3F Family
CMOS SRAM
Revision 1.0
September 2003
8
Address
CS
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled)
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
t
WR
applied in case a write ends as CS or WE going high.
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
DATA RETENTION WAVE FORM
CS controlled
V
CC
4.5V
2.2V
V
DR
CS
GND
Data Retention Mode
CS
V
CC
- 0.2V
t
SDR
t
RDR
t
AS(3)
K6X4016C3F Family
CMOS SRAM
Revision 1.0
September 2003
9
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
Units: millimeter(inch)
0
.
0
0
2
#1
0
.
0
5
#22
#44
#23
0.35
0.10
0.014
0.004
0.80
0.0315
M
I
N
.
0.047
1.20
MAX.
0.741
18.81
MAX.
18.41
0.10
0.725
0.004
11.76
0.20
0.463
0.008
+ 0
.10
- 0.0
5
0.50
+ 0.0
04
- 0.0
02
0.15
0.00
6
0.020
1
0
.
1
6
0
.
4
0
0
0.10
0.004
PACKAGE DIMENSIONS
0~8
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
( )
0.805
0.032
( )
MAX
1.00
0.10
0.039
0.004
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