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64Kx36/x32 Synchronous SRAM
- 1 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
Document Title
64Kx36 & 64Kx32-Bit Synchronous Pipelined Burst SRAM
Revision History
Remark
Preliminary
Preliminary
Final
Final
History
1. Initial draft
1. Add tCYC 250,225, 200MHz bin.
1. Final spec release
2. Remove tCYC 225MHz( -22)
1. Remove the x18 organization
2. Remove tCYC 250/200/167MHz( -25/-20/-16)
Draft Date
Dec. 10. 2001
Jan . 17. 2002
April. 01. 2002
Nov. 17. 2003
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No
0.0
0.1
1.0
2.0
64Kx36/x32 Synchronous SRAM
- 2 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
2Mb SPB Synchronous SRAM Ordering Information
Org.
Part Number
Mode
VDD
Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz)
PKG
Temp
64Kx32 K7A203200B-QC(I)14
SPB(2E1D)
3.3
138MHz
Q
(100TQFP)
C (Commercial
Temperature
Range)
I:(Industrial
Temperature
Range)
64Kx36 K7A203600B-QC(I)14
SPB(2E1D)
3.3
138MHz
64Kx36/x32 Synchronous SRAM
- 3 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
64Kx36 & 64Kx32-Bit Synchronous Pipelined Burst SRAM
The K7A203600B and K7A203200B are 2,359,296-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
It is organized as 64K words of 36/32 bits and integrates
address and control registers, a 2-bit burst address counter
and added some new functions for high performance cache
RAM applications; GW, BW, LBO, ZZ. Write cycles are inter-
nally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system
s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A203600B and K7A203200B are fabricated using
SAMSUNG
s high performance CMOS technology and is
available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
LOGIC BLOCK DIAGRAM
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
V
DD
= 3.3V+0.3V/-0.165V Power Supply.
V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a linear
burst.
Three Chip Enables for simple depth expansion with No Data Cont-
nention ; 2cycle Enable, 1cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A .
Operating in commeical and industrial temperature range.
CLK
LBO
ADV
ADSC
ADSP
CS1
CS2
CS2
GW
BW
WEx
OE
ZZ
DQa0 ~ DQd7
BURST CONTROL
LOGIC
BURST
64Kx36/32
ADDRESS
CONTROL
OUTPUT
DATA-IN
ADDRESS
COUNTER
MEMORY
ARRAY
REGISTER
REGISTER
BUFFER
LOGIC
CONT
ROL
RE
GI
S
T
ER
CO
NTROL
REGI
ST
ER
A
0~A1
A0~A1
A0~A15
REGISTER
DQPa ~ DQPd
A2~A15
(x=a,b,c,d)
36/32 or 18
FAST ACCESS TIMES
PARAMETER
Symbol
-14
Unit
Cycle Time
tCYC
7.2
ns
Clock Access Time
tCD
4.0
ns
Output Enable Access Time
tOE
4.0
ns
64Kx36/x32 Synchronous SRAM
- 4 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
DQPc/NC
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd/NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa/NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A
6
A
7
CS
1
CS
2
WE
d
WE
c
WE
b
WE
a
CS
2
V
DD
V
SS
CL
K
GW
BW
OE
AD
S
C
AD
S
P
AD
V
A
8
81
A
9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
N.
C.
A
15
A
14
A
13
A
12
A
11
A
10
N.
C.
N.
C.
V
DD
V
SS
N.
C.
N.
C.
A
0
A
1
A
2
A
3
A
4
A
5
31
LBO
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A
0
- A
15
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WEx
(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37
44,45,46,47,48,49
81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
VDD
VSS
N.C.
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
/NC
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,41,65,91
17,40,67,90
14,16,38,39,42,43,50,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
K7A203600B(64Kx36)
K7A203200B(64Kx32)
64Kx36/x32 Synchronous SRAM
- 5 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
FUNCTION DESCRIPTION
The K7A2036/3200B are synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC
based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration
of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS
1
.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regardless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa
0
~ DQa
7
and DQPa, WEb controls DQb
0
~ DQb
7
and DQPb,
WEc controls DQc
0
~ DQc
7
and DQPc,
and WEd control DQd
0
~ DQd
7
and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
LBO PIN
HIGH
Case 1
Case 2
Case 3
Case 4
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
BQ TABLE
(Linear Burst)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
LBO PIN
LOW
Case 1
Case 2
Case 3
Case 4
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2)
:
OPERATION
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
Read
L
L
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes
1. X means "Don
t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
64Kx36/x32 Synchronous SRAM
- 6 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
SYNCHRONOUS TRUTH TABLE
Notes : 1. X means "Don
t Care". 2. The rising edge of clock is symbolized by .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS
1
CS
2
CS
2
ADSP ADSC
ADV
WRITE
CLK
ADDRESS ACCESSED
OPERATION
H
X
X
X
L
X
X
N/A
Not Selected
L
L
X
L
X
X
X
N/A
Not Selected
L
X
H
L
X
X
X
N/A
Not Selected
L
L
X
X
L
X
X
N/A
Not Selected
L
X
H
X
L
X
X
N/A
Not Selected
L
H
L
L
X
X
X
External Address
Begin Burst Read Cycle
L
H
L
H
L
X
L
External Address
Begin Burst Write Cycle
L
H
L
H
L
X
H
External Address
Begin Burst Read Cycle
X
X
X
H
H
L
H
Next Address
Continue Burst Read Cycle
H
X
X
X
H
L
H
Next Address
Continue Burst Read Cycle
X
X
X
H
H
L
L
Next Address
Continue Burst Write Cycle
H
X
X
X
H
L
L
Next Address
Continue Burst Write Cycle
X
X
X
H
H
H
H
Current Address
Suspend Burst Read Cycle
H
X
X
X
H
H
H
Current Address
Suspend Burst Read Cycle
X
X
X
H
H
H
L
Current Address
Suspend Burst Write Cycle
H
X
X
X
H
H
L
Current Address
Suspend Burst Write Cycle
WRITE TRUTH TABLE( x36/32)
Notes : 1. X means "Don
t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(
).
GW
BW
WEa
WEb
WEc
WEd
OPERATION
H
H
X
X
X
X
READ
H
L
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
H
L
H
L
H
H
WRITE BYTE b
H
L
H
H
L
L
WRITE BYTE c and d
H
L
L
L
L
L
WRITE ALL BYTEs
L
X
X
X
X
X
WRITE ALL BYTEs
TRUTH TABLES
64Kx36/x32 Synchronous SRAM
- 7 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
ABSOLUTE MAXIMUM RATINGS*
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER
SYMBOL
RATING
UNIT
Voltage on V
DD
Supply Relative to V
SS
Voltage on V
DDQ
Supply Relative to V
SS
V
DD
-0.3 to 4.6
V
V
DDQ
V
DD
V
Voltage on Input Pin Relative to V
SS
V
IN
-0.3 to V
DD
+0.3
V
Voltage on I/O Pin Relative to V
SS
V
IO
-0.3 to V
DDQ
+0.3
V
Power Dissipation
P
D
2.2
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
Commercial
T
OPR
0 to 70
C
Industrial
T
OPR
-40 to 85
C
Storage Temperature Range Under Bias
T
BIAS
-10 to 85
C
CAPACITANCE*
(T
A
=25
C, f=1MHz)
*Note : Sampled not 100% tested.
PARAMETER
SYMBOL
TEST CONDITION
TYP
MAX
UNIT
Input Capacitance
C
IN
V
IN
=0V
-
4
pF
Output Capacitance
C
OUT
V
OUT
=0V
-
6
pF
OPERATING CONDITIONS at 3.3V I/O
(0
C T
A
70C)
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER
SYMBOL
MIN
Typ.
MAX
UNIT
Supply Voltage
V
DD
3.135
3.3
3.6
V
V
DDQ
3.135
3.3
3.6
V
Ground
V
SS
0
0
0
V
OPERATING CONDITIONS at 2.5V I/O
(0
C T
A
70C)
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER
SYMBOL
MIN
Typ.
MAX
UNIT
Supply Voltage
V
DD
3.135
3.3
3.6
V
V
DDQ
2.375
2.5
2.9
V
Ground
V
SS
0
0
0
V
64Kx36/x32 Synchronous SRAM
- 8 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
DC ELECTRICAL CHARACTERISTICS
(T
A
=0 to 70
C, V
DD
=3.3V+0.3V/-0.165V)
The above parameters are also guaranteed at industrial temperature range.
* V
IL
(Min)=-2.0(Pulse Width
t
CYC
/
2)
** V
IH
(Max)=4.6(Pulse Width
t
CYC
/
2)
** In Case of I/O Pins, the Max. V
IH
=V
DDQ
+0.3V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
Input Leakage Current(except ZZ)
I
IL
V
DD
= Max ; V
IN
=V
SS
to V
DD
-2
+2
A
Output Leakage Current
I
OL
Output Disabled, V
OUT
=V
SS
to V
DDQ
-2
+2
A
Operating Current
Standby Current
I
CC
Device Selected, I
OUT
=0mA, ZZ
V
IL
,
All Inputs=V
IL
or V
IH
, Cycle Time
cyc Min
-14
-
250
mA
Standby Current
I
SB
Device deselected, I
OUT
=0mA,ZZ
V
IL
,
f=Max, All Inputs
0.2V or V
DD
-0.2V
-14
-
130
mA
I
SB1
Device deselected, I
OUT
=0mA, ZZ
0.2V,
f = 0, All Inputs=fixed (V
DD
-0.2V or 0.2V)
-
80
mA
I
SB2
Device deselected, I
OUT
=0mA, ZZ
V
DD
-0.2V,
f=Max, All Inputs
V
IL
or
V
IH
-
50
mA
Output Low Voltage(3.3V I/O)
V
OL
I
OL
= 8.0mA
-
0.4
V
Output High Voltage(3.3V I/O)
V
OH
I
OH
= -4.0mA
2.4
-
V
Output Low Voltage(2.5V I/O)
V
OL
I
OL
= 1.0mA
-
0.4
V
Output High Voltage(2.5V I/O)
V
OH
I
OH
= -1.0mA
2.0
-
V
Input Low Voltage(3.3V I/O)
V
IL
-0.5*
0.8
V
Input High Voltage(3.3V I/O)
V
IH
2.0
V
DD
+0.3**
V
Input Low Voltage(2.5V I/O)
V
IL
-0.3*
0.7
V
Input High Voltage(2.5V I/O)
V
IH
1.7
V
DD
+0.3**
V
TEST CONDITIONS
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
0 to 3V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
1ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
1ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
V
DDQ
/2
Output Load
See Fig. 1
(V
DD
=3.3V+0.3V/-0.165V,V
DDQ
=3.3V+0.3/-0.165V or V
DD
=3.3V+0.3V/-0.165V,V
DDQ
=2.5V+0.4V/-0.125V, T
A
=0 to 70
C)
* The above parameters are also guaranteed at industrial temperature range.
64Kx36/x32 Synchronous SRAM
- 9 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
AC TIMING CHARACTERISTICS
(T
A
=0 to 70
C, V
DD
=3.3V+0.3V/-0.165V)
Notes :
1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP
is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times
whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
PARAMETER
Symbol
-14
Unit
Min
Max
Cycle Time
tCYC
7.2
-
ns
Clock Access Time
tCD
-
4.0
ns
Output Enable to Data Valid
tOE
-
4.0
ns
Clock High to Output Low-Z
tLZC
0
-
ns
Output Hold from Clock High
tOH
1.5
-
ns
Output Enable Low to Output Low-Z
tLZOE
0
-
ns
Output Enable High to Output High-Z
tHZOE
-
4.0
ns
Clock High to Output High-Z
tHZC
1.5
4.0
ns
Clock High Pulse Width
tCH
2.8
-
ns
Clock Low Pulse Width
tCL
2.8
-
ns
Address Setup to Clock High
tAS
1.5
-
ns
Address Status Setup to Clock High
tSS
1.5
-
ns
Data Setup to Clock High
tDS
1.5
-
ns
Write Setup to Clock High (GW, BW, WEX)
tWS
1.5
-
ns
Address Advance Setup to Clock High
tADVS
1.5
-
ns
Chip Select Setup to Clock High
tCSS
1.5
-
ns
Address Hold from Clock High
tAH
0.5
-
ns
Address Status Hold from Clock High
tSH
0.5
-
ns
Data Hold from Clock High
tDH
0.5
-
ns
Write Hold from Clock High (GW, BW, WEX)
tWH
0.5
-
ns
Address Advance Hold from Clock High
tADVH
0.5
-
ns
Chip Select Hold from Clock High
tCSH
0.5
-
ns
ZZ High to Power Down
tPDS
2
-
cycle
ZZ Low to Power Up
tPUS
2
-
cycle
Output Load(B)
(for t
LZC
, t
LZOE
, t
HZOE
& t
HZC
)
Dout
5pF*
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Z0=50
* Capacitive Load consists of all components of
30pF*
the test environment.
RL=50
353
/ 1538
+3.3V for 3.3V I/O
319
/ 1667
VL=1.5V for 3.3V I/O
V
DDQ
/2 for 2.5V I/O
/+2.5V for 2.5V I/O
64Kx36/x32 Synchronous SRAM
- 10 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
CL
OC
K
AD
SP
AD
SC
A
DDRESS
WRIT
E
CS
AD
V
OE
Da
ta
O
u
t
TIMING
WAV
E
FORM OF REA
D
CYCLE
NO
T
ES : WRIT
E
= L
me
ans GW
=
L,
or GW
= H, B
W
=
L, W
E
x =
L
CS
= L mean
s CS
1
= L
,
CS
2
= H
a
nd CS
2
=
L
CS
= H means CS
1
= H, or CS
1
=
L an
d
CS
2
= H
,
o
r
CS
1
=
L,
and CS
2
=
L
t
CH
t
CL
t
SS
t
SH
t
SS
t
SH
t
AS
t
AH
A1
A2
A3
B
URS
T CONTINUE
D WITH
NE
W BAS
E
A
D
D
R
E
S
S
t
WS
t
WH
t
CS
S
t
CS
H
t
AD
VS
t
AD
VH
t
OE
t
HZOE
t
LZ
OE
t
CD
t
OH
(A
DV
I
N
S
E
R
T
S W
A
I
T
STATE
)
t
HZC
Q3-4
Q3-3
Q3-2
Q3-
1
Q2-
4
Q2
-3
Q2-
2
Q2-1
Q1-
1
Don
t Ca
r
e
Undef
ine
d
t
CY
C
64Kx36/x32 Synchronous SRAM
- 11 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
TIMI
NG
WAVEFORM
OF W
R
TE CYCLE
CLOCK
ADSP
ADSC
ADDRESS
WRI
T
E
CS
ADV
Data In
t
CH
t
CL
t
SS
t
SH
t
AS
t
AH
A1
A2
A3
(A
DS
C
E
X
TE
NDE
D B
URS
T)
D2-
1
D1
-
1
t
CS
S
t
CS
H
(A
D
V
SU
SP
E
NDS
B
URS
T)
D2
-2
D2-
3
D2-4
D3
-1
D3-
2
D3
-
3
D2-
2
D
3
-4
Q0-
3
Q0-
4
OE
Data Out
t
SS
t
SH
t
WS
t
WH
t
AD
VS
t
ADV
H
t
DS
t
DH
t
HZOE
Don
t Ca
r
e
Undef
ine
d
t
CY
C
64Kx36/x32 Synchronous SRAM
- 12 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
TIMING WAVEFOR
M OF C
O
MBINATION
R
E
AD/WRTE CYC
L
E(ADSP
CONTROLLE
D
,
A
D
SC
=HIGH)
CLOCK
ADSP
ADD
RESS
WRI
T
E
CS
AD
V
OE
Da
ta Out
t
CH
t
CL
t
DS
t
DH
Q3-
2
Da
ta In
t
OH
A1
A2
A3
D2-1
Q3-
1
Q
3
-3
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
AD
VS
t
AD
VH
t
LZ
O
E
t
HZOE
t
CD
t
HZC
Q3-
4
t
LZ
C
Q1-
1
Don
t Care
Unde
fin
e
d
t
CY
C
64Kx36/x32 Synchronous SRAM
- 13 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
TIMING WAVEFOR
M OF S
I
N
G
LE REA
D
/WRITE CYCLE(AD
SC
CON
T
ROLLED , ADS
P
=HIGH)
CLOCK
AD
SC
AD
DRESS
WRIT
E
CS
AD
V
OE
Da
ta In
t
CH
t
CL
t
HZOE
D6
-
1
Da
ta Out
t
WS
t
WH
t
LZ
O
E
t
OH
t
OE
D5-1
D7-1
t
WS
t
WH
t
LZO
E
t
DH
t
DS
A1
A2
A3
A4
A5
A6
A7
A8
A9
Q3-
1
Q1-
1
Q
2
-1
Q4
-1
Q8-
1
t
CSS
t
CS
H
t
SS
t
SH
Q9-
1
Don
t Ca
re
Und
e
f
i
ned
t
CY
C
64Kx36/x32 Synchronous SRAM
- 14 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
TIMING WAVEFORM OF POWER DOWN CYCL
E
CLOCK
AD
SP
AD
DRESS
WRIT
E
CS
AD
V
Da
ta In
t
CH
t
CL
D2-2
OE
t
HZOE
D2
-
1
A1
t
SS
t
SH
Da
ta Out
t
PU
S
AD
SC
ZZ
t
AS
t
AH
t
CS
S
t
CS
H
Sl
ee
p S
t
at
e
Nor
m
a
l
Op
er
at
io
n Mo
d
e
Z
Z
R
e
cove
ry
Cycl
e
A2
t
WS
t
WH
t
LZOE
Q1-
1
t
OE
t
HZC
t
PD
S
ZZ S
e
tu
p Cycle
Don
t Ca
r
e
Undef
ine
d
t
CYC
64Kx36/x32 Synchronous SRAM
- 15 -
Rev 2.0
Nov 2003
K7A203200B
K7A203600B
APPLICATION INFORMATION
The Samsung 64Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
DEPTH EXPANSION
This permits easy secondary cache upgrades from 64K depth to 128K depth without extra logic.
Data
Address
CLK
ADS
64-Bits
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address
Data
ADV
ADSP
64Kx36
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address
Data
ADV
ADSP
64Kx36
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:16]
A
[16]
A
[0:15]
A
[16]
A
[0:15]
I/O
[0:71]
Microprocessor
Clock
ADSP
ADDRESS
Data Out
Bank 0 is selected by CS
2
, and Bank 1 deselected by CS
2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
t
SS
t
SH
A1
A2
WRITE
CS
1
A
n+1
ADV
(Bank 0)
(Bank 1)
Q2-2
Q2-4
Q2-3
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
t
HZC
Bank 0 is deselected by CS
2
, and Bank 1 selected by CS
2
t
CSS
t
CSH
t
CD
t
LZC
[0:n]
Q2-1
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
Don
t Care
Undefined
*Notes : n = 14 32K depth
15 64K depth
16 128K depth
17 256K depth
(ADSP CONTROLLED , ADSC=HIGH)
64Kx36/x32 Synchronous SRAM
- 16 -
Rev 2.0
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