K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 1 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
Document Title
256Kx36 & 256Kx32 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
1.0
2.0
2.1
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
Final
History
Initial draft
1. Delete pass- through
1. Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change I
SB2
form 50mA to 60mA
Change ordering information( remove 225MHz at SPB)
1. Delete 119BGA package
Draft Date
May. 18 . 2001
June. 26. 2001
Aug. 11. 2001
Aug. 28. 2001
Nov. 16. 2001
April. 01. 2002
April. 04. 2003
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 2 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
8Mb SB/SPB Synchronous SRAM Ordering Information
NOTE :
119BGA is Only Supported with K7A801800B-HC16, K7A803600B-HC16 and K7A803609B-HC20.
Org.
Part Number
Mode
VDD
Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz)
PKG
Temp
512Kx18
K7B801825B-QC(I)65/75/85
SB
3.3
6.5/7.5/8.5 ns
Q:
100TQFP
C:
Commercial
Temperature
Range
I:
Industrial
Temperature
Range
K7A801800B-QC(I)16/14
SPB(2E1D)
3.3
167/138 MHz
K7A801809B-QC(I)25/20
SPB(2E1D)
3.3
250/200 MHz
K7A801801B-QC(I)16/14
SPB(2E2D)
3.3
167/138 MHz
K7A801808B-QC(I)25/20
SPB(2E2D)
3.3
250/200 MHz
256Kx32
K7B803225B-QC(I)65/75/85
SB
3.3
6.5/7.5/8.5 ns
K7A803200B-QC(I)16/14
SPB(2E1D)
3.3
167/138 MHz
K7A803209B-QC(I)25/20
SPB(2E1D)
3.3
250/200 MHz
K7A803201B-QC(I)16/14
SPB(2E2D)
3.3
167/138 MHz
K7A803208B-QC(I)25/20
SPB(2E2D)
3.3
250/200 MHz
256Kx36
K7B803625B-QC(I)65/75/85
SB
3.3
6.5/7.5/8.5 ns
K7A803600B-QC(I)16/14
SPB(2E1D)
3.3
167/138 MHz
K7A803609B-QC(I)25/20
SPB(2E1D)
3.3
250/200 MHz
K7A803601B-QC(I)16/14
SPB(2E2D)
3.3
167/138 MHz
K7A803608B-QC(I)25/20
SPB(2E2D)
3.3
250/200 MHz
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 3 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
256Kx36 & 256Kx32 & 512Kx18-bit Synchronous Pipelined Burst SRAM
The K7A803600B, K7A803200B and K7A801800B are
9,437,184-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pen-
tium and Power PC based System.
It is organized as 256K(512K) words of 36/32(18) bits and
integrates address and control registers, a 2-bit burst
address counter and added some new functions for high
performance cache RAM applications; GW, BW , LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by G W, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the systems burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A803600B, K7A803200B and K7A801800B are fab-
ricated using SAMSUNGs high performance CMOS tech-
nology and is available in a 100pin TQFP and Multiple
power and ground pins are utilized to minimize ground
bounce.
GENERAL DESCRIPTION
FEATURES
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
3.3V+0.165V/-0.165V Power Supply.
I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a linear
burst.
Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP ; 2cycle Enable, 1cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A
Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
PARAMETER
Symbol
-16
-14
Unit
Cycle Time
tCYC
6.0
7.2
ns
Clock Access Time
tCD
3.5
3.8
ns
Output Enable Access Time
tOE
3.5
3.8
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb7
BURST CONTROL
LOGIC
BURST
256Kx36/32 , 512Kx18
ADDRESS
CONTROL
OUTPUT
DATA-IN
ADDRESS
COUNTER
MEMORY
ARRAY
REGISTER
REGISTER
BUFFER
LOGIC
C
O
N
T
R
O
L
R
E
G
I
S
T
E
R
C
O
N
T
R
O
L
R
E
G
I
S
T
E
R
A
0
~A
1
A
0
~A
1
or A
2
~A
18
or A
0
~A
18
REGISTER
DQPa ~ DQPd
A
0
~A
17
A
2
~A
17
(x=a,b,c,d or a,b)
DQP
a
,DQP
b
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 4 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
PIN CONFIGURATION
(TOP VIEW)
PIN NAME
Notes :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
3. DQPa~DQPd are NC for K7A803200B
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A
0
- A
17
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WE x(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50
81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
/NC
V
DDQ
V
SSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,41,65,91
17,40,67,90
14,16,38,39,42,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
DQPc/NC
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd/NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa/NC
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
A
6
A
7
C
S
1
C
S
2
W
E
d
W
E
c
W
E
b
W
E
a
C
S
2
V
D
D
V
S
S
C
L
K
G
W
B
W
O
E
A
D
S
C
A
D
S
P
A
D
V
A
8
8
1
A
9
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
A
1
0
A
1
7
N
.
C
.
V
D
D
V
S
S
N
.
C
.
N
.
C
.
A
0
A
1
A
2
A
3
A
4
A
5
3
1
L
B
O
A
1
6
K7A803600B(256Kx36)
K7A803200B(256Kx32)
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 5 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
PIN CONFIGURATION
(TOP VIEW)
PIN NAME
Notes :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A
0
- A
18
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
W Ex
OE
G W
B W
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50
80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
V
DD
V
SS
N.C.
DQa
0
~ a
7
DQb
0
~ b
7
DQPa, Pb
V
DDQ
V
SSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,51,52,53,56,
57,66,75,78,79,95,96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
0
DQb
1
V
SSQ
V
DDQ
DQb
2
DQb
3
N.C.
V
DD
N.C.
V
SS
DQb
4
DQb
5
V
DDQ
V
SSQ
DQb
6
DQb
7
DQPb
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQPa
DQa
7
DQa
6
V
SSQ
V
DDQ
DQa
5
DQa
4
V
SS
N.C.
V
DD
ZZ
DQa
3
DQa
2
V
DDQ
V
SSQ
DQa
1
DQa
0
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
A
6
A
7
C
S
1
C
S
2
N
.
C
.
N
.
C
.
W
E
b
W
E
a
C
S
2
V
D
D
V
S
S
C
L
K
G
W
B
W
O
E
A
D
S
C
A
D
S
P
A
D
V
A
8
8
1
A
9
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
A
1
8
N
.
C
.
V
D
D
V
S
S
N
.
C
.
N
.
C
.
A
0
A
1
A
2
A
3
A
4
A
5
3
1
L
B
O
A
1
6
K7A801800B(512Kx18)
A
1
7
A
10
(20mm x 14mm)
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 6 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
119BGA PACKAGE PIN CONFIGURATIONS
(TOP VIEW)
Only for K7A803600B - HC16(256Kx36)
Note :
* A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
1
2
3
4
5
6
7
A
V
DDQ
A
A
ADSP
A
A
V
DDQ
B
NC
CS
2
A
ADSC
A
A
NC
C
NC
A
A
V
DD
A
A
NC
D
DQc
DQPc
V
SS
NC
V
SS
DQPb
DQb
E
DQc
DQc
V
SS
CS
1
V
SS
DQb
DQb
F
V
DDQ
DQc
V
SS
OE
V
SS
DQb
V
DDQ
G
DQc
DQc
WEc
ADV
WEb
DQb
DQb
H
DQc
DQc
V
SS
GW
V
SS
DQb
DQb
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
DQd
DQd
V
SS
CLK
V
SS
DQa
DQa
L
DQd
DQd
WEd
NC
WEa
DQa
DQa
M
V
DDQ
DQd
V
SS
B W
V
SS
DQa
V
DDQ
N
DQd
DQd
V
SS
A
1
*
V
SS
DQa
DQa
P
DQd
DQPd
V
SS
A
0
*
V
SS
DQPa
DQa
R
NC
A
LBO
V
DD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
A
0
,A
1
ADV
ADSP
ADSC
CLK
CS
1
CS
2
WE x
(x=a,b,c,d)
OE
G W
BW
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Count Address
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
V
DD
V
SS
N.C.
DQa
DQb
DQc
DQd
DQPa~Pd
V
DDQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
Output Power Supply
(2.5V or 3.3V)
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 7 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
K7A801800B - HC16 (512Kx18)
Note :
* A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
1
2
3
4
5
6
7
A
V
DDQ
A
A
ADSP
A
A
V
DDQ
B
NC
CS
2
A
ADSC
A
A
NC
C
NC
A
A
V
DD
A
A
NC
D
DQb
NC
V
SS
NC
V
SS
DQPa
NC
E
NC
DQb
V
SS
CS
1
V
SS
NC
DQa
F
V
DDQ
NC
V
SS
OE
V
SS
DQa
V
DDQ
G
NC
DQb
WEb
ADV
V
SS
NC
DQa
H
DQb
NC
V
SS
GW
V
SS
DQa
NC
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
NC
DQb
V
SS
CLK
V
SS
NC
DQa
L
DQb
NC
V
SS
NC
WEa
DQa
NC
M
V
DDQ
DQb
V
SS
BW
V
SS
NC
V
DDQ
N
DQb
NC
V
SS
A
1
*
V
SS
DQa
NC
P
NC
DQPb
V
SS
A
0
*
V
SS
NC
DQa
R
NC
A
LBO
V
DD
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
119BGA PACKAGE PIN CONFIGURATIONS
(TOP VIEW)
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
A
0
,A
1
ADV
ADSP
ADSC
CLK
CS
1
CS
2
WE x
(x=a,b)
OE
G W
BW
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Count Address
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
V
DD
V
SS
N.C.
DQa
DQb
DQPa~Pb
V
DDQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
Output Power Supply
(2.5V or 3.3V)
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 8 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
FUNCTION DESCRIPTION
The K7A803600B, K7A803200B and K7A801800B are synchronous SRAM designed to support the burst address accessing
sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock
edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS
1
.
All byte write is done by GW(regaedless of BW and W Ex.), and each byte write is performed by the combination of B W and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WE x sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WE b, WE c or WEd) sampled low. The WEa control DQa
0
~ DQa
7
and DQPa, WEb controls DQb
0
~ DQb
7
and DQPb,
W Ec controls DQc
0
~ DQc
7
and DQPc,
and WEd control DQd
0
~ DQd
7
and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
LBO PIN
HIGH
Case 1
Case 2
Case 3
Case 4
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
TABLE
(Linear Burst)
Note
: 1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
LBO PIN
LOW
Case 1
Case 2
Case 3
Case 4
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
ASYNCHRONOUS TRUTH TABLE
OPERATION
ZZ
O E
I/O STATUS
Sleep Mode
H
X
High-Z
Read
L
L
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes
1. X means "Don
t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 9 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
SYNCHRONOUS TRUTH TABLE
NOTE
: 1. X means "Don
t Care". 2. The rising edge of clock is symbolized by
.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS
1
CS
2
CS
2
ADSP ADSC ADV WRITE
CLK
ADDRESS ACCESSED
OPERATION
H
X
X
X
L
X
X
N/A
Not Selected
L
L
X
L
X
X
X
N/A
Not Selected
L
X
H
L
X
X
X
N/A
Not Selected
L
L
X
X
L
X
X
N/A
Not Selected
L
X
H
X
L
X
X
N/A
Not Selected
L
H
L
L
X
X
X
External Address
Begin Burst Read Cycle
L
H
L
H
L
X
L
External Address
Begin Burst Write Cycle
L
H
L
H
L
X
H
External Address
Begin Burst Read Cycle
X
X
X
H
H
L
H
Next Address
Continue Burst Read Cycle
H
X
X
X
H
L
H
Next Address
Continue Burst Read Cycle
X
X
X
H
H
L
L
Next Address
Continue Burst Write Cycle
H
X
X
X
H
L
L
Next Address
Continue Burst Write Cycle
X
X
X
H
H
H
H
Current Address
Suspend Burst Read Cycle
H
X
X
X
H
H
H
Current Address
Suspend Burst Read Cycle
X
X
X
H
H
H
L
Current Address
Suspend Burst Write Cycle
H
X
X
X
H
H
L
Current Address
Suspend Burst Write Cycle
TRUTH TABLES
WRITE TRUTH TABLE
(x36/32)
Notes :
1. X means "Don
t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(
) .
GW
BW
WEa
WEb
WEc
WE d
OPERATION
H
H
X
X
X
X
READ
H
L
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
H
L
H
L
H
H
WRITE BYTE b
H
L
H
H
L
L
WRITE BYTE c and d
H
L
L
L
L
L
WRITE ALL BYTEs
L
X
X
X
X
X
WRITE ALL BYTEs
WRITE TRUTH TABLE
(x18)
Notes :
1. X means "Don
t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(
).
GW
BW
WEa
WEb
OPERATION
H
H
X
X
READ
H
L
H
H
READ
H
L
L
H
WRITE BYTE a
H
L
H
L
WRITE BYTE b
H
L
L
L
WRITE ALL BYTEs
L
X
X
X
WRITE ALL BYTEs
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 10 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
ABSOLUTE MAXIMUM RATINGS*
*Note :
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER
SYMBOL
RATING
UNIT
Voltage on V
DD
Supply Relative to V
SS
V
DD
-0.3 to 4.6
V
Voltage on V
DDQ
Supply Relative to V
SS
V
DDQ
V
DD
V
Voltage on Input Pin Relative to V
SS
V
IN
-0.3 to V
DD
+0.3
V
Voltage on I/O Pin Relative to V
SS
V
IO
-0.3 to V
DDQ
+0.3
V
Power Dissipation
P
D
1.6
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
Commercial
T
OPR
0 to 70
C
Industrial
T
OPR
-40 to 85
C
Storage Temperature Range Under Bias
T
BIAS
-10 to 85
C
CAPACITANCE*
(T
A
=25
C, f=1MHz)
*Note :
Sampled not 100% tested.
PARAMETER
SYMBOL
TEST CONDITION
MIN
MAX
UNIT
Input Capacitance
C
IN
V
IN
=0V
-
5
pF
Output Capacitance
C
OUT
V
OUT
=0V
-
7
pF
OPERATING CONDITIONS at 3.3V I/O
(0
C
T
A
70
C)
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER
SYMBOL
MIN
Typ.
MAX
UNIT
Supply Voltage
V
DD
3.135
3.3
3.465
V
V
DDQ
3.135
3.3
3.465
V
Ground
V
SS
0
0
0
V
OPERATING CONDITIONS at 2.5V I/O
(0
C
T
A
70
C)
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER
SYMBOL
MIN
Typ.
MAX
UNIT
Supply Voltage
V
DD
3.135
3.3
3.465
V
V
DDQ
2.375
2.5
2.9
V
Ground
V
SS
0
0
0
V
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 11 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
DC ELECTRICAL CHARACTERISTICS
(V
DD
=3.3V+0.165V/-0.165V, T
A
=0
C to +70
C)
Notes :
1.The above parameters are also guaranteed at industrial temperature range.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. Data states are all zero.
4. In Case of I/O Pins, the Max. V
IH
=V
DDQ
+0.3V.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT NOTES
Input Leakage Current(except ZZ)
I
IL
V
DD
= Max ; V
IN
=V
SS
to V
DD
-2
+2
A
Output Leakage Current
I
OL
Output Disabled, V
OUT
=V
SS
to V
DDQ
-2
+2
A
Operating Current
I
CC
Device Selected, I
OUT
=0mA,
ZZ
V
IL ,
Cycle Time
t
CYC
Min
-16
-
350
mA
1,2
-14
-
300
Standby Current
I
SB
Device deselected, I
OUT
=0mA, ZZ
V
IL
,
f=Max, All Inputs
0.2V or
V
DD
-0.2V
-16
-
130
mA
-14
-
120
I
SB1
Device deselected, I
OUT
=0mA, ZZ
0.2V,
f = 0, All Inputs=fixed (V
DD
-0.2V or 0.2V)
-
100
mA
I
SB2
Device deselected, I
OUT
=0mA, ZZ
V
DD
-0.2V,
f=Max, All Inputs
V
IL
or
V
IH
-
60
mA
Output Low Voltage(3.3V I/O)
V
OL
I
OL
=8.0mA
-
0.4
V
Output High Voltage(3.3V I/O)
V
OH
I
OH
=-4.0mA
2.4
-
V
Output Low Voltage(2.5V I/O)
V
OL
I
OL
=1.0mA
-
0.4
V
Output High Voltage(2.5V I/O)
V
OH
I
OH
=-1.0mA
2.0
-
V
Input Low Voltage(3.3V I/O)
V
IL
-0.3*
0.8
V
Input High Voltage(3.3V I/O)
V
IH
2.0
V
DD
+0.3**
V
3
Input Low Voltage(2.5V I/O)
V
IL
-0.3*
0.7
V
Input High Voltage(2.5V I/O)
V
IH
1.7
V
DD
+0.3**
V
3
V
SS
V
IH
V
SS-
1.0V
20% t
CYC
(MIN)
(V
DD
=3.3V+0.165V/-0.165V,V
DDQ
=3.3V+0.165/-0.165V or V
DD
=3.3V+0.165V/-0.165V,V
DDQ
=2.5V+0.4V/-0.125V, T
A
=0to70
C)
TEST CONDITIONS
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Value
Input Pulse Level(for 3.3V I/O)
0 to 3.0V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
1.0V/ns
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
1.0V/ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
V
DDQ
/2
Output Load
See Fig. 1
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 12 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
AC TIMING CHARACTERISTICS
(V
DD
=3.3V+0.165V/-0.165V, T
A
=0
C to +70
C)
Notes :
1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
PARAMETER
Symbol
-16
-14
UNIT
MIN
MAX
MIN
MAX
Cycle Time
t
CYC
6.0
-
7.2
-
ns
Clock Access Time
t
CD
-
3.5
-
3.8
ns
Output Enable to Data Valid
t
OE
-
3.5
-
3.8
ns
Clock High to Output Low-Z
t
LZC
0
-
0
-
ns
Output Hold from Clock High
t
OH
1.5
-
1.5
-
ns
Output Enable Low to Output Low-Z
t
LZOE
0
-
0
-
ns
Output Enable High to Output High-Z
t
HZOE
-
3.0
-
3.5
ns
Clock High to Output High-Z
t
HZC
1.5
3.0
1.5
3.5
ns
Clock High Pulse Width
t
CH
2.3
-
2.5
-
ns
Clock Low Pulse Width
t
CL
2.3
-
2.5
-
ns
Address Setup to Clock High
t
AS
1.5
-
1.5
-
ns
Address Status Setup to Clock High
t
SS
1.5
-
1.5
-
ns
Data Setup to Clock High
t
DS
1.5
-
1.5
-
ns
Write Setup to Clock High (GW , BW , WE
X
)
t
WS
1.5
-
1.5
-
ns
Address Advance Setup to Clock High
t
ADVS
1.5
-
1.5
-
ns
Chip Select Setup to Clock High
t
CSS
1.5
-
1.5
-
ns
Address Hold from Clock High
t
AH
0.5
-
0.5
-
ns
Address Status Hold from Clock High
t
SH
0.5
-
0.5
-
ns
Data Hold from Clock High
t
DH
0.5
-
0.5
-
ns
Write Hold from Clock High (G W, BW, WE
X
)
t
WH
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
t
ADVH
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
t
CSH
0.5
-
0.5
-
ns
ZZ High to Power Down
t
PDS
2
-
2
-
cycle
ZZ Low to Power Up
t
PUS
2
-
2
-
cycle
Output Load(B),
(for t
LZC
, t
LZOE
, t
HZOE
& t
HZC
)
Dout
353
/
1538
5pF*
+3.3V for 3.3V I/O
319
/
1667
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50
RL=50
VL=1.5V for 3.3V I/O
V
DDQ
/2 for 2.5V I/O
/+2.5V for 2.5V I/O
30pF*
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 13 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to V
SS
to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to V
DD
through a resistor. TDO should be left unconnected.
TAP Controller State Diagram
JTAG Block Diagram
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
TDO
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
0
1
1
1
1
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
1
1
1
1
JTAG Instruction Coding
NOTE
:
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to V
SS
when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
IR2 IR1 IR0
Instruction
TDO Output
Notes
0
0
0 EXTEST
Boundary Scan Register
1
0
0
1 IDCODE
Identification Register
3
0
1
0 SAMPLE-Z
Boundary Scan Register
2
0
1
1 BYPASS
Bypass Register
4
1
0
0 SAMPLE
Boundary Scan Register
5
1
0
1 RESERVED Do Not Use
6
1
1
0 BYPASS
Bypass Register
4
1
1
1 BYPASS
Bypass Register
4
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 14 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
ID REGISTER DEFINITION
Part
Revision Number
(31:28)
Part Configuration
(27:18)
Vendor Definition
(17:12)
Samsung JEDEC Code
(11: 1)
Start Bit(0)
256Kx36
0000
00110 00100
XXXXXX
00001001110
1
512Kx18
0000
00111 00011
XXXXXX
00001001110
1
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
ID Register
Boundary Scan
256Kx36
3 bits
1 bits
32 bits
70 bits
512Kx18
3 bits
1 bits
32 bits
70 bits
119BGA BOUNDARY SCAN EXIT ORDER(x36)
36
4B
ADSC
OE
4F
35
37
4E
CS
1
ADV
4G
34
38
4H
GW
CLK
4K
33
39
3G
WEc
BW
4M
32
40
3C
A
ADSP
4A
31
41
3B
A
WEb
5G
30
42
3A
A
A
5C
29
43
2B
CS2
A
5B
28
44
2C
A
A
5A
27
45
2A
A
A
6B
26
46
2D
DQPc
A
6A
25
47
1E
DQc
A
6C
24
48
2F
DQc
DQPb
6D
23
49
1G
DQc
DQb
6E
22
50
2H
DQc
DQb
6G
21
51
1D
DQc
DQb
7H
20
52
2E
DQc
DQb
7D
19
53
2G
DQc
DQb
7E
18
54
1H
DQc
DQb
6F
17
55
2K
DQd
DQb
7G
16
56
1L
DQd
DQb
6H
15
57
2M
DQd
DQa
7K
14
58
1N
DQd
DQa
6L
13
59
1P
DQd
DQa
6N
12
60
1K
DQd
DQa
7P
11
61
2L
DQd
DQa
6K
10
62
2N
DQd
DQa
7L
9
63
2P
DQPd
DQa
6M
8
64
3R
LBO
DQa
7N
7
65
3L
WEd
DQPa
6P
6
66
2R
A
ZZ
7T
5
67
3T
A
A
6R
4
68
4N
A1
WEa
5L
3
69
4P
A0
A
5T
2
70
2T
NC
A
4T
1
119BGA BOUNDARY SCAN EXIT ORDER(x18)
36
4B
ADSC
OE
4F
35
37
4E
CS
1
ADV
4G
34
38
4H
G W
CLK
4K
33
39
3G
WEb
BW
4M
32
40
3C
A
ADSP
4A
31
41
3B
A
NC
5G
30
42
3A
A
A
5C
29
43
2B
CS2
A
5B
28
44
2C
A
A
5A
27
45
2A
A
A
6B
26
46
2D
NC
A
6A
25
47
1E
NC
A
6C
24
48
2F
NC
NC
7D
23
49
1G
NC
NC
6E
22
50
2H
NC
NC
6G
21
51
1D
DQb
NC
7H
20
52
2E
DQb
DQPa
6D
19
53
2G
DQb
DQa
7E
18
54
1H
DQb
DQa
6F
17
55
2K
DQb
DQa
7G
16
56
1L
DQb
DQa
6H
15
57
2M
DQb
DQa
7K
14
58
1N
DQb
DQa
6L
13
59
2P
DQPb
DQa
6N
12
60
1K
NC
DQa
7P
11
61
2L
NC
NC
6K
10
62
2N
NC
NC
7L
9
63
1P
NC
NC
6M
8
64
3R
LBO
NC
7N
7
65
3L
NC
NC
6P
6
66
2R
A
ZZ
7T
5
67
3T
A
A
6R
4
68
4N
A1
WE a
5L
3
69
4P
A0
A
5T
2
70
2T
A
A
6T
1
NOTE
: 1. NC ; Don't care.
2.
119BGA is Only Supported with K7A801800B-HC16, K7A803600B-HC16 and K7A803609B-HC20.
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 15 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
JTAG DC OPERATING CONDITIONS
NOTE
: The input level of SRAM pin is to follow the SRAM DC specification
.
1. In Case of I/O Pins, the Max. V
IH
=V
DDQ
+0.3V
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
V
DD
3.135
3.3
3.465
V
Input High Level ( 3.3V I/O / 2.5V I/O )
V
IH
2.0 / 1.7
-
V
DD
+0.3
V
1
Input Low Level ( 3.3V I/O / 2.5V I/O )
V
IL
-0.3
-
0.8 / 0.7
V
Output High Voltage ( 3.3V I/O / 2.5V I/O )
V
OH
2.4 / 2.0
-
-
V
Output Low Voltage ( 3.3V I/O / 2.5V I/O )
V
OL
-
-
0.4 / 0.4
V
JTAG TIMING DIAGRAM
JTAG AC Characteristics
Parameter
Symbol
Min
Max
Unit
Note
TCK Cycle Time
t
CHCH
50
-
ns
TCK High Pulse Width
t
CHCL
20
-
ns
TCK Low Pulse Width
t
CLCH
20
-
ns
TMS Input Setup Time
t
MVCH
5
-
ns
TMS Input Hold Time
t
CHMX
5
-
ns
TDI Input Setup Time
t
DVCH
5
-
ns
TDI Input Hold Time
t
CHDX
5
-
ns
SRAM Input Setup Time
t
SVCH
5
-
ns
SRAM Input Hold Time
t
CHSX
5
-
ns
Clock Low to Output Valid
t
CLQV
0
10
ns
JTAG AC TEST CONDITIONS
Parameter
Symbol
Min
Unit
Note
Input High/Low Level ( 3.3V I/O / 2.5V I/O )
V
IH
/V
IL
3.0 / 0 , 2.5 / 0
V
Input Rise/Fall Time ( 3.3V I/O / 2.5V I/O )
TR/TF
1.0 / 1.0 , 1.0 /1 .0
ns
Input and Output Timing Reference Level
V
DDQ
/2
V
TCK
TMS
TDI
PI
t
CHCH
t
MVCH
t
CHMX
t
CHCL
t
CLCH
t
DVCH
t
CHDX
t
CLQV
TDO
(SRAM)
t
SVCH
t
CHSX
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 16 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
C
L
O
C
K
A
D
S
P
A
D
S
C
A
D
D
R
E
S
S
W
R
I
T
E
C
S
A
D
V
O
E
D
a
t
a
O
u
t
T
I
M
I
N
G
W
A
V
E
F
O
R
M
O
F
R
E
A
D
C
Y
C
L
E
N
O
T
E
S
:
W
R
I
T
E
=
L
m
e
a
n
s
G
W
=
L
,
o
r
G
W
=
H
,
B
W
=
L
,
W
E
x
=
L
C
S
=
L
m
e
a
n
s
C
S
1
=
L
,
C
S
2
=
H
a
n
d
C
S
2
=
L
C
S
=
H
m
e
a
n
s
C
S
1
=
H
,
o
r
C
S
1
=
L
a
n
d
C
S
2
=
H
,
o
r
C
S
1
=
L
,
a
n
d
C
S
2
=
L
t
C
H
t
C
L
t
S
S
t
S
H
t
S
S
t
S
H
t
A
S
t
A
H
A
1
A
2
A
3
B
U
R
S
T
C
O
N
T
I
N
U
E
D
W
I
T
H
N
E
W
B
A
S
E
A
D
D
R
E
S
S
t
W
S
t
W
H
t
C
S
S
t
C
S
H
t
A
D
V
S
t
A
D
V
H
t
O
E
t
H
Z
O
E
t
L
Z
O
E
t
C
D
t
O
H
(
A
D
V
I
N
S
E
R
T
S
W
A
I
T
S
T
A
T
E
)
t
H
Z
C
Q
3
-
4
Q
3
-
3
Q
3
-
2
Q
3
-
1
Q
2
-
4
Q
2
-
3
Q
2
-
2
Q
2
-
1
Q
1
-
1
D
o
n
t
C
a
r
e
U
n
d
e
f
i
n
e
d
t
C
Y
C
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 17 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
T
I
M
I
N
G
W
A
V
E
F
O
R
M
O
F
W
R
T
E
C
Y
C
L
E
C
L
O
C
K
A
D
S
P
A
D
S
C
A
D
D
R
E
S
S
W
R
I
T
E
C
S
A
D
V
D
a
t
a
I
n
t
C
H
t
C
L
t
S
S
t
S
H
t
A
S
t
A
H
A
1
A
2
A
3
(
A
D
S
C
E
X
T
E
N
D
E
D
B
U
R
S
T
)
D
2
-
1
D
1
-
1
t
C
S
S
t
C
S
H
(
A
D
V
S
U
S
P
E
N
D
S
B
U
R
S
T
)
D
2
-
2
D
2
-
3
D
2
-
4
D
3
-
1
D
3
-
2
D
3
-
3
D
2
-
2
D
3
-
4
Q
0
-
3
Q
0
-
4
O
E
D
a
t
a
O
u
t
t
S
S
t
S
H
t
W
S
t
W
H
t
A
D
V
S
t
A
D
V
H
t
D
S
t
D
H
t
H
Z
O
E
D
o
n
t
C
a
r
e
U
n
d
e
f
i
n
e
d
t
C
Y
C
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 18 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
T
I
M
I
N
G
W
A
V
E
F
O
R
M
O
F
C
O
M
B
I
N
A
T
I
O
N
R
E
A
D
/
W
R
T
E
C
Y
C
L
E
(
A
D
S
P
C
O
N
T
R
O
L
L
E
D
,
A
D
S
C
=
H
I
G
H
)
C
L
O
C
K
A
D
S
P
A
D
D
R
E
S
S
W
R
I
T
E
C
S
A
D
V
O
E
D
a
t
a
O
u
t
t
C
H
t
C
L
t
D
S
t
D
H
Q
3
-
2
D
a
t
a
I
n
t
O
H
A
1
A
2
A
3
D
2
-
1
Q
3
-
1
Q
3
-
3
t
S
S
t
S
H
t
A
S
t
A
H
t
W
S
t
W
H
t
A
D
V
S
t
A
D
V
H
t
L
Z
O
E
t
H
Z
O
E
t
C
D
t
H
Z
C
Q
3
-
4
t
L
Z
C
Q
1
-
1
D
o
n
t
C
a
r
e
U
n
d
e
f
i
n
e
d
t
C
Y
C
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 19 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
T
I
M
I
N
G
W
A
V
E
F
O
R
M
O
F
S
I
N
G
L
E
R
E
A
D
/
W
R
I
T
E
C
Y
C
L
E
(
A
D
S
C
C
O
N
T
R
O
L
L
E
D
,
A
D
S
P
=
H
I
G
H
)
C
L
O
C
K
A
D
S
C
A
D
D
R
E
S
S
W
R
I
T
E
C
S
A
D
V
O
E
D
a
t
a
I
n
t
C
H
t
C
L
t
H
Z
O
E
D
6
-
1
D
a
t
a
O
u
t
t
W
S
t
W
H
t
L
Z
O
E
t
O
H
t
O
E
D
5
-
1
D
7
-
1
t
W
S
t
W
H
t
L
Z
O
E
t
D
H
t
D
S
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
Q
3
-
1
Q
1
-
1
Q
2
-
1
Q
4
-
1
Q
8
-
1
t
C
S
S
t
C
S
H
t
S
S
t
S
H
Q
9
-
1
D
o
n
t
C
a
r
e
U
n
d
e
f
i
n
e
d
t
C
Y
C
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 20 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
T
I
M
I
N
G
W
A
V
E
F
O
R
M
O
F
P
O
W
E
R
D
O
W
N
C
Y
C
L
E
C
L
O
C
K
A
D
S
P
A
D
D
R
E
S
S
W
R
I
T
E
C
S
A
D
V
D
a
t
a
I
n
t
C
H
t
C
L
D
2
-
2
O
E
t
H
Z
O
E
D
2
-
1
A
1
t
S
S
t
S
H
D
a
t
a
O
u
t
t
P
U
S
A
D
S
C
Z
Z
t
A
S
t
A
H
t
C
S
S
t
C
S
H
S
l
e
e
p
S
t
a
t
e
N
o
r
m
a
l
O
p
e
r
a
t
i
o
n
M
o
d
e
Z
Z
R
e
c
o
v
e
r
y
C
y
c
l
e
A
2
t
W
S
t
W
H
t
L
Z
O
E
Q
1
-
1
t
O
E
t
H
Z
C
t
P
D
S
Z
Z
S
e
t
u
p
C
y
c
l
e
D
o
n
t
C
a
r
e
U
n
d
e
f
i
n
e
d
t
C
Y
C
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 21 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
APPLICATION INFORMATION
The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
DEPTH EXPANSION
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
Data
Address
CLK
ADS
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
256Kx36
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
256Kx36
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:18]
A
[18]
A
[0:17]
A
[18]
A
[0:17]
I/O
[0:71]
Microprocessor
Clock
ADSP
ADDRESS
Data Out
Bank 0 is selected by CS
2
, and Bank 1 deselected by CS
2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
t
SS
t
SH
A1
A2
WRITE
CS
1
A
n+1
ADV
(Bank 0)
(Bank 1)
Q2-2
Q2-4
Q2-3
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
t
HZC
Bank 0 is deselected by CS
2
, and Bank 1 selected by CS
2
t
CSS
t
CSH
t
CD
t
LZC
[0:n]
Q2-1
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
Don
t Care
Undefined
(ADSP CONTROLLED , ADSC=HIGH)
*Notes :
n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 22 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
APPLICATION INFORMATION
DEPTH EXPANSION
Data
Address
CLK
ADS
Microprocessor
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
512Kx18
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
512Kx18
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:19]
A
[19]
A
[0:18]
A
[19]
A
[0:18]
I/O
[0:71]
Clock
ADSP
ADDRESS
Data Out
Bank 0 is selected by CS
2
, and Bank 1 deselected by CS
2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
t
SS
tSH
Don
t Care
A1
A2
WRITE
CS
1
A
n+1
ADV
(Bank 0)
(Bank 1)
Q2-2
Q2-4
Q2-3
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
tHZC
Bank 0 is deselected by CS
2
, and Bank 1 selected by CS
2
t
CSS
tCSH
t
CD
t
LZC
[0:n]
Undefined
Q2-1
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
The Samsung 512Kx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
*Notes :
n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 23 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
PACKAGE DIMENSIONS
0.10 MAX
0~8
22.00
0.30
20.00
0.20
16.00
0.30
14.00
0.20
1.40
0.10
1.60 MAX
0.05 MIN
(0.58)
0.50
0.10
#1
(0.83)
0.50
0.10
100-TQFP-1420A
0.65
0.30
0.10
0.10 MAX
+ 0.10
- 0.05
0.127
Units ; millimeters/Inches
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
- 24 -
Rev 2.1
April 2003
K7A803200B
K7A803600B
119BGA PACKAGE DIMENSIONS
0.750
0.15
1.27
1.27
12.50
0.10
0.60
0.10
0.60
0.10
1.50REF
C1.00
C0.70
14.00
0.10
22.00
0.10
20.50
0.10
Notes
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 Max.
3. PCB to Cavity Offset : 0.10 Max.
Indicator of
Ball(1A) Location
NOTE :
119BGA is Only Supported with K7A801800B-HC16, K7A803600B-HC16 and K7A803609B-HC20.
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