K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 1 -

Rev 3.0

May 1999

K7A803601M

Document Title

256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Revision History

Rev. No.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

1.0

2.0

3.0

Remark

Preliminary

Final

History

Initial draft

Modify DC characteristics( Input Leakage Current test Conditions)
form V

to V

to Max.

Remove 119BGA Package Type.

Change DC Characteristics.
I

value from 65mA to 110mA at -72

value from 60mA to 110mA at -85

value from 50mA to 100mA at -10

SB1

value from 10mA to 30mA

SB2

value from 10mA to 30mA

1. Changed t

from 4.0ns to 4.2ns at -85.

Changed t

from 4.0ns to 4.2ns at -85.

2. Changed DC condition at Icc and parameters
Icc ; from 375mA to 400mA at -72,
from 340mA to 380mA at -85,
from 300mA to 350mA at -10,
I

; from 110mA to 130mA at -72,

from 110mA to 130mA at -85,
from 100mA to 120mA at -10

DDQ

Supply voltage( 2.5V )

Changed V

Max value from 0.2V to 0.4V at 2.5V I/O.

Final spec Release.

1. Remove

DDQ

Supply voltage( 2.5V I/O )

1. Add

DDQ

Supply voltage( 2.5V I/O )

Draft Date

May. 07 . 1998

June .08. 1998

Aug. 20. 1998

Aug. 27. 1998

Sep. 09. 1998

Dec. 10. 1998

Dec. 23. 1998

Jan. 29. 1999

Feb. 25. 1999

May. 13. 1999

K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 2 -

Rev 3.0

May 1999

K7A803601M

256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM

The K7A803601M and K7A801801M are 9,437,184-bit Syn-

chronous Static Random Access Memory designed for high

performance second level cache of Pentium and Power PC
based System.

It is organized as 256K(512K) words of 36(18) bits and inte-

grates address and control registers, a 2-bit burst address

counter and added some new functions for high performance

cache RAM applications; GW, BW, LBO, ZZ. Write cycles are

internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-

formed by the combination of WEx and BW when GW is high.

And with CS

high, ADSP is blocked to control signals.

Burst cycle can be initiated with either the address status pro-

cessor(ADSP) or address status cache controller(ADSC)

inputs. Subsequent burst addresses are generated internally in
the system

s burst sequence and are controlled by the burst

address advance(ADV) input.

LBO pin is DC operated and determines burst sequence(linear

or interleaved).

ZZ pin controls Power Down State and reduces Stand-by cur-

rent regardless of CLK.
The K7A803601M and K7A801801M are fabricated using SAM-

SUNG

s high performance CMOS technology and is available

in a 100pin TQFP package. Multiple power and ground pins are

utilized to minimize ground bounce.

GENERAL DESCRIPTION

FEATURES

LOGIC BLOCK DIAGRAM

�

Synchronous Operation.

�

2 Stage Pipelined operation with 4 Burst.

�

On-Chip Address Counter.

�

Self-Timed Write Cycle.

�

On-Chip Address and Control Registers.

�

3.3V+0.165V/-0.165V Power Supply.

� I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
�

5V Tolerant Inputs Except I/O Pins.

�

Byte Writable Function.

�

Global Write Enable Controls a full bus-width write.

�

Power Down State via ZZ Signal.

�

LBO Pin allows a choice of either a interleaved burst or a lin-

ear burst.

�

Three Chip Enables for simple depth expansion with No Data

Contention only for TQFP ; 2cycle Enable, 2cycle Disable.

�

Asynchronous Output Enable Control.

�

ADSP, ADSC, ADV Burst Control Pins.

�

TTL-Level Three-State Output.

�

100-TQFP-1420A Package

CLK

LBO

ADV

ADSC

ADSP

WEx

DQa

~ DQd

or DQa0 ~ DQb7

BURST CONTROL

LOGIC

BURST

256Kx36 , 512Kx18

ADDRESS

CONTROL

OUTPUT

DATA-IN

ADDRESS
COUNTER

MEMORY

ARRAY

REGISTER

BUFFER

LOGIC

I
S

or A

REGISTER

DQPa ~ DQPd

(x=a,b,c,d or a,b)

DQPa,DQPb

FAST ACCESS TIMES

PARAMETER

Symbol

-14

-11

-10

Unit

Cycle Time

CYC

7.2

8.5

Clock Access Time

4.0

4.2

4.5

Output Enable Access Time

4.0

4.2

4.5

K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 3 -

Rev 3.0

May 1999

K7A803601M

PIN CONFIGURATION

(TOP VIEW)

PIN NAME

Note : 1. A

and A

are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

2. The pin 42 is reserved for address bit for the 16Mb .

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

- A

ADV
ADSP
ADSC
CLK
CS

WEx(x=a,b,c,d)
OE
GW
BW
ZZ
LBO

Address Inputs

Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control

32,33,34,35,36,37,43
44,45,46,47,48,49,50
81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31

N.C.

DQa

DQb

DQc

DQd

DQPa~P

DDQ

SSQ

Power Supply(+3.3V)
Ground
No Connect

Data Inputs/Outputs

Output Power Supply
(2.5V or 3.3V)
Output Ground

15,41,65,91
17,40,67,90
14,16,38,39,42,66

52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77

5,10,21,26,55,60,71,76

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

100 Pin TQFP

(20mm x 14mm)

DQPc

DQc

DDQ

SSQ

DQc

SSQ

DDQ

DQc

N.C.

DQd

DDQ

SSQ

DQd

SSQ

DDQ

DQd

DQPd

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQPb
DQb

DQb

DDQ

SSQ

DQb

SSQ

DDQ

DQb

N.C.
V

ZZ
DQa

DQa

DDQ

SSQ

DQa

SSQ

DDQ

DQa

DQPa

.
C

K7A803601M(256Kx36)

K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 4 -

Rev 3.0

May 1999

K7A803601M

PIN CONFIGURATION

(TOP VIEW)

PIN NAME

Note : 1. A

and A

are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

2. The pin 42 is reserved for address bit for the 16Mb .

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

- A

ADV
ADSP
ADSC
CLK
CS

WEx
OE
GW
BW
ZZ
LBO

Address Inputs

32,33,34,35,36,37,43
44,45,46,47,48,49,50
80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31

N.C.

DQa

~ a

DQb

~ b

DQPa, Pb
V

DDQ

SSQ

Power Supply(+3.3V)
Ground
No Connect

Data Inputs/Outputs

Output Power Supply
(2.5V or 3.3V)
Output Ground

15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,51,52,53,56,
57,66,75,78,79,95,96

58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77

5,10,21,26,55,60,71,76

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

100 Pin TQFP

(20mm x 14mm)

N.C.
N.C.
N.C.

DDQ

SSQ

N.C.
N.C.

DQb

SSQ

DDQ

DQb

N.C.

DQb

DDQ

SSQ

DQb

DQPb

N.C.

SSQ

DDQ

N.C.
N.C.
N.C.

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

N.C.
N.C.
V

DDQ

SSQ

N.C.
DQPa
DQa

DQa

SSQ

DDQ

DQa

N.C.
V

ZZ
DQa

DQa

DDQ

SSQ

DQa

N.C.
N.C.
V

SSQ

DDQ

N.C.
N.C.
N.C.

.
C

K7A801801M(512Kx18)

K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 5 -

Rev 3.0

May 1999

K7A803601M

FUNCTION DESCRIPTION

The K7A803601M and K7A801801M are synchronous SRAM designed to support the burst address accessing sequence of the
Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and
duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS

All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa

~ DQa

and DQPa, WEb controls DQb

~ DQb

and DQPb,

WEc controls DQc

~ DQc

and DQPc,

and WEd control DQd

~ DQd

and DQPd. Read or write cycle may also be initi-

ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is selected.

BURST SEQUENCE TABLE

(Interleaved Burst)

LBO PIN

HIGH

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0
0
1
1

0
1
0
1

0
0
1
1

1
0
1
0

1
1
0
0

0
1
0
1

1
1
0
0

1
0
1
0

BQ TABLE

(Linear Burst)

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed

LBO PIN

LOW

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0
0
1
1

0
1
0
1

0
1
1
0

1
0
1
0

1
1
0
0

0
1
0
1

1
0
0
1

1
0
1
0

ASYNCHRONOUS TRUTH TABLE

OPERATION

I/O Status

Sleep Mode

High-Z

Read

High-Z

Write

Din, High-Z

Deselected

High-Z

Notes

1. X means "Don

t Care".

2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be

disabled with OE, otherwise data bus contention will occur.

4. Sleep Mode means power down state of which stand-by current does

not depend on cycle time.

5. Deselected means power down state of which stand-by current

depends on cycle time.

K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 6 -

Rev 3.0

May 1999

K7A803601M

SYNCHRONOUS TRUTH TABLE

Notes : 1. X means "Don

t Care". 2. The rising edge of clock is symbolized by

3. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

4. Operation finally depends on status of asynchronous input pins(ZZ and OE).

ADSP ADSC

ADV

WRITE

CLK

ADDRESS ACCESSED

OPERATION

N/A

Not Selected

N/A

Not Selected

N/A

Not Selected

N/A

Not Selected

N/A

Not Selected

External Address

Begin Burst Read Cycle

External Address

Begin Burst Write Cycle

External Address

Begin Burst Read Cycle

Next Address

Continue Burst Read Cycle

Next Address

Continue Burst Read Cycle

Next Address

Continue Burst Write Cycle

Next Address

Continue Burst Write Cycle

Current Address

Suspend Burst Read Cycle

Current Address

Suspend Burst Read Cycle

Current Address

Suspend Burst Write Cycle

Current Address

Suspend Burst Write Cycle

TRUTH TABLES

WRITE TRUTH TABLE

(x36)

Note : 1. X means "Don

t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(

WEa

WEb

WEc

WEd

OPERATION

READ

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c and d

WRITE ALL BYTEs

WRITE TRUTH TABLE

(x18)

Note : 1. X means "Don

t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(

WEa

WEb

OPERATION

READ

WRITE BYTE a

WRITE BYTE b

WRITE ALL BYTEs

K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 7 -

Rev 3.0

May 1999

K7A803601M

PASS-THROUGH TRUTH TABLE

Note : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle.

PREVIOUS CYCLE

PRESENT CYCLE

NEXT CYCLE

OPERATION

WRITE

OPERATION

WRITE

Write Cycle, All bytes
Address=An-1, Data=Dn-1

All L

Initiate Read Cycle
Address=An
Data=Qn-1 for all bytes

Read Cycle
Data=Qn

Write Cycle, All bytes
Address=An-1, Data=Dn-1

All L

No new cycle
Data=Qn-1 for all bytes

No carryover from
previous cycle

Write Cycle, All bytes
Address=An-1, Data=Dn-1

All L

No new cycle
Data=High-Z

No carryover from
previous cycle

Write Cycle, One byte
Address=An-1, Data=Dn-1

One L

Initiate Read Cycle
Address=An
Data=Qn-1 for one byte

Read Cycle
Data=Qn

Write Cycle, One byte
Address=An-1, Data=Dn-1

One L

No new cycle
Data=Qn-1 for one byte

No carryover from
previous cycle

ABSOLUTE MAXIMUM RATINGS*

*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

PARAMETER

SYMBOL

RATING

UNIT

Voltage on V

Supply Relative to V

-0.3 to 4.6

Voltage on V

DDQ

Supply Relative to V

DDQ

Voltage on Input Pin Relative to V

-0.3 to 4.6

Voltage on I/O Pin Relative to V

-0.3 to V

DDQ

+0.5

Power Dissipation

1.6

Storage Temperature

STG

-65 to 150

�

Operating Temperature

OPR

0 to 70

�

Storage Temperature Range Under Bias

BIAS

-10 to 85

�

CAPACITANCE*

=25

�

C, f=1MHz)

*Note : Sampled not 100% tested.

PARAMETER

SYMBOL

TEST CONDITION

MIN

MAX

UNIT

Input Capacitance

=0V

Output Capacitance

OUT

=0V

OPERATING CONDITIONS at 3.3V I/O

�

PARAMETER

SYMBOL

MIN

Typ.

MAX

UNIT

Supply Voltage

3.135

3.3

3.465

DDQ

3.135

3.3

3.465

Ground

OPERATING CONDITIONS at 2.5V I/O

�

PARAMETER

SYMBOL

MIN

Typ.

MAX

UNIT

Supply Voltage

3.135

3.3

3.465

DDQ

2.375

2.5

2.9

Ground

K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 8 -

Rev 3.0

May 1999

K7A803601M

DC ELECTRICAL CHARACTERISTICS

=3.3V+0.165V/-0.165V, T

�

C to +70

�

Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. V

DDQ

+0.3V

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

NOTES

Input Leakage Current(except ZZ)

=Max ; V

to V

-2

�

Output Leakage Current

Output Disabled, V

OUT

to V

DDQ

-2

�

Operating Current

Device Selected, I

OUT

=0mA,

IL ,

Cycle Time

CYC

Min

-14

400

1,2

-11

380

-10

350

Standby Current

Device deselected, I

OUT

=0mA,

, f=Max, All Inputs

0.2V or

-0.2V

-14

130

-11

130

-10

120

SB1

Device deselected, I

OUT

=0mA, ZZ

0.2V,

f =0, All Inputs=fixed (V

-0.2V or 0.2V)

SB2

Device deselected, I

OUT

=0mA, ZZ

-0.2V,

f=Max, All Inputs

Output Low Voltage(3.3V I/O)

=8.0mA

0.4

Output High Voltage(3.3V I/O)

=-4.0mA

2.4

Output Low Voltage(2.5V I/O)

=1.0mA

0.4

Output High Voltage(2.5V I/O)

=-1.0mA

2.0

Input Low Voltage(3.3V I/O)

-0.3*

0.8

Input High Voltage(3.3V I/O)

2.0

+0.5**

Input Low Voltage(2.5V I/O)

-0.3*

0.7

Input High Voltage(2.5V I/O)

1.7

+0.5**

SS-

1.0V

20% t

CYC

(MIN)

=3.3V+0.165V/-0.165V,V

DDQ

=3.3V+0.165/-0.165V or V

=3.3V+0.165V/-0.165V,V

DDQ

=2.5V+0.4V/-0.125V, T

=0to70

�

TEST CONDITIONS

PARAMETER

VALUE

Input Pulse Level(for 3.3V I/O)

0 to 3.0V

Input Pulse Level(for 2.5V I/O)

0 to 2.5V

Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)

1.0V/ns

Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)

1.0V/ns

Input and Output Timing Reference Levels for 3.3V I/O

1.5V

Input and Output Timing Reference Levels for 2.5V I/O

DDQ

Output Load

See Fig. 1

K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 9 -

Rev 3.0

May 1999

K7A803601M

AC TIMING CHARACTERISTICS

=3.3V+0.165V/-0.165V, T

�

C to +70

�

Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and

CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
4. At any given voltage and temperature, t

HZC

is less than t

LZC

PARAMETER

SYMBOL

-14

-11

-10

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Cycle Time

CYC

7.2

8.5

Clock Access Time

4.0

4.2

4.5

Output Enable to Data Valid

4.0

4.2

4.5

Clock High to Output Low-Z

LZC

Output Hold from Clock High

1.5

Output Enable Low to Output Low-Z

LZOE

Output Enable High to Output High-Z

HZOE

3.5

4.0

Clock High to Output High-Z

HZC

1.5

3.5

1.5

3.5

1.5

4.0

Clock High Pulse Width

2.5

3.0

Clock Low Pulse Width

2.5

3.0

Address Setup to Clock High

2.0

Address Status Setup to Clock High

2.0

Data Setup to Clock High

2.0

Write Setup to Clock High (GW, BW, WE

)

2.0

Address Advance Setup to Clock High

ADVS

2.0

Chip Select Setup to Clock High

CSS

2.0

Address Hold from Clock High

0.5

Address Status Hold from Clock High

0.5

Data Hold from Clock High

0.5

Write Hold from Clock High (GW, BW, WE

)

0.5

Address Advance Hold from Clock High

ADVH

0.5

Chip Select Hold from Clock High

CSH

0.5

ZZ High to Power Down

PDS

cycle

ZZ Low to Power Up

PUS

cycle

Output Load(B),
(for t

LZC

, t

LZOE

, t

HZOE

& t

HZC

)

Dout

353

1538

5pF*

+3.3V for 3.3V I/O

319

1667

Fig. 1

* Including Scope and Jig Capacitance

Output Load(A)

Dout

Zo=50

RL=50

VL=1.5V for 3.3V I/O
V

DDQ

/2 for 2.5V I/O

/+2.5V for 2.5V I/O

30pF*

K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 10 -

Rev 3.0

May 1999

K7A803601M

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K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 15 -

Rev 3.0

May 1999

K7A803601M

APPLICATION INFORMATION

The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.

DEPTH EXPANSION

This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.

Data

Address

CLK

ADS

CLK

ADSC

WEx

Address Data

ADV

ADSP

256Kx36
SPB
SRAM

(Bank 0)

CLK

ADSC

WEx

Address Data

ADV

ADSP

256Kx36
SPB
SRAM

(Bank 1)

CLK

Address

Cache
Controller

[0:18]

[18]

[0:17]

[18]

[0:17]

I/O

[0:71]

Microprocessor

Clock

ADSP

ADDRESS

Data Out

WRITE

n+1*

ADV

(Bank 0)

(Bank 1)

[0:n*]

INTERLEAVE READ TIMING

(Refer to non-interleave write timing for interleave write timing)

Bank 0 is selected by CS

, and Bank 1 deselected by CS

Q1-1

Q1-2

Q1-4

Q1-3

Q2-2

Q2-4

Q2-3

ADVS

ADVH

LZOE

HZC

Bank 0 is deselected by CS

, and Bank 1 selected by CS

CSS

CSH

LZC

Q2-1

Don

t Care

Undefined

(ADSP CONTROLLED , ADSC=HIGH)

*Notes : n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth

K7A801801M

256Kx36 & 512Kx18 Synchronous SRAM

- 16 -

Rev 3.0

May 1999

K7A803601M

APPLICATION INFORMATION

DEPTH EXPANSION

Data

Address

CLK

ADS

Microprocessor

CLK

ADSC

WEx

Address Data

ADV

ADSP

512Kx18
SPB
SRAM

(Bank 0)

CLK

ADSC

WEx

Address Data

ADV

ADSP

512Kx18
SPB
SRAM

(Bank 1)

CLK

Address

Cache
Controller

[0:19]

[19]

[0:18]

[19]

[0:18]

I/O

[0:71]

The Samsung 512Kx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.

Clock

ADSP

ADDRESS

Data Out

WRITE

n+1*

ADV

(Bank 0)

(Bank 1)

[0:n*]

INTERLEAVE READ TIMING

(Refer to non-interleave write timing for interleave write timing)

Bank 0 is selected by CS

, and Bank 1 deselected by CS

Q1-1

Q1-2

Q1-4

Q1-3

Q2-2

Q2-4

Q2-3

ADVS

ADVH

LZOE

HZC

Bank 0 is deselected by CS

, and Bank 1 selected by CS

CSS

CSH

LZC

Q2-1

Don

t Care

Undefined

(ADSP CONTROLLED , ADSC=HIGH)

*Notes : n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth

Электронный компонент: K7A803601M