K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

PIN DESCRIPTION

Pin Name

Pin Description

Pin Name

Pin Description

K, K

Differential Clocks

Asynchronous Output Enable

Synchronous Address Input

TCK

JTAG Test Clock

, SA

Synchronous Burst Address Input

TMS

JTAG Test Mode Select

Synchronous Data I/O

TDI

JTAG Test Data Input

Core Power Supply

TDO

JTAG Test Data Output

DDQ

Output Power Supply

Output Driver Impedance Control Input

REF

HSTL Input Reference Voltage

LBO

Linear Burst Order

Load External Address

MODE

No Connect (Reserved)

Burst R/W Enable

GND

Single/Double Data Selection

No Connection

KQ, KQ

Differential Output Echo Clocks

FEATURES

FUNCTIONAL BLOCK DIAGRAM

· 128Kx36 or 256Kx18 Organizations.
· 2.5V Core/1.5V Output Power Supply.
· HSTL Input and HSTL Outputs.
· Single Differential HSTL Clock.
· Synchronous Pipeline Mode of Operation with Self-Timed
Late Write.
· Free Running Active High and Active Low Echo Clock Output
Pin.
· Asynchronous Output Enable.
· Registered Addresses, Burst Control Inputs and Data Inputs.
· Registered Outputs.
· Single and Double Data Rate Burst Read and Write.
· 4 Count Burst Operation
· JTAG 1149.1 Compatible Test Access port.
· 153(9x17) Pin Ball Grid Array Package(14mm x 22mm).

· Programmable Impedance Output Drivers.

Organization

Part Number

Cycle

Time

Access

Time

128Kx36

K7D403671M-H25

2.4

K7D403671M-H22

2.4

K7D403671M-H20

2.7

K7D403671M-H16

3.3

256Kx18

K7D401871M-H25

2.4

K7D401871M-H22

2.4

K7D401871M-H20

2.7

K7D401871M-H16

3.3

K,K

Memory Array

128Kx36

Data Out

Data In

Advance
Control

SD/DD

Synchronous

Internal
Clock
Generator

R/W

Data Output Strobe

Data Output Enable

State Machine

Strobe_out

S/A Array

2 : 1 MUX

Data In

Write Buffer

W/D
Array

Echo Clock

Output

36(or 18)x2

XDIN

KQ,KQ

DATA

36(or 18)

Select

R/W control

Output
Buffer

Write

Burst
Counter

Address

Comparator

2:1

MUX

Dec.

17(or 18)

15(or 16)

17(or 18)

(Burst Write

SA[0:16]( or SA[0:17])

(256Kx18)

(2 stage)

(Burst Address)

Address)

Clock
Buffer

K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

PACKAGE PIN CONFIGURATIONS

(TOP VIEW)

K7D403671(128Kx36)

DDQ

N.C

DDQ

REF

DDQ

LBO

MODE

DDQ

REF

DDQ

TMS

TDI

TCK

TDO

DDQ

K7D401871(256Kx18)

DDQ

REF

DDQ

LBO

MODE

DDQ

REF

DDQ

TMS

TDI

TCK

TDO

DDQ

K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

FUNCTION DESCRIPTION

Read Operation(Single and Double)

During single read operation, the address is registered during the first clock edge, the internal array is read between this first edge
and second edge, it is read again in the following cycle from the address increased by burst counter, and data is captured in the out-
put register driven to the CPU during the second clock high edge and third clock high edge. During double read operation, the
address is registered during the first clock edge, the internal array is read twice as much as wider than external bits, transfered to
dout buffer sequentially by burst order and the following cycle the same operation occur from address increased by burst counter,
and data is captured in the output register driven to the CPU at active high clock edge and active low clock edge.
During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.

Write(Store) Operation

All addresses and R/W are sampled with B

and B

on the clock rising edge. B

and B

are low on the rising clock. Write address is

sampled on the rising clock, one cycle after write address and Din have been sampled by the SRAM during 2 consecutive cycles at
each active high and low clock edge and stored to write buffer for next real writing array. Actual write is done by using write data
buffer on the SRAM that capture the write addresses on one address write cycles, and write the array on the next address write
cycles. The "next address write cycles" can actually be many cycles away, broken by a series of read cycles. The SRAM is able to
write 72 bits per cycle with 2-prefetched write buffer. This alleviates timing penalty of read after write cycle.

Echo clock operation

To assure the output tracibility, the SRAM provides the output Echo clock, pair of complement clock, which is synchronized with inter-
nal data output.
During read and write cycle, the Echo clock is triggered by internal output clock signal, and transfered to external through same struc-
tures as output driver in read cycle.

Bypass Read Operation

Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to
be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address
is the same as the contents of the stored write address latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array.

PROGRAMMABLE IMPEDANCE OUTPUT BUFFER OPERATION

The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V

through a precision resistor(RQ).

The value of RQ is five times the output impedance desired. For example, 250

resistor will give an output impedance of 50

. The

allowable range of RQ is between 175

and 350

. Impedance updates occur early in cycles that do not activate the outputs, such

as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance updates are transparent to the user
and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Periodic readjustment is necessary as the
impedance is greatly affected by drifts in supply voltage and temperature. Impedance updates occur no more often than every 32
clock cycles. Clock cycles are counted whether the SRAM is selected or not and proceed regardless of the type of cycle being exe-
cuted. Therefore, the user can be assured that after 33 continuous read cycles have occurred, an impedance update will occur the
next time G are high at a rising edge of the K clock. There are no power up requirements for the SRAM. However, to guarantee opti-
mum output driver impedance after power up, the SRAM needs 1024 non-read cycles.

The K7D403671M and K7D401871M are 4,718,592 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
131,072 words by 36 bits for K7D403671M and 262,144 words by 18 bits for K7D401871M, fabricated using Samsung's advanced
CMOS technology.
Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the
rising edge of K clock, all addresses and burst control inputs are registered internally. And data inputs are registered at rising edges
of K clock for a single data controlled mode, or at rising and falling edges of K clock for a dual data controlled mode, in the following
cycle after write addresses are asserted.
An internal write data buffer allows write data to be stored before loaded into memory core in the next write cycles. Data outputs are
updated from output registers on the rising edges of K clock for a single data controlled mode, or on the rising and falling edges of
the K clock for a dual data controlled mode. Read data is referenced to Echo clock outputs. The chip is operated with a single +2.5V
power supply and is compatible with HSTL input and HSTL output. The package is 9x17(153) Ball Grid Array balls on a 1.27mm
pitch.

K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

4 Burst Operation for Interleaved Burst (LBO = High)

Interleaved Burst

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0
0
1
1

0
1
0
1

0
0
1
1

1
0
1
0

1
1
0
0

0
1
0
1

1
1
0
0

1
0
1
0

4 Burst Operation for Linear Burst (LBO = Low)

Interleaved Burst

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0
0
1
1

0
1
0
1

0
1
1
0

1
0
1
0

1
1
0
0

0
1
0
1

1
0
0
1

1
0
1
0

TRUTH TABLE

NOTE : B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".

Operation

Hi-Z

Clock Stop

Hi-Z

No Operation, Pipeline High-Z

DOUT

Load Address, Single Read

DOUT

Load Address, Double Read

DIN

Load Address, Single Write

DIN

Load Address, Double Write

Increment Address, Continue

BURST SEQUENCE TABLE

K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

RECOMMENDED DC OPERATING CONDITIONS

NOTE :1. These are DC test criteria. DC design criteria is V

REF

50mV. The AC V

levels are defined separately for measuring

timing parameters.
2. V

(Max)DC=

+0.3, V

(Max)AC=

+1.5V(pulse width

5ns).

3. V

(Min)DC=

0.3V, V

(Min)AC=-1.5V(pulse width

5ns).

4. Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and
mounting site thermal impedance. T

+ P

x T

HETA

_JA

Parameter

Symbol

Min

Typ

Max

Unit

Note

Core Power Supply Voltage

2.4

2.5

2.6

Output Power Supply Voltage

DDQ

1.4

1.5

1.6

Input High Level Voltage

REF

+0.1

+ 0.3

1, 2

Input Low Level Voltage

-0.3

REF

-0.1

1, 3

Input Reference Voltage

REF

0.6

0.75

1.0

Operating Junction Temperature

110

ABSOLUTE MAXIMUM RATINGS

NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.

Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter

Symbol

Value

Unit

Core Supply Voltage Relative to V

-0.5 to 3.5

Output Supply Voltage Relative to V

DDQ

-0.5 to V

+0.5

Voltage on any pin Relative to V

-0.5 to V

+0.5

Maximum Power Dissipation

Output Short-Circuit Current(per I/O)

OUT

Storage Temperature

STR

-55 to 125

DC CHARACTERISTICS

NOTE :1. Minimum cycle. I

OUT

=0mA.

2. 50% read cycles.
3. |I

|=(V

DDQ

/2)/(RQ/5)

10% @V

DDQ

/2 for 175

350

4. |I

|=(V

DDQ

/2)/(RQ/5)

10% @V

DDQ

/2 for 175

350

5. Minimum Impedance Mode when ZQ pin is connected to V

Parameter

Symbol

Min

Max

Unit

Note

Average Power Supply Operating Current(x36)
(Cycle time = t

KHKH

min)

DD4

DD44

DD5

DD6

700
650
600
550

1,2

Average Power Supply Operating Current(x18)
(Cycle time = t

KHKH

min)

DD4

DD44

DD5

DD6

650
600
550
500

1,2

Stop Clock Standby Current
(V

-0.2V or 0.2V fixed, Clock=Low)

SB1

Input Leakage Current
(V

or V

)

-1

Output Leakage Current
(V

OUT

or V

DDQ except KQx,KQx

)

-1

Output High Voltage(Programmable Impedance Mode)

OH1

DDQ

Output Low Voltage(Programmable Impedance Mode)

OL1

DDQ

Output High Voltage(I

=-0.1mA )

OH3

DDQ

-0.2

DDQ

Output Low Voltage(I

=0.1mA)

OL3

0.2

K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

Output Load(A)

Output Load(B)

(for t

KQLZ

, t

KQHZ

, t

GLQZ

& t

GHQZ

)

Z0=50

0.75V

*Capacitive load consists of all components

AC TEST CONDITIONS

=20 to 110

C, V

=2.4 -2.6V, V

DDQ

=1.4 - 1.6V)

Parameter

Symbol

Value

Unit

Note

Input High/Low Level

1.25/0.25

Input Reference Level

REF

0.75

Input Rise/Fall Time

1.0/1.0

Output Timing Reference Level

0.75

Clock Input Timing Reference Level

Cross Point

Output Load

See Below

AC TEST OUTPUT LOAD

REF

Dout

DEVICE
UNDER
TEST

250

5pF*

REF

Dout

DEVICE
UNDER
TEST

250

0.75V

of the tester environment

AC CHARACTERISTICS

NOTE : 1. See AC Test Output Load figure
2. Design target is 0ns

Parameter

Symbol

-25

-22

-20

-16

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

Clock Cycle Time

KHKH

4.0

4.4

5.0

6.0

Clock High Pulse Width

KHKL

1.6

1.8

2.0

2.4

Clock Low Pulse Width

KLKH

1.6

1.8

2.0

2.4

Clock to Echo Clock(KQ, KQ)

KHKE

2.2

2.5

3.0

Echo Clock to Output Valid

KEQV

0.2

0.3

1,2

Echo Clock to Output Hold

KEQX

-0.5

-0.6

Echo Clock to Output Low-Z

KQLZ

-0.5

-0.6

Echo Clock to Output High-Z

KQHZ

0.2

G Low to Output Low-Z

GLQX

0.5

G High to Output High-Z

GHQZ

2.2

2.7

3.3

G Low to Output Valid

GLQV

2.2

2.7

3.3

G High to Output Hold

GHQX

0.5

Address Setup Time

AVKH

0.5

0.7

Address Hold Time

KHAX

0.5

0.7

Burst Control Setup Time

BVKH

0.5

0.7

Burst Control Hold Time

KHBX

0.5

0.7

Data Setup Time

DVKH

0.5

0.7

Data Hold Time

KHDX

0.5

0.7

PIN CAPACITANCE

*NOTE : Periodically Sampled and not 100% tested. (dV=0V, f=1MHz)

Parameter

Symbol

Typ.

Max

Unit

Input Pin Capacitance

I/O Pin Capacitance

I/O

Clock Pin Capacitance

CLK

0.75V

K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES

(Burst Length=4)

NOTE
1. Q

refers to output from address A

. Q

refers to output from the next internal burst address following A

, etc.

2. Outputs are disabled(High-Z) one clock cycle after NOP detected.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
4. The second NOP cycle is not necessary for correct device operation.
However, at high clock frequencies it may be required to prevent bus contention.

NOP

CONTINUE

KHKL

AVKH

KHAX

NOP

READ

(burst of 2)

READ

(burst of 2)

READ

(burst of 2)

NOP

WRITE

CONTINUE

WRITE

(burst of 2)

READ

CONTINUE

READ

(burst of 2)

READ
(burst of 2)

CONTINUE

READ

(burst of 2)

BVKH

KHBX

KQHZ

KHKE

KQLZ

CEQV

KEQX

GHQZ

DVKH

KHDX

GLQX

GLQV

KLKH

KHKH

GHQX

UNDEFINED

DON

T CARE

K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES

(Burst Length=4)

NOTE :
1. Q

refers to output from address A

. Q

refers to output from the next internal burst address following A

, etc.

2. Outputs are disabled(High-Z) one clock cycle after NOP detected
3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation.
4. This device will have an address to wrap around if further Continues are applied.
5. The second NOP cycle is not necessary for correct device operation.
however, at high clock frequencies it may be required to prevent bus contention.

NOP

CONTINUE

KHKH

AVKH

KHAX

NOP

READ

(burst of 2)

READ

(burst of 2)

READ

(burst of 2)

NOP

WRITE

CONTINUE

WRITE

(burst of 2)

READ

CONTINUE

READ

(burst of 2)

CONTINUE

READ

(burst of 2)

CONTINUE

READ

(burst of 2)

BVKH

KHBX

KQHZ

KHKE

KQLZ

KEQV

KEQX

GHQZ

GHQX

DVKH

KHDX

GLQX

GLQV

KLKH

UNDEFINED

DON

T CARE

KHKL

K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Teat Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction
Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM. TCK must be tied to V

to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to V

through a resistor. TDO should be left unconnected.

TAP Controller State Diagram

Test Logic Reset

Run Test Idle

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

JTAG Block Diagram

SRAM
CORE

BYPASS Reg.

Identification Reg.

Instruction Reg.

Control Signals

TAP Controller

TDO

SA(5R)

SA(4R)

TDI

TMS
TCK

JTAG Instruction Coding

NOTE :
1. Places DQs,KQx,KQx in Hi-Z in order to sample all input data regard-

less of other SRAM inputs.

2. TDI is sampled as an input to the first ID register to allow for the serial

shift of the external TDI data.

3. Bypass register is initiated to V

when BYPASS instruction is

invoked. The Bypass Register also holds serially loaded TDI when
exiting the Shift DR states.

4. SAMPLE instruction dose not places DQs,KQx,KQx in Hi-Z.

IR2 IR1 IR0

Instruction

TDO Output

Note

SAMPLE-Z

Boundary Scan Register

IDCODE

Identification Register

SAMPLE-Z

Boundary Scan Register

BYPASS

Bypass Register

SAMPLE

Boundary Scan Register

BYPASS

Bypass Register

BYPASS

Bypass Register

BYPASS

Bypass Register

K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

ID REGISTER DEFINITION

Part

Revision Number

(31:28)

Part Configuration

(27:18)

Vendor Definition

(17:12)

Samsung JEDEC Code

(11: 1)

Start Bit

(0)

128Kx36

0000

00101 00100

XXXXXX

00001001110

256Kx18

0000

00110 00011

XXXXXX

00001001110

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

ID Register

Boundary Scan

128Kx36

3 bits

1 bits

32 bits

68 bits

256Kx18

3 bits

1 bits

32 bits

49 bits

BOUNDARY SCAN EXIT ORDER(x36)

MODE

LBO

BOUNDARY SCAN EXIT ORDER(x18)

MODE

LBO

NOTE :
1. Pins 7D/3D are no connection pins to internal chip and place holders for 8M/16M parts. The scanned data are fixed to "1" for this 4M part.
2. Mode pin 6L is no connection pin to internal chip. The scanned data is fixed to "1".

K7D401871M

128Kx36 & 256Kx18 SRAM

K7D403671M

Rev 1.0

Nov. 1999

JTAG DC OPERATING CONDITIONS

NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

2.4

2.5

2.6

Input High Level

1.7

+0.3

Input Low Level

-0.3

0.7

Output High Voltage(I

=-2mA)

2.0

Output Low Voltage(I

=2mA)

0.4

JTAG TIMING DIAGRAM

JTAG AC TEST CONDITIONS

NOTE : 1. See SRAM AC test output load on page 7.

Parameter

Symbol

Min

Unit

Note

Input High/Low Level

2.5/0.0

Input Rise/Fall Time

TR/TF

1.0/1.0

Input and Output Timing Reference Level

1.25

JTAG AC Characteristics

Parameter

Symbol

Min

Max

Unit

Note

TCK Cycle Time

CHCH

TCK High Pulse Width

CHCL

TCK Low Pulse Width

CLCH

TMS Input Setup Time

MVCH

TMS Input Hold Time

CHMX

TDI Input Setup Time

DVCH

TDI Input Hold Time

CHDX

SRAM Input Setup Time

SVCH

SRAM Input Hold Time

CHSX

Clock Low to Output Valid

CLQV

TCK

TMS

TDI

CHCH

MVCH

CHMX

CHCL

CLCH

DVCH

CHDX

CLQV

TDO

SVCH

CHSX

(SRAM)

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