Rev 4.0

256Kx36 & 512Kx18 SRAM

- 1 -

January. 2002

K7D801871B

K7D803671B

Document Title

8M DDR SYNCHRONOUS SRAM

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.

Rev No.

Rev. 0.0

Rev. 0.1

Rev. 0.2

Rev. 0.3

Rev. 0.5

Rev. 0.6

Rev. 0.7

Rev. 1.0

Rev. 2.0

Rev. 3.0

Rev. 4.0

Remark

Advance

Advance

Prelimary

Final

History

-Initial document.

-ZQ tolerance changed from 10% to 15%

-Stop Clock Standby Current condition changed from
V

-0.2V or 0.2V fixed to V

or V

-V

DDQ

Max. changed to 2.0V

SA0, SA1 defined for Boundary Scan Order

-Deleted -HC16 part(Part Number, Idd, AC Characterisctics)

- Absolute Maximum ratings V

DDQ

changed from 3.13V to 2.825V

- LBO input level changed from High/Low to V

DDQ

- Stop Clock Standby Current condition changed
from K=Low, K=High to K=Low, K=Low
- t

CHQV/

CLQV

changed from 0.1ns to 0.2ns for -33 part

from 0.1ns to 0.2ns for -30 part
from 0.1ns to 0.25ns for -25part
- t

CHQX/

CLQX

changed from -0.3ns to -0.2ns for -33 part

from -0.3ns to -0.2ns for -30 part
from -0.4ns to -0.25ns for -25part

CHQZ/

CLQZ

changed from 0.1ns to 0.2ns for -33 part

from 0.1ns to 0.2ns for -30 part
from 0.1ns to 0.25ns for -25part

KXCH

changed from 1.8ns to 1.7ns for -33 part

KXCL

changed from 1.8ns to 1.7ns for -33 part

- Clarification on the features and the timing waveforms regarding the
burst controllability.
- Recommended DC operating conditions for Clock added.
- AC test conditions for V

DDQ

=1.8V and Single ended clock added.

(AC Test Conditions 2)
- Package thermal characteristics added.

- Add-HC35 part(Part Number, Idd, AC Characteristics)

- Absolute Maximum Rating VDDQ changed from 2.825V to 2.4V
- V

CM-CLK

Min changed from 0.6V to 0.68V

- Add-HC37 part(Part Number, Idd, AC Characteristics)

Draft Data

July. 2000

Aug. 2000

Oct. 2000

Nov. 2000

Jan. 2001

Feb. 2001

Mar. 2001

May. 2001

Sep. 2001

Jan. 2002

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 2 -

January. 2002

K7D801871B

K7D803671B

PIN DESCRIPTION

Pin Name

Pin Description

Pin Name

Pin Description

K, K

Differential Clocks

Output Driver Impedance Control Input

Synchronous Address Input

TCK

JTAG Test Clock

, SA

Synchronous Burst Address Input (SA

= LSB)

TMS

JTAG Test Mode Select

Synchronous Data I/O

TDI

JTAG Test Data Input

CQ, CQ

Differential Output Echo Clocks

TDO

JTAG Test Data Output

Load External Address

REF

HSTL Input Reference Voltage

Burst R/W Enable

Power Supply

Single/Double Data Selection

DDQ

Output Power Supply

Asynchronous Output Enable

GND

LBO

Linear Burst Order

No Connection

FEATURES

� 256Kx36 or 512Kx18 Organizations.
� Maximum Frequency : 370MHz (Data Rate : 740Mbps)
� 2.5V V

/1.5V V

DDQ

(2.0V max V

DDQ

� HSTL Input and Outputs.
� Single Differential HSTL Clock.
� Synchronous Pipeline Mode of Operation with Self-Timed Late Write.
� Free Running Active High and Active Low Echo Clock Output Pin.
� Asynchronous Output Enable.
� Registered Addresses, Burst Control and Data Inputs.
� Registered Outputs.
� Single and Double Data Rate Burst Read and Write.
� Burst Count Controllable With Max Burst Length of 4
� Interleved and Linear Burst mode support
� Bypass Operation Support
� Programmable Impedance Output Drivers.
� JTAG Boundary Scan (subset of IEEE std. 1149.1)
� 153(9x17) Pin Ball Grid Array Package(14mm x 22mm).

FUNCTIONAL BLOCK DIAGRAM

K,K

Memory Array

256Kx36

Data Out

Data In

Advance
Control

SD/DD

Clock

Synchronous

Buffer

Internal
Clock

Generator

R/W

Data Output Strobe
Data Output Enable
State Machine

Strobe_out

S/A Array

2 : 1 MUX

Data In

Write Buffer

W/D

Array

Echo Clock

Output

36(or 18)x2

36(or18)x2

XDIN

CQ,CQ

36(or 18)

Select

R/W control

Output

Buffer

Write

Burst

Counter

Address

Comparator

2:1

MUX

Dec.

18(or 19)

16(or 17)

18(or 19)

(Burst Write

SA[0:17]( or SA[0:18])

(512Kx18)

(2 stage)

(Burst Address)

Address)

NOTE : *Access time equals

KXCH/

KXCL

Organization

Part Number

Maximum

Frequency

Access

Time

256Kx36

K7D803671B-HC37

370MHz

1.7*

K7D803671B-HC35

357MHz

1.7*

K7D803671B-HC33

333MHz

1.7*

K7D803671B-HC30

300MHz

1.9*

K7D803671B-HC25

250MHz

2.0*

512Kx18

K7D801871B-HC37

370MHz

1.7*

K7D801871B-HC35

357MHz

1.7*

K7D801871B-HC33

333MHz

1.7*

K7D801871B-HC30

300MHz

1.9*

K7D801871B-HC25

250MHz

2.0*

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 3 -

January. 2002

K7D801871B

K7D803671B

PACKAGE PIN CONFIGURATIONS

(TOP VIEW)

K7D803671B(256Kx36)

* Mode Pin(6L) is a internally NC.

DDQ

REF

DDQ

LBO

MODE

DDQ

REF

DDQ

TMS

TDI

TCK

TDO

DDQ

K7D801871B(512Kx18)

* Mode Pin(6L)is a internally NC.

DDQ

REF

DDQ

LBO

MODE

DDQ

REF

DDQ

TMS

TDI

TCK

TDO

DDQ

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 4 -

January. 2002

K7D801871B

K7D803671B

FUNCTION DESCRIPTION

The K7D803671B and K7D801871B are 9,437,184 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
262,144 words by 36 bits for K7D803671B and 524,288 words by 18 bits for K7D801871B, fabricated using Samsung's advanced
CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At
the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after
write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and
falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations, and off the rising and falling
edges of K clock for DDR read operations. Free running echo clocks are supported which are representive of data output access
time for all SDR and DDR operations.
The chip is operated with a single +2.5V power supply and is compatible with Extended HSTL input and output. The package is
9x17(153) Ball Grid Array balls on a 1.27mm pitch.

Read Operation(Single and Double)

During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is
read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of
K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal
array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by
burst order off the second rising and falling edge of K clock.
Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.
To avoid data contention,at least one NOP operations are required between the last read and the first write operation.

Write Operation(Late Write)

During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered
at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of
K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are
stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM
array.

Echo clock operation

Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation
only when K clock is in the stop mode.
Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture
data outputs outputs.

Bypass Read Operation

Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array.

Programmable Impedance Output Driver

The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and V

, and

are equal to RQ/5. For example, 250

resistor will give an output impedance of 50

. Output driver impedance tolerance is 15% by

test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates
occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In
all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior
in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is
selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 contin-
uous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are
no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs
1024 non-read cycles.

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 5 -

January. 2002

K7D801871B

K7D803671B

4 Burst Operation for Interleaved Burst (LBO = V

DDQ

)

NOTE : - For Interleave Burst LBO = V

DDQ

is recommended. If LBO = V

, it must not exceed 2.63V.

Interleaved Burst

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0
0
1
1

0
1
0
1

0
0
1
1

1
0
1
0

1
1
0
0

0
1
0
1

1
1
0
0

1
0
1
0

TRUTH TABLE

NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".
- K & K are complementary.

Operation

Hi-Z

Clock Stop

Hi-Z

No Operation, Pipeline High-Z

DOUT

Load Address, Single Read

DOUT

Load Address, Double Read

DIN

Load Address, Single Write

DIN

Load Address, Double Write

Increment Address, Continue

BURST SEQUENCE TABLE

4 Burst Operation for Linear Burst (LBO = V

)

Linear Burst Mode

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0
0
1
1

0
1
0
1

0
1
1
0

1
0
1
0

1
1
0
0

0
1
0
1

1
0
0
1

1
0
1
0

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 7 -

January. 2002

K7D801871B

K7D803671B

RECOMMENDED DC OPERATING CONDITIONS

NOTE : 1. These are DC test criteria. DC design criteria is V

REF

�

50mV. The AC V

levels are defined separately for measuring

timing parameters.
2. V

(Max)DC=

DDQ

+0.3, V

(Max)AC=

2.6

V (2.1V for DQs) (pulse width

20% of cycle time).

3. V

(Min)DC=

0.3V, V

(Min)AC=-1.0V (-0.5V for DQs) (pulse width

20% of cycle time).

4. V

IN-CLK

specifies the maximum allowable DC level for the differential clock. i.e V

IL-CLK

and V

IH-CLK

5. V

DIF-CLK

specifies the minimum Clock differential voltage required for switching. i.e DC voltage difference between V

IL-CLK

and V

IH-CLK

6. V

CM-CLK

specifies the Clock crossing point for the differential clock or the allowable common clock level for a single ended clock.

Parameter

Symbol

Min

Typ

Max

Unit

Note

Core Power Supply Voltage

2.37

2.5

2.63

Output Power Supply Voltage

DDQ

1.4

1.5

2.0

Input High Level Voltage

REF

+0.1

DDQ

+0.3

1, 2

Input Low Level Voltage

-0.3

REF

-0.1

1, 3

Input Reference Voltage

REF

0.68

0.75

1.0

Clock Input Signal Voltage

IN-CLK

-0.3

DDQ

+0.3

1, 4

Clock Input Differential Voltage

DIF-CLK

0.1

DDQ

+0.6

1, 5

Clock Input Common Mode Voltage

CM-CLK

0.68

0.75

0.9

1, 6

ABSOLUTE MAXIMUM RATINGS

NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.

Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter

Symbol

Value

Unit

Core Supply Voltage Relative to V

-0.5 to 3.13

Output Supply Voltage Relative to V

DDQ

-0.5 to 2.4

Voltage on any pin Relative to V

-0.5 to V

DDQ

+0.5 (2.4V

MAX

)

Output Short-Circuit Current(per I/O)

OUT

Storage Temperature

STR

-55 to 125

�

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 8 -

January. 2002

K7D801871B

K7D803671B

PIN CAPACITANCE

NOTE : Periodically sampled and not 100% tested.(T

=25

�

C, f=1MHz)

Parameter

Symbol

Test Condition

Min

Max

Unit

Input Capacitance

=0V

Data Output Capacitance

OUT

=0V

DC CHARACTERISTICS

NOTE :1. Minimum cycle. I

OUT

=0mA.

2. 50% read cycles.
3. |I

|=(V

DDQ

/2)/(RQ/5)

�

15% @V

DDQ

/2 for 175

350

4. |I

|=(V

DDQ

/2)/(RQ/5)

�

15% @V

DDQ

/2 for 175

350

5. Minimum Impedance Mode when ZQ pin is connected to V

Parameter

Symbol

Min

Max

Unit

Note

Average Power Supply Operating Current(x36)
(Cycle time = t

KHKH

min)

DD37

DD35

DD33

DD30

DD25

880
850
750
670
600

1,2

Average Power Supply Operating Current(x18)
(Cycle time = t

KHKH

min)

DD37

DD35

DD33

DD30

DD25

830
800
700
620
550

1,2

Stop Clock Standby Current
(V

or V

, K=Low, K=Low)

SB1

150

Input Leakage Current
(V

or V

DDQ

)

-1

�

Output Leakage Current
(V

OUT

or V

DDQ

)

-1

�

Output High Voltage(Programmable Impedance Mode)

OH1

DDQ

Output Low Voltage(Programmable Impedance Mode)

OL1

DDQ

Output High Voltage(I

=-0.1mA)

OH2

DDQ

-0.2

DDQ

Output Low Voltage(I

=0.1mA)

OL2

0.2

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 9 -

January. 2002

K7D801871B

K7D803671B

AC TEST CONDITIONS 2

=0 to 70

�

C, V

=2.37 -2.63V, V

DDQ

=1.8V)

Parameter

Symbol

Value

Unit

Note

Input High/Low Level

1.64/0.18

Input Reference Level

REF

0.9

Input Rise/Fall Time

0.5/0.5

Output Timing Reference Level

0.9

Clock Input Timing Reference Level

Cross Point

Output Load

See Below

AC TEST OUTPUT LOAD 2

5pF

0.9V

5pF

0.9V

AC TEST CONDITIONS 1

=0 to 70

�

C, V

=2.37 -2.63V, V

DDQ

=1.5V)

Parameter

Symbol

Value

Unit

Note

Input High/Low Level

1.25/0.25

Input Reference Level

REF

0.75

Input Rise/Fall Time

0.5/0.5

Output Timing Reference Level

0.75

Clock Input Timing Reference Level

Cross Point

Output Load

See Below

AC TEST OUTPUT LOAD 1

5pF

0.75V

5pF

0.75V

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 10

January. 2002

K7D801871B

K7D803671B

AC CHARACTERISTICS

(For both AC test condition 1 and 2)

NOTE : 1. See AC Test Output Load figure
2. Design target is 0ns

Parameter

Symbol

-33

-30

-25

Unit

Note

Min

Max

Min

Max

Min

Max

Clock Cycle Time

KHKH

3.0

3.3

4.0

Clock High Pulse Width

KHKL

1.3

1.5

1.7

Clock Low Pulse Width

KLKH

1.3

1.5

1.7

CQ High Pulse Width

CHCL

KHKL

-0.1

KHKL

+0.1

KHKL

-0.2

KHKL

+0.2

KHKL

-0.3

KHKL

+0.3

CQ Low Pulse Width

CLCH

KLKH

-0.1

KLKH

+0.1

KLKH

-0.2

KLKH

+0.2

KLKH

-0.3

KLKH

+0.3

Clock to Echo Clock(CQ) High

KXCH

0.5

1.7

0.5

1.9

0.5

2.0

Clock to Echo Clock(CQ) Low

KXCL

0.5

1.7

0.5

1.9

0.5

2.0

Echo Clock to Output Valid

CHQV/

CLQV

0.2

0.25

1,2

Echo Clock to Output Hold

CHQX/

CLQX

-0.2

-0.25

Echo Clock to Output High-Z

CHQZ/

CLQZ

0.2

0.25

G Low to Output Low-Z

GLQX

0.5

G High to Output High-Z

GHQZ

2.1

2.3

2.5

G Low to Output Valid

GLQV

2.1

2.3

2.5

Address Setup Time

AVKH

0.4

0.5

Address Hold Time

KHAX

0.4

0.5

Burst Control Setup Time

BVKH

0.4

0.5

Burst Control Hold Time

KHBX

0.4

0.5

Data Setup Time

DVKH

0.4

0.5

Data Hold Time

KHDX

0.4

0.5

AC CHARACTERISTICS

(For AC test condition 1)

NOTE : 1. See AC Test Output Load figure
2. Design target is 0ns

Parameter

Symbol

-37

-35

Unit

Note

Min

Max

Min

Max

Clock Cycle Time

KHKH

2.7

2.8

Clock High Pulse Width

KHKL

1.3

Clock Low Pulse Width

KLKH

1.3

CQ High Pulse Width

CHCL

KHKL

-0.1

KHKL

+0.1

KHKL

-0.1

KHKL

+0.1

CQ Low Pulse Width

CLCH

KLKH

-0.1

KLKH

+0.1

KLKH

-0.1

KLKH

+0.1

Clock to Echo Clock(CQ) High

KXCH

0.5

1.7

0.5

1.7

Clock to Echo Clock(CQ) Low

KXCL

0.5

1.7

0.5

1.7

Echo Clock to Output Valid

CHQV/

CLQV

0.2

1,2

Echo Clock to Output Hold

CHQX/

CLQX

-0.2

Echo Clock to Output High-Z

CHQZ/

CLQZ

0.2

G Low to Output Low-Z

GLQX

0.5

G High to Output High-Z

GHQZ

2.1

G Low to Output Valid

GLQV

2.1

Address Setup Time

AVKH

0.4

Address Hold Time

KHAX

0.4

Burst Control Setup Time

BVKH

0.4

Burst Control Hold Time

KHBX

0.4

Data Setup Time

DVKH

0.4

Data Hold Time

KHDX

0.4

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 11

January. 2002

K7D801871B

K7D803671B

NOP

CONTINUE

AVKH

KHAX

NOP

READ

(burst of 4)

READ

(burst of 4)

NOP

WRITE

CONTINUE

WRITE

(burst of 4)

READ

CONTINUE

READ

READ
(burst of 4)

CONTINUE

READ

BVKH

KHBX

CHQZ

KXCH

CHLZ

CHQV

CHQX

GHQZ

DVKH

KHDX

GLQX

GLQV

KHKH

GHQX

UNDEFINED

DON'T CARE

NOTE
1. Q

refers to output from address A. Q

refers to output from the next internal burst address following A, etc.

2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.

(burst of 2)

TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES

(Burst Length=4, 2)

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 12

January. 2002

K7D801871B

K7D803671B

TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES

(Burst Length=4, 2, 1)

NOTE :
1. Q

refers to output from address A

. Q

refers to output from the next internal burst address following A

, etc.

2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further

Continue assertions constitute invalid operations.

4. This device will have an address wraparound if further Continues are applied.

NOP

CONTINUE

KHKH

AVKH

KHAX

NOP

READ

(burst of 2)

READ

(burst of 4)

NOP

WRITE

CONTINUE

WRITE

(burst of 2)

READ

CONTINUE

READ

CONTINUE

READ

CONTINUE

READ

BVKH

KHBX

CHQZ

KXCH

CHLZ

CHQV

CHQX

GHQZ

GHQX

DVKH

KHDX

GLQX

GLQV

KLKH

KHKL

(burst of 1)

UNDEFINED

DON'T CARE

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 13

January. 2002

K7D801871B

K7D803671B

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

TAP Controller State Diagram

JTAG Block Diagram

SRAM
CORE

BYPASS Reg.
Identification Reg.
Instruction Reg.

Control Signals

TAP Controller

TDO

TDI

TMS

TCK

Test Logic Reset

Run Test Idle

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

JTAG Instruction Coding

NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
3. Bypass register is initiated to V

when BYPASS instruction is

invoked.
The Bypass Register also holds serially loaded TDI when exiting
the Shift DR states.
4. SAMPLE instruction dose not places DQs in Hi-Z.

IR2 IR1 IR0 Instruction

TDO Output

Notes

EXTEST

Boundary Scan Register

IDCODE

Identification Register

SAMPLE-Z Boundary Scan Register

BYPASS

Bypass Register

SAMPLE

Boundary Scan Register

BYPASS

Bypass Register

BYPASS

Bypass Register

BYPASS

Bypass Register

The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-
ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-
ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM. TCK must
be tied to V

to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the

application of a logic 1, and may be left unconnected. But they may also be tied to V

through a resistor. TDO should be left uncon-

nected.

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 14

January. 2002

K7D801871B

K7D803671B

ID REGISTER DEFINITION

Part

Revision Number

(31:28)

Part Configuration

(27:18)

Vendor Definition

(17:12)

Samsung JEDEC Code

(11: 1)

Start Bit

(0)

256Kx36

0000

00110 00100

XXXXXX

00001001110

512Kx18

0000

00111 00011

XXXXXX

00001001110

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

ID Register

Boundary Scan

256Kx36

3 bits

1 bits

32 bits

68 bits

512Kx18

3 bits

1 bits

32 bits

49 bits

BOUNDARY SCAN EXIT ORDER(x36)

1.Pin 6L is reserved for Mode Pin and the scanned data is fixed to "0"
2.Pin 3D is reserved for Address bit for 16Mb density and
the scanned data is fixed to "0"

LBO

BOUNDARY SCAN EXIT ORDER(x18)

1.Pin 6L is reserved for Mode Pin and the scanned data is fixed to "0"
2.Pin 3D is reserved for Address bit for 16Mb density and
the scanned data is fixed to "0"

LBO

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 15

January. 2002

K7D801871B

K7D803671B

JTAG DC OPERATING CONDITIONS

NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

2.37

2.5

2.63

Input High Level

1.7

+0.3

Input Low Level

-0.3

0.7

Output High Voltage(I

=-2mA)

2.1

Output Low Voltage(I

=2mA)

0.2

JTAG AC Characteristics

Parameter

Symbol

Min

Max

Unit

Note

TCK Cycle Time

CHCH

TCK High Pulse Width

CHCL

TCK Low Pulse Width

CLCH

TMS Input Setup Time

MVCH

TMS Input Hold Time

CHMX

TDI Input Setup Time

DVCH

TDI Input Hold Time

CHDX

Clock Low to Output Valid

CLQV

JTAG AC TEST CONDITIONS

NOTE : 1. See SRAM AC test output load on page 5.

Parameter

Symbol

Min

Unit

Note

Input High/Low Level

2.5/0.0

Input Rise/Fall Time

TR/TF

1.0/1.0

Input and Output Timing Reference Level

1.25

JTAG TIMING DIAGRAM

TCK

TMS

TDI

TDO

CHCH

CHCL

CLCH

MVCH

CHMX

DVCH

CHDX

CLQV

Rev 4.0

256Kx36 & 512Kx18 SRAM

- 16

January. 2002

K7D801871B

K7D803671B

NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCS Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.

153 BGA PACKAGE DIMENSIONS

1.27

7 6 5 4 3 2 1

0.050

F
G

J
K

L
M

T
U

1
.
2
7

0
.
0
5
0

BOTTOM VIEW

0.3/0.012MAX

153-

0.030

�

0.006

14.00

�

0.10

0.551

�

0.004

2
2
.
0
0

�

.
1
0

.
8
6
6

�

0
.
0

0
4

12.50

�

0.10

0.492

�

0.004

0.60

�

0.10

0.024

�

0.004

2
0
.
5
0

�

.
1
0

.
8
0
7

�

0
.
0

0
4

0.56

�

0.04

0.022

�

0.002

0.90

�

0.10

0.035

�

0.004

2.21

0.087

TOP VIEW

0.006

0.15 MAX

0.75

�

0.15

MAX

9 8

153 BGA PACKAGE THERMAL CHARACTERISTICS

NOTE : 1. Junction temperature can be calculated by : T

= T

+ P

x Theta_JA.

Parameter

Symbol

Thermal Resistance

Unit

Note

Junction to Ambient(at still air)

Theta_JA

30.0

�

C/W

1W Heating

Junction to Case

Theta_JC

5.9

�

C/W

Junction to Board

Theta_JB

4.8

�

C/W

2W Heating

Электронный компонент: K7D803671B-HC33