2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 1 -

Rev 1.0

Aug. 2005

72Mb M-die DDRII SRAM Specification

165 FBGA with Pb & Pb-Free

(RoHS compliant)

* Samsung Electronics reserves the right to change products or specification without notice.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-

lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 2 -

Rev 1.0

Aug. 2005

Document Title

2Mx36-bit, 4Mx18-bit DDRII CIO b2 SRAM

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Revision History

Rev. No.

0.0

0.1

0.2

0.3

0.4

1.0

Remark

Advance

Preliminary

Final

History

1. Initial document.

1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)

1. Add the Power-on Sequence specification

1. Correct the pin name table

1. Update the power consumption (Icc & Isb)

1. Finalize the datasheet

Draft Date

Mar. 9, 2003

Mar. 20, 2003

Aug. 16, 2004

Oct. 18, 2004

May. 17, 2005

Aug. 2, 2005

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 3 -

Rev 1.0

Aug. 2005

2Mx36-bit, 4Mx18-bit DDRII CIO b2 SRAM

FEATURES

FUNCTIONAL BLOCK DIAGRAM

1.8V+0.1V/-0.1V Power Supply.

DLL circuitry for wide output data valid window and future

freguency scaling.

· I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O

· Pipelined, double-data rate operation.
· Common data input/output bus .
· HSTL I/O
· Full data coherency, providing most current data.
· Synchronous pipeline read with self timed late write.
· Registered address, control and data input/output.
· DDR(Double Data Rate) Interface on read and write ports.
· Fixed 2-bit burst for both read and write operation.
· Clock-stop supports to reduce current.
·

Two input clocks(K and K) for accurate DDR timing at clock

rising edges only.

Two input clocks for output data(C and C) to minimize

clock-skew and flight-time mismatches.

Two echo clocks (CQ and CQ) to enhance output data

traceability.

Single address bus.

Byte write function.

· Simple depth expansion with no data contention.
·

Programmable output impedance.

· JTAG 1149.1 compatible test access port.
· 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm

& Lead Free

ADDRESS

R/W

ADD REG

BURST

LOGIC

DATA

REG

CLK

GEN

CTRL

LOGIC

2Mx36

(4Mx18)

MEMORY

ARRAY

WRITE DRIVER

K
K

4(or 2)

SELECT OUTPUT CONTROL

I
T

/
RE

AD DE

CODE

OUT

DRI

Notes: 1. Numbers in ( ) are for x18 device.

20 (or 21)

36 (or 18)

(Echo Clock out)

CQ, CQ

* E : Lead Free Package
* I : Industrial Temperature

Org.

Part

Number

Cycle

Time

Access

Time

Unit

X36

K7I643682M-F(E)C(I)30

3.3

0.45

K7I643682M-F(E)C(I)25

4.0

0.45

K7I643682M-F(E)C(I)20

5.0

0.45

K7I643682M-F(E)C(I)16

6.0

0.50

X18

K7I641882M-F(E)C(I)30

3.3

0.45

K7I641882M-F(E)C(I)25

4.0

0.45

K7I641882M-F(E)C(I)20

5.0

0.45

K7I641882M-F(E)C(I)16

6.0

0.50

36 (or 18)

DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.

(or 21)

(or 18)

(or 36)

36 (or 18)

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 4 -

Rev 1.0

Aug. 2005

PIN CONFIGURATIONS

(TOP VIEW) K7I643682M(2Mx36)

Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 144Mb .
2. BW

controls write to DQ0:DQ8, BW

controls write to DQ9:DQ17, BW

controls write to DQ18:DQ26 and BW

controls write to DQ27:DQ35.

SS/

SA*

R/W

DQ27

DQ18

DQ8

DQ28

SA0

DQ17

DQ7

DQ29

DQ19

DQ16

DQ20

DDQ

DQ15

DQ6

DQ30

DQ21

DDQ

DQ5

DQ31

DQ22

DDQ

DQ14

Doff

REF

DDQ

REF

DQ32

DDQ

DQ13

DQ4

DQ23

DDQ

DQ12

DQ3

DQ33

DQ24

DDQ

DQ2

DQ34

DQ11

DQ1

DQ35

DQ25

DQ10

DQ26

DQ9

DQ0

TDO

TCK

TMS

TDI

PIN NAME

Notes: 1. C, C, K or K cannot be set to V

REF

voltage.

2. When ZQ pin is directly connected to V

output impedance is set to minimum value

and it cannot be connected to ground or left unconnected.

3. Not connected to chip pad internally.

SYMBOL

PIN NUMBERS

DESCRIPTION

NOTE

K, K

6B, 6A

Input Clock

C, C

6P, 6R

Input Clock for Output Data

CQ, CQ

11A, 1A

Output Echo Clock

Doff

DLL Disable when low

SA0

Burst Count Address Inputs

3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

Address Inputs

DQ0-35

2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F

11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L

3M,10M,11M,2N,3N,11N,3P,10P,11P

Data Inputs Outputs

R/W

Read, Write Control Pin, Read active

when high

Synchronous Load Pin, bus Cycle

sequence is to be defined when low

, BW

7B,7A,5A,5B

Block Write Control Pin,active when low

REF

2H,10H

Input Reference Voltage

11H

Output Driver Impedance Control Input

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

Power Supply ( 1.8 V )

DDQ

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output Power Supply ( 1.5V or 1.8V )

2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,

4M-8M,4N,8N

Ground

TMS

10R

JTAG Test Mode Select

TDI

11R

JTAG Test Data Input

TCK

JTAG Test Clock

TDO

JTAG Test Data Output

1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,

1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K

1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P

No Connect

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 5 -

Rev 1.0

Aug. 2005

PIN CONFIGURATIONS

(TOP VIEW) K7I641882M(4Mx18)

Notes: 1. BW

controls write to DQ0:DQ8 and BW

controls write to DQ9:DQ17.

R/W

DQ9

DQ8

SA0

DQ7

DQ10

DQ11

DDQ

DQ6

DQ12

DDQ

DQ5

DQ13

DDQ

Doff

REF

DDQ

REF

DDQ

DQ4

DQ14

DDQ

DQ3

DQ15

DDQ

DQ2

DQ1

DQ16

DQ17

DQ0

TDO

TCK

TMS

TDI

PIN NAME

Notes: 1. C, C, K or K cannot be set to V

REF

voltage.

2. When ZQ pin is directly connected to V

output impedance is set to minimum value

and it cannot be connected to ground or left unconnected.

3. Not connected to chip pad internally.

SYMBOL

PIN NUMBERS

DESCRIPTION

NOTE

K, K

6B, 6A

Input Clock

C, C

6P, 6R

Input Clock for Output Data

CQ, CQ

11A, 1A

Output Echo Clock

Doff

DLL Disable when low

SA0

Burst Count Address Inputs

2A,3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

Address Inputs

DQ0-17

2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L

10M,3N,3P,11P

Data Inputs Outputs

R/W

Read, Write Control Pin, Read active

when high

Synchronous Load Pin, bus Cycle

sequence is to be defined when low

, BW

7B, 5A

Block Write Control Pin,active when low

REF

2H,10H

Input Reference Voltage

11H

Output Driver Impedance Control Input

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

Power Supply ( 1.8 V )

DDQ

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output Power Supply ( 1.5V or 1.8V )

4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N

Ground

TMS

10R

JTAG Test Mode Select

TDI

11R

JTAG Test Data Input

TCK

JTAG Test Clock

TDO

JTAG Test Data Output

7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D

1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G

1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L

1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P

No Connect

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 6 -

Rev 1.0

Aug. 2005

The K7I643682M and K7I641882M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.
They are organized as 2,097,152 words by 36bits for K7I643682M and 4,194,304 words by 18 bits for K7I641882M.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address and write address are registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using LD for port selection.
Byte write operation is supported with BW

and BW

( BW

and BW

pins for x18 ( x36 ) device.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7I643682M and K7I641882M are implemented with SAMSUNG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

GENERAL DESCRIPTION

Read Operations

Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the LD is disabled after a read operation, the K7I643682M and K7I641882M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.

Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with next K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command.
The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks.
When the LD is disabled, the K7I643682M and K7I641882M will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7I643682M and K7I641882M support byte write operations.
With activating BW

or BW

( BW

or BW

3 )

in write cycle, only one byte of input data is presented.

In K7I641882M, BW

controls write operation to D0:D8, BW

controls write operation to D9:D17.

And in K7I643682M BW

controls write operation to D18:D26, BW

controls write operation to D27:D35.

Write Operations

Single Clock Mode

K7I643682M and K7I641882M can be operated with the single clock pair K and K, insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up
and must be maintained high during operation.
After power up, this device can

t change to or from single clock mode.

System flight time and clock skew could not be compensated in this mode.

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 7 -

Rev 1.0

Aug. 2005

Depth Expansion

Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.

Clock Consideration

K7I643682M and K7I641882M utlizes internal DLL(Delay-Locked Loops) for maximum output data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.

The following power-up supply voltage application is recommended: V

, V

DDQ

, V

REF

, then V

. V

and V

DDQ

can be applied

simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

Power-Up/Power-Down Supply Voltage Sequencing

Echo clock operation

To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver.

Programmable Impedance Output Buffer Operation

The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V

through a precision resistor(RQ).

The value of RQ (within 15%) is five times the output impedance desired.
For example, 250

resistor will give an output impedance of 50

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous
behavior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 8 -

Rev 1.0

Aug. 2005

WRITE TRUTH TABLE

(x18)

Notes: 1. X means "Don

t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (

3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.

OPERATION

WRITE ALL BYTEs ( K

)

WRITE ALL BYTEs ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 1 ( K

)

WRITE BYTE 1 ( K

)

WRITE NOTHING ( K

)

WRITE NOTHING ( K

)

WRITE TRUTH TABLE

(x36)

Notes: 1. X means "Don

t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (

3. Assumes a WRITE cycle was initiated.

OPERATION

WRITE ALL BYTEs ( K

)

WRITE ALL BYTEs ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 1 ( K

)

WRITE BYTE 1 ( K

)

WRITE BYTE 2 and BYTE 3 ( K

)

WRITE BYTE 2 and BYTE 3 ( K

)

WRITE NOTHING ( K

)

WRITE NOTHING ( K

)

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

Notes: 1. X means "Don

t Care".

2. The rising edge of clock is symbolized by (

3. Before enter into clock stop status, all pending read and write operations will be completed.

R/W

OPERATION

Q(A0)

Q(A1)

Stopped

Previous state

Clock Stop

High-Z

No Operation

OUT

at C(t+1) Q

OUT

at C(t+2)

Read

Din at K(t+1)

Write

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 9 -

Rev 1.0

Aug. 2005

ABSOLUTE MAXIMUM RATINGS*

*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V

DDQ

must not exceed V

during normal operation.

PARAMETER

SYMBOL

RATING

UNIT

Voltage on V

Supply Relative to V

-0.5 to 2.9

Voltage on V

DDQ

Supply Relative to V

DDQ

-0.5 to V

Voltage on Input Pin Relative to V

-0.5 to V

DD+

0.3

Storage Temperature

STG

-65 to 150

Operating Temperature (Commercial / Industrial)

OPR

0 to 70 / -40 to 85

Storage Temperature Range Under Bias

BIAS

-10 to 85

DC ELECTRICAL CHARACTERISTICS

=1.8V

0.1V, T

C to +70

Notes: 1. Minimum cycle. I

OUT

=0mA.

2. |I

|=(V

DDQ

/2)/(RQ/5)

15% for 175

350

. |I

|=(V

DDQ

/2)/(RQ/5)

15% for 175

350

3. Minimum Impedance Mode when ZQ pin is connected to V

DDQ

4. Operating current is calculated with 50% read cycles and 50% write cycles.
5. Standby Current is only after all pending read and write burst opeactions are completed.
6. Programmable Impedance Mode.

7. These are DC test criteria. DC design criteria is V

REF

50mV. The AC V

levels are defined separately for measuring timing parameters.

8. V

(Min)DC=

0.3V, V

(Min)AC=-1.5V(pulse width

3ns).

9. V

(Max)DC=

DDQ

+0.3, V

(Max)AC=

DDQ

+0.85V(pulse width

3ns).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT NOTES

Input Leakage Current

=Max ; V

to V

DDQ

-2

Output Leakage Current

Output Disabled,

-2

Operating Current (x36):
QDR mode

=Max , I

OUT

=0mA

Cycle Time

KHKH

Min

-30

900

1,4

-25

800

-20

700

-16

650

Operating Current (x18):
QDR mode

=Max , I

OUT

=0mA

Cycle Time

KHKH

Min

-30

850

1,4

-25

750

-20

650

-16

600

Standby Current(NOP):
QDR mode

SB1

Device deselected, I

OUT

=0mA,

f=Max,
All Inputs

0.2V or

-0.2V

-30

400

1,5

-25

380

-20

360

-16

340

Output High Voltage

OH1

DDQ

/2-0.12 V

DDQ

/2+0.12

2,6

Output Low Voltage

OL1

DDQ

/2-0.12 V

DDQ

/2+0.12

2,6

Output High Voltage

OH2

=-1.0mA

DDQ

-0.2

DDQ

Output Low Voltage

OL2

=1.0mA

0.2

Input Low Voltage

-0.3

REF

-0.1

7,8

Input High Voltage

REF

+0.1

DDQ

+0.3

7,9

OPERATING CONDITIONS

PARAMETER

SYMBOL

MIN

MAX

UNIT

Supply Voltage

1.7

1.9

DDQ

1.4

1.9

Reference

Voltage

REF

0.68

0.95

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 10 -

Rev 1.0

Aug. 2005

AC ELECTRICAL CHARACTERISTICS

=1.8V

0.1V, T

C to +70

Notes: 1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transitioning edge of the input must :
a) Sustain a constant slew rate from the current AC level through the target AC level, V

IL(AC)

or V

IH(AC)

b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, V

IL(DC)

or V

IH(DC)

PARAMETER

SYMBOL

MIN

MAX

UNIT

NOTES

Input High Voltage

(AC)

REF

+ 0.2

1,2

Input Low Voltage

(AC)

REF

- 0.2

1,2

AC TIMING CHARACTERISTICS

=1.8V

0.1V, T

C to +70

Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW

,BW

and BW

, BW

, also for x36

3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX

is bigger than tCHQZ.

The specs as shown do not imply bus contention because tCHQX

is a MIN parameter that is worst case at totally different test conditions

C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70

C, 1.7V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a

0.1

ns variation from echo clock to data.

The data sheet parameters reflect tester guardbands and test setup variations.

PARAMETER

SYMBOL

-30

-25

-20

-16

UNIT NOTE

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Clock

Clock Cycle Time (K, K, C, C)

KHKH

3.30

5.25

4.00

6.30

5.00

7.88

6.00

8.40

Clock Phase Jitter (K, K, C, C)

KC var

0.20

Clock High Time (K, K, C, C)

KHKL

1.32

1.60

2.00

2.40

Clock Low Time (K, K, C, C)

KLKH

1.32

1.60

2.00

2.40

Clock to Clock (K

, C

)

KHKH

1.49

1.80

2.20

2.70

Clock to data clock (K

, K

)

KHCH

0.00

1.45

0.00

1.80

0.00

2.30

0.00

2.80

DLL Lock Time (K, C)

KC lock

1024

cycle

K Static to DLL reset

KC reset

Output Times

C, C High to Output Valid

CHQV

0.45

0.50

C, C High to Output Hold

CHQX

-0.45

-0.50

C, C High to Echo Clock Valid

CHCQV

0.45

0.50

C, C High to Echo Clock Hold

CHCQX

-0.45

-0.50

CQ, CQ High to Output Valid

CQHQV

0.27

0.30

0.35

0.40

CQ, CQ High to Output Hold

CQHQX

-0.27

-0.30

-0.35

-0.40

C, High to Output High-Z

CHQZ

0.45

0.50

C, High to Output Low-Z

CHQX1

-0.45

-0.50

Setup Times

Address valid to K rising edge

AVKH

0.40

0.50

0.60

0.70

Control inputs valid to K rising edge

IVKH

0.40

0.50

0.60

0.70

Data-in valid to K, K rising edge

DVKH

0.30

0.35

0.40

0.50

Hold Times

K rising edge to address hold

KHAX

0.40

0.50

0.60

0.70

K rising edge to control inputs hold

KHIX

0.40

0.50

0.60

0.70

K, K rising edge to data-in hold

KHDX

0.30

0.35

0.40

0.50

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 11 -

Rev 1.0

Aug. 2005

Note: For power-up, V

DDQ

+0.3V and V

1.7V and V

DDQ

1.4V t

200ms

DDQ

+0.5V

20% t

KHKH

(MIN)

-0.5V

20% t

KHKH

(MIN)

Undershoot Timing

Overershoot Timing

DDQ

SRAM

Zo=50

0.75V

REF

250

AC TEST OUTPUT LOAD

AC TEST CONDITIONS

Note: Parameters are tested with RQ=250

Parameter

Sym-

Value

Unit

Core Power Supply Voltage

1.7~1.9

Output Power Supply Voltage

DDQ

1.4~1.9

Input High/Low Level

1.25/0.25

Input Reference Level

REF

0.75

Input Rise/Fall Time

0.3/0.3

Output Timing Reference Level

DDQ

+0.25V

-0.25V

THERMAL RESISTANCE

Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. T

+ P

PRMETER

SYMBOL

Typ

Unit

NOTES

Junction to Ambient

Junction to Case

2.48

PIN CAPACITANCE

Note: 1. Parameters are tested with RQ=250

and V

DDQ

=1.5V.

2. Periodically sampled and not 100% tested.

PRMETER

SYMBOL

TESTCONDITION

TYP

MAX

Unit

NOTES

Address Control Input Capacitance

=0V

3.5

Input and Output Capacitance

OUT

=0V

Clock Capacitance

CLK

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 13 -

Rev 1.0

Aug. 2005

NOP

READ

(burst of 2)

WRITE

(burst of 2)

READ

READ
(burst of 2)

IVKH

KHKH

UNDEFINED

DON

T CARE

NOTE
1. Q

refers to output from address A. Q

refers to output from the next internal burst address following A, etc.

2. Outputs are disabled(High-Z) one clock cycle after a NOP .
3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent
bus contention.

KHKH

KLKH

R/W

KHIX

NOP

KHKL

KHKH

KHKL

KLKH

KHKH

CQHQZ

TIMING WAVE FORMS OF READ, WRITE AND NOP

READ
(burst of 2)

NOP

(burst of 2)

WRITE

READ
(burst of 2)

NOP

KHCH

CHQV

CHQX1

CHCQX

CHCQV

CHQX

CHQZ

KHDX

DVKH

CHQV

CHCQX

CHCQV

(Note3)

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 14 -

Rev 1.0

Aug. 2005

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to V

to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to V

through a resistor. TDO should be left unconnected.

TAP Controller State Diagram

JTAG Block Diagram

SRAM
CORE

BYPASS Reg.
Identification Reg.
Instruction Reg.

Control Signals

TAP Controller

TDO

TDI

TMS

TCK

Test Logic Reset

Run Test Idle

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

JTAG Instruction Coding

NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to V

when BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.

5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.

IR2 IR1 IR0

Instruction

TDO Output

Notes

EXTEST

Boundary Scan Register

IDCODE

Identification Register

SAMPLE-Z

Boundary Scan Register

RESERVED Do Not Use

SAMPLE

Boundary Scan Register

RESERVED Do Not Use

BYPASS

Bypass Register

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 15 -

Rev 1.0

Aug. 2005

ID REGISTER DEFINITION

Note : Part Configuration
/def=011 for 72Mb, /wx=11 for x36, 10 for x18.
/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O

Part

Revision Number

(31:29)

Part Configuration

(28:12)

Samsung JEDEC Code

(11: 1)

Start Bit(0)

2Mx36

000

00def0wx0t0q0b0s0

00001001110

4Mx18

000

00def0wx0t0q0b0s0

00001001110

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

ID Register

Boundary Scan

2Mx36

3 bits

1 bit

32 bits

109 bits

4Mx18

3 bits

1 bit

32 bits

109 bits

Note: 1. NC pins are read as "X" ( i.e. don

t care.)

ORDER

PIN ID

10D

10C

11D

11B

11C

10B

11A

10A

ORDER

PIN ID

100

101

102

103

104

105

106

107

108

109

Internal

ORDER

PIN ID

11P

10P

10N

10M

11N

11L

11M

10L

11K

10K

10J

11J

11H

10G

11F

11G

10F

11E

10E

BOUNDARY SCAN EXIT ORDER

2Mx36 & 4Mx18 DDRII CIO b2 SRAM

K7I643682M

K7I641882M

- 16 -

Rev 1.0

Aug. 2005

JTAG DC OPERATING CONDITIONS

Note: 1. The input level of SRAM pin is to follow the SRAM DC specification

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

1.7

1.8

1.9

Input High Level

1.3

+0.3

Input Low Level

-0.3

0.5

Output High Voltage(I

=-2mA)

1.4

Output Low Voltage(I

=2mA)

0.4

JTAG TIMING DIAGRAM

JTAG AC Characteristics

Parameter

Symbol

Min

Max

Unit

Note

TCK Cycle Time

CHCH

TCK High Pulse Width

CHCL

TCK Low Pulse Width

CLCH

TMS Input Setup Time

MVCH

TMS Input Hold Time

CHMX

TDI Input Setup Time

DVCH

TDI Input Hold Time

CHDX

SRAM Input Setup Time

SVCH

SRAM Input Hold Time

CHSX

Clock Low to Output Valid

CLQV

JTAG AC TEST CONDITIONS

Note: 1. See SRAM AC test output load on page 11.

Parameter

Symbol

Min

Unit

Note

Input High/Low Level

1.3/0.5

Input Rise/Fall Time

TR/TF

1.0/1.0

Input and Output Timing Reference Level

0.9

TCK

TMS

TDI

CHCH

MVCH

CHMX

CHCL

CLCH

DVCH

CHDX

CLQV

TDO

(SRAM)

SVCH

CHSX

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