256Kx72 Pipelined NtRAM

- 1 -

Rev 1.0

April 2003

K7N167245A

Document Title

256Kx72-Bit Pipelined NtRAM

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Revision History

Rev. No.

0.0
0.1
0.2
0.3

1.0

Remark

Preliminary
Preliminary
Preliminary
Preliminary

Final

History

1. Initial document.
1. Add JTAG Scan Order
1. Update DC characteristics(icc,isb)
1. Speed bin merge.
From K7N167249A to K7N167245A.
2. AC parameter change.
tOH(min)/tLZC(min) from 0.8 to 1.5 at -25
tOH(min)/tLZC(min) from 1.0 to 1.5 at -22
tOH(min)/tLZC(min) from 1.0 to 1.5 at -20

1. Correct the sleep mode current on page 11. (60mA)
2. Update the Undershoot diagram.

Draft Date

April. 21. 2001
May. 10. 2001
Aug. 30. 2001
Dec. 26. 2001

Feb. 11, 2003

256Kx72 Pipelined NtRAM

- 2 -

Rev 1.0

April 2003

K7N167245A

16Mb NtRAM(Flow Through / Pipelined) , Double Late Write RAM x72 Ordering Informa

tion

NOTE :

119BGA is only supported with K7N161801A - HC13, K7N163645A - HC16, K7N161845A - HC13 and K7N163645 - HC16.

Org.

Part Number

Mode

VDD

Speed

FT ; Access Time(ns)

Pipelined ; Cycle Time(MHz)

PKG

Temp

1Mx18

K7M161825A-Q(F)C(I)65/75/85

FlowThrough

3.3

6.5/7.5/8.5ns

Q : 100TQFP
F : 165FBGA

(Commercial
Temperature

Range)

(Industrial

Temperature

Range)

K7N161801A-Q(F)C(I)25/22/20/16/13

Pipelined

3.3

250/225/200/167/133MHz

K7N161845A-Q(F)C(I)25/22/20/16/13

Pipelined

2.5

250/225/200/167/133MHz

512Kx32

K7M163225A-QC(I)65/75/85

FlowThrough

3.3

6.5/7.5/8.5ns

K7N163201A-QC(I)25/22/20/16/13

Pipelined

3.3

250/225/200/167/133MHz

K7N163245A-QC(I)25/22/20/16/13

Pipelined

2.5

250/225/200/167/133MHz

512Kx36

K7M163625A-Q(F)C(I)65/75/85

FlowThrough

3.3

6.5/7.5/8.5ns

K7N163601A-Q(F)C(I)25/22/20/16/13

Pipelined

3.3

250/225/200/167/133MHz

K7N163645A-Q(F)C(I)25/22/20/16/13

Pipelined

2.5

250/225/200/167/133MHz

256Kx72

K7N167245A-HC25/22/20/16/13

Pipelined

(Normal

2.5

250/225/200/167/133MHz

H : 209BGA

K7Z167285A-HC30/27/25

Pipelined

(Sigma Type) 1.8

300/275/250MHz

256Kx72 Pipelined NtRAM

- 3 -

Rev 1.0

April 2003

K7N167245A

256Kx72-Bit Pipelined NtRAM

The K7N167245A is 18,874,368-bits Synchronous Static SRAMs.
The NtRAM

, or No Turnaround Random Access Memory uti-

lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output enable
and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored
by an edge triggered output register and then released to the out-
put buffers at the next rising edge of clock.
The K7N167245A are implemented with SAMSUNG

s high perfor-

mance CMOS technology and is available in 209BGA packages.
Multiple power and ground pins minimize ground bounce.

GENERAL DESCRIPTION

FEATURES

�

2.5V

�

5% Power Supply.

� Byte Writable Function.
�

Enable clock and suspend operation.

�

Single READ/WRITE control pin.

�

Self-Timed Write Cycle.

�

Three Chip Enable for simple depth expansion with no data

contention .

�

A interleaved burst or a linear burst mode.

�

Asynchronous output enable control.

� Power Down mode.
�

TTL-Level Three-State Outputs.

�

209BGA(11x19 Ball Grid Array Package).

NtRAM

and No Turnaround Random Access Memory are trademarks of Samsung.

LOGIC BLOCK DIAGRAM

WE
BW

CLK

CKE

ADV

DQa

~ DQh

ADDRESS

REGISTER

L
O

I
C

DQPa ~ DQPh

OUTPUT

BUFFER

REGISTER

DATA-IN

REGISTER

DATA-IN

REGISTER

BURST

ADDRESS

COUNTER

WRITE

ADDRESS

REGISTER

WRITE

CONTROL

LOGIC

I
S

A [0:17]

LBO

(x=a ~ h)

256K x 72

MEMORY

ARRAY

FAST ACCESS TIMES

PARAMETER

Symbol -25

-22

-20 -16 -13 Unit

Cycle Time

tCYC

4.0 4.4 5.0 6.0 7.5 ns

Clock Access Time

tCD

2.6 2.8 3.2 3.5 4.2 ns

Output Enable Access Time

tOE

2.6 2.8 3.2 3.5 4.2 ns

256Kx72 Pipelined NtRAM

- 4 -

Rev 1.0

April 2003

K7N167245A

209BGA PACKAGE PIN CONFIGURATIONS

(TOP VIEW)

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

ADV
WE
CLK
CKE
CS

BWx

(x=a~h)

OE
ZZ
LBO

TCK
TMS
TDI
TDO

Address Inputs

Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs

Output Enable
Power Sleep Mode
Burst Mode Control

JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output

N.C.

DQa
DQb
DQc
DQd
DQe
DQf
DQg
DQh
DQPa~Ph

DDQ

Power Supply
Ground

No Connect

Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs

Output Power Supply

K7N167245A(256K x 72)

Notes :

1. ** A

and A

are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

DQg

ADV

DQb

DQg

BWc

B Wg

BW b

BWf

DQb

DQg

BWh

B Wd

BW e

BWa

DQb

DQg

DQb

DQPg

DQPc

DDQ

DQPf

DQPb

DQc

DQf

DQc

DDQ

DQf

DQc

DQf

DQc

DDQ

DQf

CLK

CKE

DQh

DDQ

DQa

DQh

DQa

DQh

DDQ

DQa

DQh

DQa

DQPd

DQPh

DDQ

DQPa

DQPe

DQd

LBO

DQe

DQd

NC(64M)

NC(32M)

DQe

DQd

1**

DQe

DQd

TMS

TDI

0**

TDO

TCK

DQe

256Kx72 Pipelined NtRAM

- 5 -

Rev 1.0

April 2003

K7N167245A

FUNCTION DESCRIPTION

BURST SEQUENCE TABLE

(Interleaved Burst, LBO=High)

LBO PIN

HIGH

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0
0
1
1

0
1
0
1

0
0
1
1

1
0
1
0

1
1
0
0

0
1
0
1

1
1
0
0

1
0
1
0

BQ TABLE

(Linear Burst, LBO=Low)

Note :

1. LBO pin must be tied to High or Low, and Floating State must not be allowed

LBO PIN

LOW

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0
0
1
1

0
1
0
1

0
1
1
0

1
0
1
0

1
1
0
0

0
1
0
1

1
0
0
1

1
0
1
0

The K7N167245A is NtRAM

designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from

Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.

Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.

NtRAM

latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables( CS

, CS

)

are active .
Output Enable(OE) can be used to disable the output at any given time.

Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS

, CS

) are active, the write enable input signals WE are driven

high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.

Write operation occurs when WE is driven low at the rising edge of the clock. B W[h:a] can be used for byte write operation. The pipe-
lined NtRAM

uses a late-late write cycle to utilize 100% of the bandwidth.

At the first rising edge of the clock, W E and address are registered, and the data associated with that address is required two cycle
later.

Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.

During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.

256Kx72 Pipelined NtRAM

- 6 -

Rev 1.0

April 2003

K7N167245A

STATE DIAGRAM FOR NtRAM

BEGIN

WRITE

BURST

WRITE

BEGIN

READ

WRITE

REA

BURST

READ

ITE

READ

DESELECT

READ

WRITE

BURST

Notes :

1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does

not change the state of the device.

2. States change on the rising edge of the clock(CLK)

COMMAND

ACTION

DESELECT

READ

BEGIN READ

WRITE

BEGIN WRITE

BURST

BEGIN READ
BEGIN WRITE
CONTINUE DESELECT

256Kx72 Pipelined NtRAM

- 7 -

Rev 1.0

April 2003

K7N167245A

SYNCHRONOUS TRUTH TABLE

Notes

: 1. X means "Don

t Care". 2. The rising edge of clock is symbolized by (

3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).

ADV

BW x

CKE

CLK

ADDRESS ACCESSED

OPERATION

N/A

Not Selected

N/A

Not Selected

N/A

Not Selected

N/A

Not Selected Continue

External Address

Begin Burst Read Cycle

Next Address

Continue Burst Read Cycle

External Address

NOP/Dummy Read

Next Address

Dummy Read

External Address

Begin Burst Write Cycle

Next Address

Continue Burst Write Cycle

N/A

NOP/Write Abort

Next Address

Write Abort

Current Address

Ignore Clock

TRUTH TABLES

WRITE TRUTH TABLE

(x72)

Notes :

1. X means "Don

t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(

BW a

BW b

BWc

BWd

BWe

BW f

BW g

BWh

OPERATION

READ

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE BYTE e

WRITE BYTE f

WRITE BYTE g

WRITE BYTE h

WRITE ALL BYTEs

WRITE ABORT/NOP

256Kx72 Pipelined NtRAM

- 8 -

Rev 1.0

April 2003

K7N167245A

ASYNCHRONOUS TRUTH TABLE

OPERATION

I/O STATUS

Sleep Mode

High-Z

Read

High-Z

Write

Din, High-Z

Deselected

High-Z

Notes
1. X means "Don

t Care".

2. Sleep Mode means power Sleep Mode of which stand-by current does

not depend on cycle time.

3. Deselected means power Sleep Mode of which stand-by current

depends on cycle time.

ABSOLUTE MAXIMUM RATINGS*

*Note

: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

PARAMETER

SYMBOL

RATING

UNIT

Voltage on V

Supply Relative to V

-0.3 to 3.6

Voltage on Any Other Pin Relative to V

-0.3 to V

+0.3

Power Dissipation

1.6

Storage Temperature

STG

-65 to 150

�

Operating Temperature

OPR

0 to 70

�

Storage Temperature Range Under Bias

BIAS

-10 to 85

�

OPERATING CONDITIONS

�

*Note

: V

and V

DDQ

must be supplied with identical vlotage levels

The above parameters are also guaranteed at industrial temperature range.

PARAMETER

SYMBOL

MIN

Typ.

MAX

UNIT

Supply Voltage

2.375

2.5

2.625

DDQ

2.375

2.5

2.625

Ground

CAPACITANCE*

=25

�

C, f=1MHz)

*Note

: Sampled not 100% tested.

PARAMETER

SYMBOL

TEST CONDITION

MIN

MAX

UNIT

Input Capacitance

=0V

Output Capacitance

OUT

=0V

256Kx72 Pipelined NtRAM

- 9 -

Rev 1.0

April 2003

K7N167245A

=0 to 70

�

C, V

=2.5V

�

5%, unless otherwise specified)

TEST CONDITIONS

* The above parameters are also guaranteed at industrial temperature range.

PARAMETER

VALUE

Input Pulse Level

0 to 2.5V

Input Rise and Fall Time(Measured at 20% to 80%)

1.0V/ns

Input and Output Timing Reference Levels

DDQ

Output Load

See Fig. 1

SS-

0.8V

20% t

CYC

(MIN)

DC ELECTRICAL CHARACTERISTICS

=2.5V

�

5%, T

�

C to +70

�

Notes :

1. The above parameters are also guaranteed at industrial temperature range.

2. Reference AC Operating Conditions and Characteristics for input and timing.

3. Data states are all zero.

4. In Case of I/O Pins, the Max. V

DDQ

+0.3V

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

NOTES

Input Leakage Current(except ZZ)

=Max ; V

to V

-2

�

Output Leakage Current

Output Disabled,

-2

�

Operating Current

=Max I

OUT

=0mA

Cycle Time

CYC

Min

-25

620

1,2

-22

580

-20

540

-16

500

-13

450

Standby Current

Device deselected, I

OUT

=0mA,

, f=Max,

All Inputs

0.2V or

-0.2V

-25

150

-22

140

-20

130

-16

120

-13

110

SB1

Device deselected, I

OUT

=0mA, ZZ

0.2V, f=0,

All Inputs=fixed (V

-0.2V or 0.2V)

SB2

Device deselected, I

OUT

=0mA, ZZ

-0.2V,

f=Max, All Inputs

Output Low Voltage

=1.0mA

0.4

Output High Voltage

=-1.0mA

2.0

Input Low Voltage

-0.3*

0.7

Input High Voltage

1.7

+0.3**

SS-

0.4V

256Kx72 Pipelined NtRAM

- 10 -

Rev 1.0

April 2003

K7N167245A

=2.5V

�

5%, T

=0 to 70

�

Output Load(B),

(for t

LZC

, t

LZOE

, t

HZOE

& t

HZC

)

Dout

1538

5pF*

+2.5V

1667

Fig. 1

* Including Scope and Jig Capacitance

Output Load(A)

Dout

Zo=50

RL=50

VL=V

DDQ

30pF*

AC TIMING CHARACTERISTICS

Notes

: 1. The above parameters are also guaranteed at industrial temperature range.

2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled

low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.

4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,

Both cases must meet setup and hold times.

5. To avoid bus contention, At a given voltage and temperature t

LZC

is more than t

HZC.

The specs as shown do not imply bus contention because t

LZC

is a Min. parameter that is worst case at totally different test conditions

�

C,2.625V) than t

HZC

, which is a Max. parameter(worst case at 70

�

C,2.375V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

PARAMETER

SYMBOL

-25

-22

-20

-16

-13

UNIT

MIN MAX MIN

MAX MIN MAX

MIN MAX MIN MAX

Cycle Time

CYC

4.0

4.4

5.0

6.0

7.5

Clock Access Time

2.6

2.8

3.2

3.5

4.2

Output Enable to Data Valid

2.6

2.8

3.2

3.5

4.2

Clock High to Output Low-Z

LZC

1.5

Output Hold from Clock High

1.5

Output Enable Low to Output Low-Z

LZOE

Output Enable High to Output High-Z

HZOE

2.6

2.8

3.0

3.5

Clock High to Output High-Z

HZC

2.6

2.8

3.0

3.5

Clock High Pulse Width

1.7

2.0

2.2

3.0

Clock Low Pulse Width

1.7

2.0

2.2

3.0

Address Setup to Clock High

1.2

1.4

1.5

CKE Setup to Clock High

CES

1.2

1.4

1.5

Data Setup to Clock High

1.2

1.4

1.5

Write Setup to Clock High (WE, BW

)

1.2

1.4

1.5

Address Advance Setup to Clock High

ADVS

1.2

1.4

1.5

Chip Select Setup to Clock High

CSS

1.2

1.4

1.5

Address Hold from Clock High

0.3

0.4

0.5

CKE Hold from Clock High

CEH

0.3

0.4

0.5

Data Hold from Clock High

0.3

0.4

0.5

Write Hold from Clock High (WE , BW

)

0.3

0.4

0.5

Address Advance Hold from Clock High

ADVH

0.3

0.4

0.5

Chip Select Hold from Clock High

CSH

0.3

0.4

0.5

ZZ High to Power Down

PDS

cycle

ZZ Low to Power Up

PUS

cycle

256Kx72 Pipelined NtRAM

- 11 -

Rev 1.0

April 2003

K7N167245A

SLEEP MODE

SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I

SB2

. The duration of

SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, I

SB2

is guaranteed after the time t

ZZI

is met. Any operation pending when entering SLEEP

MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during t

PUS

, only a DESELECT or READ cycle should be given

while the SRAM is transitioning out of SLEEP MODE.

SLEEP MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

Current during SLEEP MODE

SB2

ZZ active to input ignored

PDS

cycle

ZZ inactive to input sampled

PUS

cycle

ZZ active to SLEEP current

ZZI

cycle

ZZ inactive to exit SLEEP current

RZZI

PDS

ZZ setup cycle

RZZI

Isupply

All inputs

(except ZZ)

Outputs

(Q)

ZZI

PUS

ZZ recovery cycle

Deselect or Read Only

High-Z

DON

T CARE

SB2

SLEEP MODE WAVEFORM

Normal

operation

cycle

Deselect or Read Only

256Kx72 Pipelined NtRAM

- 12 -

Rev 1.0

April 2003

K7N167245A

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to V

to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to V

through a resistor. TDO should be left unconnected.

TAP Controller State Diagram

JTAG Block Diagram

SRAM

CORE

BYPASS Reg.
Identification Reg.
Instruction Reg.

Control Signals

TAP Controller

TDO

TDI

TMS

TCK

Test Logic Reset

Run Test Idle

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

JTAG Instruction Coding

NOTE

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to V

when BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.

5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.

IR2 IR1 IR0

Instruction

TDO Output

Notes

0 EXTEST

Boundary Scan Register

1 IDCODE

Identification Register

0 SAMPLE-Z

Boundary Scan Register

1 BYPASS

Bypass Register

0 SAMPLE

Boundary Scan Register

1 RESERVED Do Not Use

0 BYPASS

Bypass Register

1 BYPASS

Bypass Register

256Kx72 Pipelined NtRAM

- 13 -

Rev 1.0

April 2003

K7N167245A

ID REGISTER DEFINITION

Part

Revision Number

(31:28)

Part Configuration

(27:18)

Vendor Definition

(17:12)

Samsung JEDEC Code

(11: 1)

Start Bit(0)

256Kx72

0000

00110 00101

XXXXXX

00001001110

209BGA BOUNDARY SCAN EXIT ORDER(x72)

DQf

11J

DQf

11H

DQf

10H

DQf

10G

DQf

11G

DQf

11F

DQf

10F

DQPf

10E

DQPb

11E

DQb

11D

10W

DQe

DQb

10D

11W

DQe

DQb

10C

11V

DQe

DQb

11C

10V

DQe

DQb

11B

10U

DQe

DQb

10B

11U

DQe

DQb

10A

11T

DQe

DQb

11A

10T

DQe

BWa

11R

DQPe

BW f

10R

DQPa

10P

DQa

BWe

11P

DQa

BWb

11N

DQa

10N

DQa

10M

DQa

11M

DQa

11L

DQa

10L

DQa

11K

ADV

10K

BWd

10J

DQf

BWg

DQPh

106

BWh

DQPd

107

BWc

DQd

108

DQd

109

DQg

DQd

110

DQg

DQd

111

DQg

DQd

112

DQg

DQd

113

DQg

DQd

114

DQg

DQd

115

DQg

LBO

116

DQg

117

DQPg

118

DQPc

119

DQc

120

DQc

121

DQc

122

DQc

CLK

CKE

DQh

100

DQh

101

DQh

102

DQh

103

DQh

104

DQh

105

DQh

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

ID Register

Boundary Scan

256Kx72

3 bits

1 bits

32 bits

122 bits

NOTE, NC ; Don

t Care

256Kx72 Pipelined NtRAM

- 14 -

Rev 1.0

April 2003

K7N167245A

JTAG DC OPERATING CONDITIONS

NOTE

: The input level of SRAM pin is to follow the SRAM DC specification

In Case of I/O Pins, the Max. V

DDQ

+0.3V.

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

2.375

2.5

2.625

Input High Level

1.7

+0.3

Input Low Level

-0.3

0.7

Output High Voltage

2.0

Output Low Voltage

0.4

JTAG TIMING DIAGRAM

JTAG AC Characteristics

Parameter

Symbol

Min

Max

Unit

Note

TCK Cycle Time

CHCH

TCK High Pulse Width

CHCL

TCK Low Pulse Width

CLCH

TMS Input Setup Time

MVCH

TMS Input Hold Time

CHMX

TDI Input Setup Time

DVCH

TDI Input Hold Time

CHDX

SRAM Input Setup Time

SVCH

SRAM Input Hold Time

CHSX

Clock Low to Output Valid

CLQV

JTAG AC TEST CONDITIONS

Parameter

Symbol

Min

Unit

Note

Input High/Low Level

2.5/0

Input Rise/Fall Time

TR/TF

1.0/1.0

Input and Output Timing Reference Level

DDQ

TCK

TMS

TDI

CHCH

MVCH

CHMX

CHCL

CLCH

DVCH

CHDX

CLQV

TDO

(SRAM)

SVCH

CHSX

256Kx72 Pipelined NtRAM

- 15 -

Rev 1.0

April 2003

K7N167245A

l
o

r
e

I
T

a
t
a

I
M

I
N

T
E

:

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I
T

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L

m

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s

W

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L
,

a
n

d

B

x

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=

L

m

e
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C

L
,

C

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H

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L
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A
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A
H

S
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C
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L
Z
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C
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2

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2

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1

t

C

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d
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f
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d

Y
C

D
V

A
D

256Kx72 Pipelined NtRAM

- 16 -

Rev 1.0

April 2003

K7N167245A

I
M

I
N

l
o

c
k

r
e

I
T

t
a

I
n

-
1

-
2

-
3

-
4

-
1

-
2

3
-
3

t
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S

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4

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:

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L

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H

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H

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L

a
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d

C

,

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r

C

=

L
,

a
n
d

C

-
4

Z
O

-
3

256Kx72 Pipelined NtRAM

- 17 -

Rev 1.0

April 2003

K7N167245A

I
M

I
N

/
W

I
T

l
o

c
k

r
e

I
T

t
a

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Y
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H

:

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L

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L
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x

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L

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C

L
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C

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d

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L

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H

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C

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H

,

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r

C

L

a
n
d

C

,

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C

=

L
,

a
n
d

C

256Kx72 Pipelined NtRAM

- 18 -

Rev 1.0

April 2003

K7N167245A

I
M

I
N

F
O

I
O

l
o

r
e
s

I
T

a
t
a

I
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t
a

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S

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f
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Y
C

T
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:

W

I
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=

L

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a
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s

W

=

L
,

a
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d

B

x

=

L

=

L

m

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a
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C

L
,

C

=

H

a
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d

=

L

=

H

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a
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s

C

=

H

,

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r

C

=

L

a
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d

C

=

H

,

o
r

C

L
,

a
n
d

C

=

L

L
Z
C

H
Z
C

256Kx72 Pipelined NtRAM

- 19 -

Rev 1.0

April 2003

K7N167245A

T
I
M

I
N

I
O

l
o

r
e
s

I
T

a
t
a

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Y
C

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E
H

L
Z
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L
Z
C

T
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:

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=

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W

=

L
,

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d

B

x

=

L

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L

m

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C

L
,

C

=

H

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d

=

L

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H

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a
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s

C

=

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C

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=

H

,

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C

L
,

a
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d

C

=

L

H
Z
C

Электронный компонент: K7N167245A