256Kx36 & 512Kx18 Flow-Through NtRAM
TM
- 1 -
Rev 3.0
Nov. 2003
K7M803625B
K7M801825B
Document Title
256Kx36 & 512Kx18-Bit Flow Through NtRAM
TM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
1.0
2.0
2.1
3.0
Remark
Preliminary
Preliminary
Preliminary
Final
Final
Final
Final
History
1. Initial document.
1. Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change I
SB2
form 50mA to 60mA
Change ordering information( remove 225MHz at Nt-Pipelined)
1. Delete 119BGA package
1. Remove x32 organization
2. Remove -85 speed bin
Draft Date
May. 18. 2001
Aug. 11. 2001
Aug. 28. 2001
Nov. 16. 2001
April. 01. 2002
April. 04. 2003
Nov. 17. 2003
256Kx36 & 512Kx18 Flow-Through NtRAM
TM
- 2 -
Rev 3.0
Nov. 2003
K7M803625B
K7M801825B
8Mb NtRAM(Flow Through / Pipelined) Ordering Information
Org.
Part Number
Mode
VDD
Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz)
PKG
Temp
512Kx18
K7M801825B-QC(I)65/75
FlowThrough
3.3
6.5/7.5 ns
Q:
100TQFP
C:
Commercial
Temperature
Range
I:
Industrial
Temperature
Range
K7N801801B-QC(I)16/13
Pipelined
3.3
167/133 MHz
K7N801809B-QC(I)25
Pipelined
3.3
250 MHz
K7N801845B-QC(I)16/13
Pipelined
2.5
167/133 MHz
K7N801849B-QC(I)25
Pipelined
2.5
250MHz
256Kx36
K7M803625B-QC(I)65/75
FlowThrough
3.3
6.5/7.5 ns
K7N803601B-QC(I)16/13
Pipelined
3.3
167/133 MHz
K7N803609B-QC(I)25
Pipelined
3.3
250 MHz
K7N803645B-QC(I)16/13
Pipelined
2.5
167/133 MHz
K7N803649B-QC(I)25
Pipelined
2.5
250 MHz
256Kx36 & 512Kx18 Flow-Through NtRAM
TM
- 3 -
Rev 3.0
Nov. 2003
K7M803625B
K7M801825B
256Kx36 & 512Kx18-Bit Flow Through NtRAM
TM
The K7M803625B and K7M801825B are
9,437,184-bit Synchronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M803625B and K7M801825B are implemented with
SAMSUNG
s high performance CMOS technology and is avail-
able in 100pin TQFP and Multiple power and ground pins mini-
mize ground bounce.
GENERAL DESCRIPTION
FEATURES
LOGIC BLOCK DIAGRAM
3.3V+0.165V/-0.165V Power Supply.
I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
Byte Writable Function.
nable clock and suspend operation.
Single READ/WRITE control pin.
Self-Timed Write Cycle.
Three Chip Enable for simple depth expansion with no data
contention .
A interleaved burst or a linear burst mode.
Asynchronous output enable control.
Power Down mode.
TTL-Level Three-State Outputs.
100-TQFP-1420A
Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
Parameter
Symbol
-65
-75 Unit
Cycle Time
t
CYC
7.5
8.5
ns
Clock Access Time
t
CD
6.5
7.5
ns
Output Enable Access Time
t
OE
3.5
3.5
ns
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
WE
BW
x
CLK
CKE
CS
1
CS
2
CS
2
ADV
OE
ZZ
DQa
0
~ DQd
7
or
DQa
0
~ DQb
8
ADDRESS
ADDRESS
REGISTER
CONT
R
O
L
L
OGI
C
A
0
~A
1
36 or 18
DQPa ~ DQPd
BUFFER
DATA-IN
REGISTER
K
REGISTER
BURST
ADDRESS
COUNTER
WRITE
CONTROL
LOGIC
C
O
NT
RO
L
RE
GIS
T
ER
K
A [0:17]or
A [0:18]
LBO
A
2
~A
17
or
A
2
~A
18
A
0
~A
1
(x=a,b,c,d or a,b)
256Kx36 , 512Kx18
MEMORY
ARRAY
256Kx36 & 512Kx18 Flow-Through NtRAM
TM
- 4 -
Rev 3.0
Nov. 2003
K7M803625B
K7M801825B
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
Vss
V
DD
V
DD
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A
6
A
7
CS
1
CS
2
BW
d
BW
c
BW
b
BW
a
CS
2
V
DD
V
SS
CLK
WE
CKE
OE
ADV
N.C
.
A
17
A
8
81
A
9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A
16
A
15
A
14
A
13
A
12
A
11
A
10
N.C
.
N.C
.
V
DD
V
SS
N.C
.
N.C
.
A
0
A
1
A
2
A
3
A
4
A
5
31
LBO
PIN NAME
Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A
0
- A
17
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx(x=a,b,c,d)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,44
45,46,47,48,49,50,81
82,83,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,16,41,65,91
14,17,40,66,67,90
38,39,42,43,84
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
K7M803625B(256Kx36)
V
SS
256Kx36 & 512Kx18 Flow-Through NtRAM
TM
- 5 -
Rev 3.0
Nov. 2003
K7M803625B
K7M801825B
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
8
DQb
7
V
SSQ
V
DDQ
DQb
6
DQb
5
V
SS
V
DD
V
DD
V
SS
DQb
4
DQb
3
V
DDQ
V
SSQ
DQb
2
DQb
1
DQb
0
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQa
0
DQa
1
DQa
2
V
SSQ
V
DDQ
DQa
3
DQa
4
V
SS
V
SS
V
DD
ZZ
DQa
5
DQa
6
V
DDQ
V
SSQ
DQa
7
DQa
8
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A
6
A
7
CS
1
CS
2
BW
b
BW
a
CS
2
V
DD
V
SS
CLK
WE
CKE
OE
ADV
N.C
.
A
18
A
8
81
A
9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A
17
A
16
A
15
A
14
A
13
A
12
A
11
N.C
.
N.C
.
V
DD
V
SS
N.C
.
N.C
.
A
0
A
1
A
2
A
3
A
4
A
5
31
LBO
K7M801825B(512Kx18)
N.C
.
N.C.
PIN NAME
Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A
0
- A
18
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx(x=a,b)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,44
45,46,47,48,49,50,80
81,82,83,99,100
85
88
89
87
98
97
92
93,94
86
64
31
V
DD
V
SS
N.C.
DQa
0
~a
8
DQb
0
~b
8
V
DDQ
V
SSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,16,41,65,91
14,17,40,66,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,84,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
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