K7P401823M

- 1 -

K7P403623M

128Kx36 & 256Kx18 SRAM

Rev 2.0

Oct. 2000

Document Title

128Kx36 & 256Kx18 Synchronous Pipelined SRAM

Revision History

Rev. No.

Rev. 0.0

Rev. 0.1

Rev. 0.2

Rev. 0.3

Rev. 1.0

Rev. 2.0

Remark

Preliminary

Final

History

- Preliminary specification release

- Change specification format.
No change was made in parameters.

- Updated Part Number and Pin Description.
Updated and added Input/Output Voltage Level and V

DDQ

Updated DC Characteristics and Pin Capacitance.
Updated AC Characteristics, Test Conditions and Timing Wave Form.
For JTAG, updated Vendor Definition and added t

SVCH

CHSX.

- Updated PECL Clock Input Level, Output Leakage Current
Updated 119BGA Package Thermal Characteristics

- Final specification release

- Single ended LVCMOS clock operation added

Draft Date

April, 1997

Jan. 1998

Aug. 1998

Dec. 1998

Oct. 2000

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.

K7P401823M

- 2 -

K7P403623M

128Kx36 & 256Kx18 SRAM

Rev 2.0

Oct. 2000

PIN DESCRIPTION

Pin Name

Pin Description

Pin Name

Pin Description

K, K

Differential Clocks(PECL Level)

DDQ

Output Power Supply

SAn

Synchronous Address Input

, M

Read Protocol Mode Pins ( M

, M

)

DQn

Bi-directional Data Bus

Asynchronous Output Enable

Synchronous Global Write Enable

Synchronous Select

SWa

Synchronous Byte a Write Enable

TCK

JTAG Test Clock

SWb

Synchronous Byte b Write Enable

TMS

JTAG Test Mode Select

SWc

Synchronous Byte c Write Enable

TDI

JTAG Test Data Input

SWd

Synchronous Byte d Write Enable

TDO

JTAG Test Data Output

Asynchronous Power Down

GND

Core Power Supply

No Connection

128Kx36 & 256Kx18 Synchronous Pipelined SRAM

FEATURES

FUNCTIONAL BLOCK DIAGRAM

· 128Kx36 or 256Kx18 Organizations.
· 3.3V Core/ Output Power Supply.
· LVTTL 3.3V Input and Output Levels.
· Differential, PECL Clock Inputs K, K.
or Single ended LVCMOS Clock
· Synchronous Read and Write Operation
· Registered Input and Latched Output
· Internal Pipeline Latches to Support Late Write.
· Byte Write Capability(four byte write selects, one for each 9 bits)
· Synchronous or Asynchronous Output Enable.
· Power Down Mode via ZZ Signal.
· JTAG 1149.1 Compatible Test Access port.
· 119(7x17) Pin Ball Grid Array Package(14mmx22mm).

Organiza-

tion

Part Number

Cycle

Time

Access

Time

128Kx36

K7P403623M-H65

6.5

K7P403623M-H70

6.5

7.0

K7P403623M-H75

7.5

256Kx18

K7P401823M-H65

6.5

K7P401823M-H70

6.5

7.0

K7P401823M-H75

7.5

SA[0:16] or SA[0:17]

SWx

128Kx36

Data In

DQx[1:9]

(x=a, b, c, d)

or (x=a, b)

(x=a, b, c, d)

or (x=a, b)

256Kx18

Array

e
c
o

d
e
r

Column Decoder

Write/Read Circuit

0 1

Data Out

Latch

Read

Address

Write

Address

Latch

SWx

K7P401823M

- 3 -

K7P403623M

128Kx36 & 256Kx18 SRAM

Rev 2.0

Oct. 2000

PACKAGE PIN CONFIGURATIONS

(TOP VIEW)

K7P403623M(128Kx36)

NOTE : 1. NC* is used for the Boundary Scan.

2. NC** is reserved for TRST input

3. NC*** is reserved for HSTL interface.

DDQ

DQc

NC*

DQb

DQc

DQb

DDQ

DQc

DQb

DDQ

DQc

SWc

NC*

SWb

DQb

DQc

NC*

DQb

DDQ

NC***

DDQ

DQd

DQa

DQd

SWd

SWa

DQa

DDQ

DQd

DQa

DDQ

DQd

DQa

DQd

DQa

DDQ

TMS

TDI

TCK

TDO

NC**

DDQ

KM718FV4022(256Kx18)

NOTE : 1. NC* is used for the Boundary Scan.

2. NC** is reserved for TRST input

3. NC*** is reserved for HSTL interface.

DDQ

DQb

NC*

DQa

DQb

DQa

DDQ

DQa

DDQ

DQb

SWb

NC*

DQa

DQb

NC*

DQa

DDQ

NC***

DDQ

DQb

DQa

DQb

SWa

DQa

DDQ

DQb

DDQ

DQb

DQa

DQb

DQa

DDQ

TMS

TDI

TCK

TDO

NC**

DDQ

K7P401823M

- 4 -

K7P403623M

128Kx36 & 256Kx18 SRAM

Rev 2.0

Oct. 2000

FUNCTION DESCRIPTION

The K7P403623M andK7P401823M are 4,718,592 bit Synchronous SRAM. It is organized as 131,072 words of 36 bits(or 262,144
words of 18 bits) and is implemented in SAMSUNG's advanced CMOS technology.
Single differential PECL level K clocks or single ended LVCMOS clock are used to initiate the read/write operation and all internal
operations are self-timed. At the rising edge of K clock, all addresses, Write Enables, Synchronous Select and Data Ins are regis-
tered internally. Data outputs are updated from output latches of the falling edge of K clock. An internal write data buffer allows write
data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

Read Operation

During reads, the address is registered during the clock rising edge and the internal array is read. The data is driven to the CPU in
the following cycle. SS is driven low during this cycle, signaling that the SRAM should drive out the data.
During consecutive read cycles where the address is the same, the data output must be held constantly without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.

Write(Store) Operation

All addresses and SW are both sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising
clock, one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the
Address, SW and SW[a:d] are valid to signal that a valid operations is on the Address and Control Input.
Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write
cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of
read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the
same as the SW signal.

Bypass Read Operation

Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to
be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address
is the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the
SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have
new byte data from the write data buffer and the other bytes from the SRAM array.

Low Power Dissipation Mode

During normal operation, asynchronous signal ZZ must be pulled low. Low Power Mode is enabled by switching ZZ high. When the
SRAM is in Power Down Mode, the outputs will go to a Hi-Z state and the SRAM will draw standby current. SRAM data will be pre-
served and a recovery time(t

ZZR

) is required before the SRAM resumes to normal operation.

TRUTH TABLE

SWa

SWb

SWc

SWd

DQa

DQb

DQc

DQd

Operation

Hi-Z

Hi-Z Power Down Mode. No Operation

Hi-Z

Hi-Z Output Disabled. No Operation

Hi-Z

Hi-Z Output Disabled. No Operation

OUT

Read Cycle

Hi-Z

Hi-Z No Bytes Written

Hi-Z

Hi-Z Write first byte

Hi-Z

Hi-Z Write second byte

Hi-Z

Hi-Z Write third byte

Hi-Z

Write fourth byte

Write all byte

K7P401823M

- 5 -

K7P403623M

128Kx36 & 256Kx18 SRAM

Rev 2.0

Oct. 2000

ABSOLUTE MAXIMUM RATINGS

NOTE : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter

Symbol

Value

Unit

Core Supply Voltage Relative to V

-0.5 to 3.9

Output Supply Voltage Relative to V

DDQ

Voltage on any I/O pin Relative to V

TERM

-0.5 to V

+0.5

Maximum Power Dissipation

Output Short-Circuit Current

OUT

Operating Temperature

OPR

0 to 70

Storage Temperature

STG

-55 to 125

DC CHARACTERISTICS

NOTE :1. Minimum cycle. I

OUT

=0mA.

2. 50% read cycles.

Parameter

Symbol

Min

Max

Unit

Note

Average Power Supply Operating Current-x36
(V

or V

, ZZ & SS=V

)

DD65

DD7

DD75

600
550
500

1, 2

Average Power Supply Operating Current-x18
(V

or V

, ZZ & SS=V

)

DD65

DD7

DD75

550
500
450

1, 2

Power Supply Standby Current
(V

or V

, ZZ=V

)

Input Leakage Current
(V

or V

DDQ

)

-1

Output Leakage Current
(V

OUT

or V

DDQ

, ZZ=V

, G=V

)

-1

Output High Voltage(I

=-4mA) for V

DDQ

=3.3V

Output High Voltage(I

=-4mA) for V

DDQ

=2.5V

OH1

OH2

2.4
2.0

DDQ

Output Low Voltage(I

=4mA)

0.4

RECOMMENDED DC OPERATING CONDITIONS

NOTE
1. For operation with differential PECL clock inputs.
2. For operation with single ended LVCMOS clock input.

Parameter

Symbol

Min

Typ

Max

Unit

Note

Core Power Supply Voltage

3.15

3.3

3.45

Output Power Supply Voltage

DDQ

2.35

2.5

3.45

Input High Level

1.7

+0.3

Input Low Level

-0.3

0.7

PECL Clock Input High Level

-PECL

2.135

2.420

PECL Clock Input Low Level

-PECL

1.490

1.825

Clock Input Signal Voltage

-0.3

3.45

Clock Input Differential Voltage

DIF

-CLK

0.2

+0.6

Clock Input Common Mode Voltage

-CLK

1.1

2.1

Operating Junction Temperature

110

K7P401823M

- 6 -

K7P403623M

128Kx36 & 256Kx18 SRAM

Rev 2.0

Oct. 2000

AC CHARACTERISTICS

Parameter

Symbol

-65

-70

-75

Unit

Note

Min

Max

Min

Max

Min

Max

Clock Cycle Time

KHKH

6.0

6.5

7.0

Clock High Pulse Width

KHKL

2.0

Clock Low Pulse Width

KLKH

2.0

Clock High to Output Valid

KHQV

6.5

7.0

7.5

Clock Low to Output Valid

KLQV

2.5

3.0

Clock Low to Output Hold

KLQX

0.5

Address Setup Time

AVKH

0.5

Address Hold Time

KHAX

1.0

Write Data Setup Time

DVKH

0.5

Write Data Hold Time

KHDX

1.0

SW, SW[a:d] Setup Time

WVKH

0.5

SW, SW[a:d] Hold Time

KHWX

1.0

SS Setup Time

SVKH

0.5

SS Hold Time

KHSX

1.0

Clock High to Output Hi-Z

KHQZ

2.5

3.0

3.5

Clock Low to Output Low-Z

KLQX1

0.5

G High to Output High-Z

GHQZ

2.5

3.0

3.5

G Low to Output Low-Z

GLQX

0.5

G Low to Output Valid

GLQV

2.5

3.0

3.5

ZZ High to Power Down(Sleep Time)

ZZE

6.5

7.0

7.5

ZZ Low to Recovery(Wake-up Time)

ZZR

6.0

6.5

7.0

Z0=50

1.25V

*Capacitive load consists of all components

AC TEST OUTPUT LOAD

Dout

of the tester environment

20pF*

PIN CAPACITANCE

NOTE : Periodically sampled and not 100% tested.(dV=0V, f=1MHz)

Parameter

Symbol

Typ

Max

Unit

Input Capacitance

Output Capacitance

OUT

AC TEST CONDITIONS

Parameter

Symbol

Value

Unit

Core Power Supply Voltage

3.15~3.45

Output Power Supply Voltage

DDQ

2.4~2.6

Input High/Low Level

1.7/0.7

Clock Input High/Low Level(PECL) V

IH/

2.4/1.5

Input Rise/Fall Time

1.0/1.0

Clock Input Rise/Fall Time(PECL)

1.0/1.0

Input and Out Timing Reference Level

1.25

Clock Input Timing Reference Level

Cross Point

K7P401823M

- 7 -

K7P403623M

128Kx36 & 256Kx18 SRAM

Rev 2.0

Oct. 2000

TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES

NOTE
1. D3 is the input data written in memory location A3.
2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last write

cycle address.

3. Data is valid at the output at the later of t

KHQV

following the rising clock edge, or t

KLQV

following the fallowing clock edge.

4. When SS is sampled high or SW is sampled low on the rising edge of clock, the outputs go into Hi-Z state no later than t

KHQZ

following

the rising clock edge.

5. When SS is low and SW is high on the rising edge of clock, the outputs go into Low-Z state(being driven) no earlier than t

KLQX1

following

the next falling edge of clock.

6. When the SRAM is deselected, the output goes Hi-Z at t

KHQZ

following the rising clock edge. On the next read cycle, note that the

SRAM output do not leave the Hi-Z state until t

KLQX1

after the falling clock edge.

SAn

SWx

DQn

KHKH

KHAX

AVKH

KHKL

KLKH

KHSX

SVKH

WVKH

KHWX

WVKH

KHWX

KLQV

KHQZ

WVKH

KHWX

KHQV

KHQZ

DVKH

KHDX

GHQZ

GLQV

KLQV

KLQX

KLQV

GLQX

KLQX1

K7P401823M

- 9 -

K7P403623M

128Kx36 & 256Kx18 SRAM

Rev 2.0

Oct. 2000

JTAG Instruction Coding

NOTE
1. Places DQs in Hi-Z in order to sample all input data regardless of

other SRAM inputs.

2. TDI is sampled as an input to the first ID register to allow for the serial

shift of the external TDI data.

3. Bypass register is initiated to VSS when BYPASS instruction is

invoked. The Bypass Register also holds serially loaded TDI when
exiting the Shift DR states.

4. SAMPLE instruction dose not places DQs in Hi-Z.

IR2 IR1 IR0 Instruction

TDO Output

Notes

0 SAMPLE-Z Boundary Scan Register

1 IDCODE

Identification Register

0 SAMPLE-Z Boundary Scan Register

1 BYPASS

Bypass Register

0 SAMPLE

Boundary Scan Register

1 BYPASS

Bypass Register

0 BYPASS

Bypass Register

1 BYPASS

Bypass Register

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Teat Access Port(TAP). The package pads are monitored by the Serial
Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is
not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction
Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to V

to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to V

through a resistor. TDO should be left unconnected.

JTAG Block Diagram

SRAM

CORE

BYPASS Reg.
Identification Reg.
Instruction Reg.

Control Signals

TAP Controller

TDO

TDI

TMS

TCK

TAP Controller State Diagram

Test Logic Reset

Run Test Idle

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

K7P401823M

- 10

K7P403623M

128Kx36 & 256Kx18 SRAM

Rev 2.0

Oct. 2000

BOUNDARY SCAN EXIT ORDER(x36)

DQc

DQb

DQc

DQb

DQc7

DQb

DQc

DQb

DQc

DQb

DQc

DQb

DQc

DQb

DQc

DQb

DQc

DQb

SWc

SWb

SWa

DQa

SWd

DQa

DQd

DQa

DQd

DQa

DQd

DQa

DQd

DQa

DQd

DQa

DQd

DQa

DQd

DQa

DQd

BOUNDARY SCAN EXIT ORDER(x18)

DQa

DQb

DQa

DQb

DQa

DQb

SWb

SWa

DQa

DQb

DQa

DQb

DQa

DQb

DQa

DQb

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

ID Register

Boundary Scan

128Kx36

3 bits

1 bits

32 bits

70 bits

256Kx18

3 bits

1 bits

32 bits

51 bits

ID REGISTER DEFINITION

Part

Revision Number

(31:28)

Part Configuration

(27:18)

Vendor Definition

(17:12)

Samsung JEDEC Code

(11: 1)

Start Bit(0)

128Kx36

0000

00101 00100

xxxxxx

00001001110

256Kx18

0000

00110 00011

xxxxxx

00001001110

NOTE : 1. Pins 6B and 2B are no connection pin to internal chip. These pins are place holders for 16M part and the scanned data are fixed to "0" for this

4M parts.

K7P401823M

- 11

K7P403623M

128Kx36 & 256Kx18 SRAM

Rev 2.0

Oct. 2000

JTAG DC OPERATING CONDITIONS

NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

3.15

3.3

3.45

Input High Level

2.0

+0.3

Input Low Level

-0.3

0.8

Output High Voltage(I

=-2mA)

2.4

Output Low Voltage(I

=2mA)

0.4

JTAG TIMING DIAGRAM

JTAG AC TEST CONDITIONS

NOTE : 1. See SRAM AC test output load.

Parameter

Symbol

Min

Unit

Note

Input High/Low Level

3.0/0.0

Input Rise/Fall Time

TR/TF

2.0/2.0

Input and Output Timing Reference Level

1.5

TCK

TMS

TDI

TDO

CHCH

CHCL

CLCH

DVCH

CHDX

CLQV

MVCH

CHMX

JTAG AC Characteristics

Parameter

Symbol

Min

Max

Unit

Note

TCK Cycle Time

CHCH

TCK High Pulse Width

CHCL

TCK Low Pulse Width

CLCH

TMS Input Setup Time

MVCH

TMS Input Hold Time

CHMX

TDI Input Setup Time

DVCH

TDI Input Hold Time

CHDX

SRAM Input Setup Time

SVCH

SRAM Input Hold Time

CHSX

Clock Low to Output Valid

CLQV

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