512Kx36 & 1Mx18 QDR

b2 SRAM

- 1 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

Document Title

512Kx36-bit, 1Mx18-bit QDR

SRAM

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Revision History

Rev. No.

0.0

0.1

0.2

0.3

0.4

0.5

1.0

Remark

Advance

Preliminary

Final

History

1. Initial document.

1. Amendment
1) Page 3,4 PIN NAME DESCRIPTION
W (4A) : from Read Control Pin to Write Control
R (8A) : from Write Control Pin to Read Control
BW

(7B)

(7A)

(5A)

(5B)

from

Read Control Pin to Byte Wrtie Control

2) Page 7 STATE DIAGRAM
from LEAD NOP to READ NOP
1. Amendment
1) Page 8 WRITE TRUTH TABLE(x36)
BW

,BW

values for WRITE ALL BYTEs( K

)

and

WRITE ALLBYTEs( K

) :

from "H" to " L"

2) Page 13 TIMING WAVE FORMS Note 2 supplement

1. 1.8V I/O supply voltage addition
1) Page 2 FEATURES
2) Page 3,4 PIN NAME V

DDQ

3) Page 10, OPERATING CONTITIONS
4) Page 11 AC TEST CONTITIONS
2. Amendment
1) Page 15 BOUNDARY SCAN ORDER EXIT

1. Icc, Isb addition
2. 1.8V Vddq addition

1. Reserved pin for high density name change from NC to Vss/SA

1. Final SPEC release
2. Modify thermal resistance

Draft Date

April, 30, 2001

May, 13, 2001

May, 26, 2001

June, 11, 2001

Sep,03, 2001

Nov, 30, 2001

July, 03. 2002

512Kx36 & 1Mx18 QDR

b2 SRAM

- 2 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

512Kx36-bit, 1Mx18-bit QDR

SRAM

FEATURES

FUNCTIONAL BLOCK DIAGRAM

2.5V+0.1V/-0.1V Power Supply.

· I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,

1.8V+0.1V/-0.1V for 1.8V I/O

Separate independent read and write data ports

with concurrent read and write operation

· HSTL I/O.
· Full data coherency, providing most current data .
· Synchronous pipeline read with self timed early write.
· Registered address, control and data input/output.
· DDR(Double Data Rate) Interface on read and write ports.
· Fixed 2-bit burst for both read and write operation.
· Clock-stop supports to reduce current.
·

Two input clocks(K and K) for accurate DDR timing at clock

rising edges only.

Two Input clocks for output data(C and C) to minimize

clock-skew and flight-time mismatches.

Single address bus.

Byte writable function.

· Sepatate read/write control pin(R and W)
· Simple depth expansion with no data contention.
·

Programmable output impedance.

· JTAG 1149.1 compatible test access port.
· 165FBGA(11x15 ball aray FBGA) with body size of 13x15mm

ADDRESS

D(Data in)

ADD
REG

DATA

REG

CLK

GEN

CTRL

LOGIC

512Kx36

1Mx18

MEMORY

ARRAY

WRITE DRIVER

36 (or 18)

4(or 2)

Organization

Part

Number

Cycle

Time

Access

Time

Unit

X36

K7Q163652A-FC16

6.0

2.5

K7Q163652A-FC13

7.5

3.0

K7Q163652A-FC10

10.0

3.0

X18

K7Q161852A-FC16

6.0

2.5

K7Q161852A-FC13

7.5

3.0

K7Q161852A-FC10

10.0

3.0

SELECT OUTPUT CONTROL

I
T

/
R

I
V

Notes: 1. Numbers in ( ) are for x18 device.

18 (or 19)

36 (or 18)

Q(Data Out)

QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology.

36 (or 18)

(or 36)

512Kx36 & 1Mx18 QDR

b2 SRAM

- 3 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

PIN CONFIGURATIONS

(TOP VIEW) K7Q161852A(1Mx18)

Notes: 1. * Checked pins are reserved for higher density address, i.e. 3A for 32Mb, 10A for 64Mb and 2A for 128Mb.
2. BW

controls write to D0:D8 and BW

controls write to D9:D17.

/SA*

NC/SA*

/SA*

D10

D11

Q10

Q11

DDQ

Q12

D12

DDQ

D13

Q13

DDQ

REF

DDQ

REF

D14

DDQ

Q14

DDQ

Q15

D15

DDQ

D16

D17

Q16

Q17

TDO

TCK

TMS

TDI

PIN NAME

Notes: 1. C, C, K or K cannot be set to V

REF

voltage.

2. When ZQ pin is directly connected to V

output impedance is set to minimum value

and it cannot be connected to ground or left unconnected.

3. Not connected to chip pad internally.

SYMBOL

PIN NUMBERS

DESCRIPTION

NOTE

K, K

6B, 6A

Input Clock

C, C

6P, 6R

Input Clocks for Output data

9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

Address Inputs

0-17

10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,

3F,2G,3J,3L,3M,2N

Data Inputs

0-17

11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,

2F,3G,3K,2L,3N,3P

Data Outputs

Write Control

Read Control

, BW

7B, 5A

Byte Write Control Pin

REF

2H,10H

Input Reference Voltage

11H

Output Driver Impedance Control Input

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

Power Supply ( 2.5V )

DDQ

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output Power Supply ( 1.5V or 1.8V )

2A,10A,4C,8C,4D-8D,5E-7E,

6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N

Ground

TMS

10R

JTAG Test Mode Select

TDI

11R

JTAG Test Data Input

TCK

JTAG Test Clock

TDO

JTAG Test Data Output

1A,3A,7A,11A,1B,5B,9B,10B,1C,2C,9C,1D,9D,

10D,1E,2E,9E,1F,9F,10F,1G,9G,10G,1H,1J,2J,9J,1K,

2K,9J,1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P

No Connect

512Kx36 & 1Mx18 QDR

b2 SRAM

- 4 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

PIN CONFIGURATIONS

(TOP VIEW) K7Q163652A(512Kx36)

Notes : 1. * Checked pins are reserved for higher density address, i.e. 9A for 32Mb, 3A for 64Mb, 10A for 128Mb and 2A for 256Mb.

2. BW

controls write to D0:D8, BW

controls write to D9:D17, BW

controls write to D18:D26 and BW

controls write to D27:D35.

/SA*

NC/SA*

/SA*

Q27

Q18

D18

D17

Q17

D27

Q28

D19

D16

D28

D20

Q19

Q16

D15

Q29

D29

Q20

DDQ

Q15

Q30

Q21

D21

DDQ

D14

Q14

D30

D22

Q22

DDQ

Q13

D13

REF

DDQ

REF

D31

Q31

D23

DDQ

D12

Q32

D32

Q23

DDQ

Q12

Q33

Q24

D24

DDQ

D11

Q11

D33

Q34

D25

D10

D34

D26

Q25

Q10

Q35

D35

Q26

TDO

TCK

TMS

TDI

PIN NAME

Notes: 1. C, C, K or K cannot be set to V

REF

voltage.

2. When ZQ pin is directly connected to V

output impedance is set to minimum value

and it cannot be connected to ground or left unconnected.

3. Not connected to chip pad internally.

SYMBOL

PIN NUMBERS

DESCRIPTION

NOTES

K, K

6B, 6A

Input Clock

C, C

6P, 6R

Input Clocks for Output data

4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

Address Inputs

D0-35

10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L

9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N

1C,1D,2E,1G,1J,2K,1M,1N,2P

Data Inputs

Q0-35

11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L

9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N

3P,1B,2C,1E,1F,2J,1K,1L,2M,1P

Data Outputs

Write Control Pin

Read Control Pin

,BW

7B,7A,5A,5B

Byte Write Control Pin

REF

2H,10H

Input Reference Voltage

11H

Output Driver Impedance Control Input

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

Power Supply ( 2.5V )

DDQ

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output Power Supply ( 1.5V or 1.8V )

2A,10A,4C,8C,4D-8D,5E-7E,

6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N

Ground

TMS

10R

JTAG Test Mode Select

TDI

11R

JTAG Test Data Input

TCK

JTAG Test Clock

TDO

JTAG Test Data Output

1A,3A,9A,11A,1H

No Connect

512Kx36 & 1Mx18 QDR

b2 SRAM

- 5 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

The K7Q163652A and K7Q161852A are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.
They are organized as 524,288 words by 36bits for K7Q163652A and 1,048,576 words by 18 bits for K7Q161852A.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram

on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.

And totally independent read and write ports eliminate the need for high speed bus turn around.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).
Read address is registered on rising edges of the input K clocks, and write address is

registered on rising edges of the input K clocks.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 2-bit sequential for both read and write operations.

Synchronous pipeline read and early write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.

Byte write operation is supported with BW

and BW

( BW

and BW

3 )

pins.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7Q163652A and K7Q161852A are implemented with SAMSUNG's high performance 6T CMOS technology and is available

in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

GENERAL DESCRIPTION

Read Operations

Read cycles are initiated by activating R at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.

The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.

Continuous read operations are initiated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K instead of C and C.

When the R is disabled after a read operation, the K7Q163652A and K7Q161852A will first complete burst read operation

before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

512Kx36 & 1Mx18 QDR

b2 SRAM

- 6 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with following K clock.

For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command.
The first "early" data is transfered and registered in to the device synchronous with same K clock rising edge with W presented.

Next burst data is transfered and registered synchronous with following K clock rising edge.

Continuous write operations are initiated with K rising edge.

And "early writed" data is presented to the device on every rising edge of both K and K clocks.

When the W is disabled, the K7Q163652A and K7Q161852A will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.

The K7Q163652A and K7Q161852A support byte write operations.
With activating BW

or BW

( BW

or BW

3 )

in write cycle, only one byte of input data is presented.

In K7Q161852A, BW

controls write operation to D0:D8, BW

controls write operation to D9:D17.

And in K7Q163652A BW

controls write operation to D18:D26, BW

controls write operation to D27:D35.

Write Operations

Programmable Impedance Output Buffer Operation

Single Clock Mode

Depth Expansion

The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V

through a precision resistor(RQ).

The value of RQ (within 15%) is five times the output impedance desired.

For example, 250

resistor will give an output impedance of 50

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs"

or other anomalous behavior in the SRAM.

There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up,

the SRAM needs 1024 non-read cycles.

The K7Q163652A and K7Q161852A can be used with the single clock pair K and K.

In this mode, C and C must be tied high during power up and this single clock pair control both the input and output registers.

C and C cannot be tied high during operation.
System flight time and clock skew could not be compensated in single clock mode.

Separate input and output ports enables easy depth expansion.

Each port can be selected and deselected independently

and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.

512Kx36 & 1Mx18 QDR

b2 SRAM

- 7 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

READ

DDR READ

DDR WRITE

READ NOP

POWER-UP

WRITE NOP

LOAD NEW

WRITE ADDRESS

LOAD NEW

READ ADDRESS

ALWAYS

(FIXED)

WRITE

STATE DIAGRAM

Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.

2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case.

3. Read and write state machine can be active simultaneously.

4. State machine control timing sequence is controlled by K.

ALWAYS

(FIXED)

READ

WRITE

READ

WRITE

READ

WRITE

512Kx36 & 1Mx18 QDR

b2 SRAM

- 8 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

Notes: 1. X means "Don

t Care".

2. The rising edge of clock is symbolized by (

3. Before enter into clock stop status, all pending read and write operations will be completed.

OPERATION

D(A0)

D(A1)

Q(A0)

Q(A1)

Stopped

Previous state

Clock Stop

High-Z

No Operation

OUT

at C(t+1)

OUT

at C(t+1)

Read

Din at K(t)

Write

WRITE TRUTH TABLE

(x18)

Notes: 1. X means "Don

t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(

OPERATION

READ/NOP

WRITE ALL BYTEs ( K

)

WRITE ALL BYTEs ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 1 ( K

)

WRITE BYTE 1 ( K

)

WRITE NOTHING ( K

)

WRITE NOTHING ( K

)

WRITE TRUTH TABLE

(x36)

Notes: 1. X means "Don

t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(

OPERATION

READ/NOP

WRITE ALL BYTEs ( K

)

WRITE ALL BYTEs ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 1 ( K

)

WRITE BYTE 1 ( K

)

WRITE BYTE 2 and BYTE 3 ( K

)

WRITE BYTE 2 and BYTE 3 ( K

)

WRITE NOTHING ( K

)

WRITE NOTHING ( K

)

512Kx36 & 1Mx18 QDR

b2 SRAM

- 9 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

DC ELECTRICAL CHARACTERISTICS

=2.5V

0.1V, T

C to +70

Notes: 1. Minimum cycle. I

OUT

=0mA.

2. |I

|=(V

DDQ

/2)/(RQ/5)

15% @V

DDQ

/2 for 175

350

3. |I

|=(V

DDQ

/2)/(RQ/5)

15% @V

DDQ

/2 for 175

350

4. Minimum Impedance Mode when ZQ pin is connected to V

5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.

8. These are DC test criteria. DC design criteria is V

REF

50mV. The AC V

levels are defined separately for measuring

timing parameters.
9. V

(Min)DC=

0.3V, V

(Min)AC=-1.5V(pulse width

3ns).

10. V

(Max)DC=

DDQ

+0.3, V

(Max)AC=

DDQ

+0.85V(pulse width

3ns).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT NOTES

Input Leakage Current

=Max ; V

to V

DDQ

-2

Output Leakage Current

Output Disabled,

-2

Operating Current (x18) : DDR

=Max , I

OUT

=0mA

Cycle Time

KHKH

Min

-16

550

1,5

-13

470

-10

420

Operating Current (x36) : DDR

=Max , I

OUT

=0mA

Cycle Time

KHKH

Min

-16

590

1,5

-13

500

-10

450

Standby Current(NOP) : DDR

SB1

Device deselected, I

OUT

=0mA,

f=Max,

All Inputs

0.2V or

-0.2V

-16

220

1,6

-13

200

-10

190

Output High Voltage

OH1

DDQ

2,7

Output Low Voltage

OL1

DDQ

3,7

Output High Voltage

OH2

=-1.0mA

DDQ

-0.2

DDQ

Output Low Voltage

OL2

=1.0mA

0.2

Input Low Voltage

-0.3

REF

-0.1

8,9

Input High Voltage

REF

+0.1

DDQ

+0.3

8,10

ABSOLUTE MAXIMUM RATINGS*

*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. V

DDQ

must not exceed V

during normal operation.

PARAMETER

SYMBOL

RATING

UNIT

Voltage on V

Supply Relative to V

-0.5 to 3.6

Voltage on V

DDQ

Supply Relative to V

DDQ

-0.5 to V

Voltage on Input Pin Relative to V

-0.5 to V

DD+

0.3

Power Dissipation

1.8

Storage Temperature

STG

-65 to 150

Operating Temperature

OPR

0 to 70

Storage Temperature Range Under Bias

BIAS

-10 to 85

512Kx36 & 1Mx18 QDR

b2 SRAM

- 10 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

AC TIMING CHARACTERISTICS

=2.5V

0.1V, T

C to +70

Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W,BW

,BW

and (BW

, BW

, also for x36)

3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX

is bigger than tCHQZ.

The specs as shown do not imply bus contention beacuse tCHQX

is a MIN parameter that is worst case at totally different test conditions

C, 2.6V) than tCHQZ, which is a MAX parameter(worst case at 70

C, 2.4V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

PARAMETER

SYMBOL

-16

-13

-10

UNITS

NOTES

MIN

MAX

MIN

MAX

MIN

MAX

Clock

Clock Cycle Time(K, K, C, C)

KHKH

7.5

Clock HIGH time (K, K, C, C)

KHKL

2.4

3.0

3.5

Clock Low time (K, K, C, C)

KLKH

2.4

3.0

3.5

Clock to clock (K

, C

)

KHKH

2.7

3.3

3.4

4.1

4.6

5.4

Clock to data clock (K

, K

)

KHCH

0.0

2.0

0.0

2.5

0.0

3.0

Output Times

C, C High to Output Valid

CHQV

2.5

3.0

C, C High to Output Hold

CHQX

1.2

C High to Output High-Z

CHQZ

2.5

3.0

C High to Output Low-Z

CHQX1

1.2

Setup Times

Address valid to K rising edge

AVKH

0.7

0.8

1.0

Control inputs valid to K rising edge

IVKH

0.7

0.8

1.0

Data-in valid to K, K rising edge

DVKH

0.7

0.8

1.0

Hold Times

K rising edge to address hold

KHAX

0.7

0.8

1.0

K rising edge to control inputs hold

KHIX

0.7

0.8

1.0

K, K rising edge to data-in hold

KHDX

0.7

0.8

1.0

OPERATING CONDITIONS

PARAMETER

SYMBOL

MIN

MAX

UNIT

Supply Voltage

2.4

2.6

DDQ

1.4

1.9

Reference

Voltage

REF

0.68

0.95

Ground

Note: For power-up, V

DDQ

+0.3V and V

2.4V and V

DDQ

1.4V for t

200ms

DDQ

+0.7V

20% t

KHKH

(MIN)

-0.7V

20% t

KHKH

(MIN)

Undershoot Timing

Overershoot Timing

512Kx36 & 1Mx18 QDR

b2 SRAM

- 11 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

APPLICATION INFORMATION

PIN CAPACITANCE

Note: 1. Parameters are tested with RQ=250

and V

DDQ

=1.5V.

2. Periodically sampled and not 100% tested.

PRMETER

SYMBOL

TESTCONDITION

MIN

MAX

Unit

NOTES

Address Control Input Capacitance

=0V

Input and Output Capacitance

OUT

=0V

Clock Capacitance

CLK

1Mx18

SRAM#1

0-17

R W BW

0-17

C C

SRAM#4

R=50

Vt=V

REF

R=250

0-17

RW BW

0-17

C C

Data In

Data Out

Address

BW0-7

Return CLK

Source CLK

Return CLK

Source CLK

MEMORY
CONTROLLER

THERMAL RESISTANCE

Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. T

+ P

PRMETER

SYMBOL

TYP

Unit

NOTES

Junction to Ambient

24.0

Junction to Case

2.8

Junction to Pins

5.5

Q/2

SRAM

Zo=50

0.75V

REF

250

AC TEST OUTPUT LOAD

AC TEST CONDITIONS

Note: Parameters are tested with RQ=250

Parameter

Symbol

Value

Unit

Core Power Supply Voltage

2.4~2.6

Output Power Supply Voltage

DDQ

1.4~1.9

Input High/Low Level

1.25/0.25

Input Reference Level

REF

0.75

Input Rise/Fall Time

0.3/0.3

Output Timing Reference Level

DDQ

512Kx36 & 1Mx18 QDR

b2 SRAM

- 12 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

Q1-1

Q1-2

Q2-1

Q2-2

Q3-1

Q3-2

KLKH

KHKH

KHKL

AVKH

KHAX

IVKH

KHIX

CHQX

KHCH

CHQV

CHQX

Q(Data Out)

Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.

2. Outputs are disabled(High-Z) one cycle after a NOP.

TIMING WAVE FORMS OF READ AND NOP

Don

t Care Undefined

CHQZ

D1-1

D1-2

D2-1

D2-2

D3-1

D3-2

D(Data In)

KLKH

KHKH

KHKL

AVKH

KHAX

IVKH

KHIX

DVKH

KHDX

KHIX

TIMING WAVE FORMS OF WRITE AND NOP

READ

NOP

READ

WRITE

NOP

WRITE

NOP

512Kx36 & 1Mx18 QDR

b2 SRAM

- 13 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

Q1-1

Q1-2

Q3-1

Q3-2

Q5-1

Q5-2

TIMING WAVE FORMS OF READ, WRITE AND NOP

D(Data In)

Q(Data Out)

D2-1

D2-2

D4-1

D4-2

D7-1

D7-2

D6-1

D6-2

Don

t Care Undefined

Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.

2. Outputs are disabled(High-Z) one cycle after a NOP.

3. If address A1=A2, data Q1-1=D2-1, data Q1-2=D2-2. Write data is forwarded immediately as read results.

4. BWx are assumed active.

READ

WRITE

NOP

WRITE

READ

WRITE

READ

WRITE

512Kx36 & 1Mx18 QDR

b2 SRAM

- 14 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to V

to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to V

through a resistor. TDO should be left unconnected.

TAP Controller State Diagram

JTAG Block Diagram

SRAM
CORE

BYPASS Reg.

Identification Reg.

Instruction Reg.

Control Signals

TAP Controller

TDO

TDI

TMS
TCK

Test Logic Reset

Run Test Idle

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

JTAG Instruction Coding

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to V

when BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

IR2

IR1

IR0

Instruction

TDO Output

Notes

EXTEST

Boundary Scan Register

IDCODE

Identification Register

SAMPLE-Z

Boundary Scan Register

BYPASS

Bypass Register

SAMPLE

Boundary Scan Register

RESERVED

Do Not Use

BYPASS

Bypass Register

BYPASS

Bypass Register

512Kx36 & 1Mx18 QDR

b2 SRAM

- 15 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

ID REGISTER DEFINITION

Part

Revision Number

(31:28)

Part Configuration

(27:18)

Vendor Definition

(17:12)

Samsung JEDEC Code

(11: 1)

Start Bit(0)

1Mx18

0000

01000 00011

XXXXXX

00001001110

512Kx36

0000

00111 00100

XXXXXX

00001001110

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

ID Register

Boundary Scan

1Mx18

3 bits

1 bits

32 bits

107 bits

512Kx36

3 bits

1 bits

32 bits

107 bits

Note: 1. NC pins are read as "X" ( i.e. don

t care.)

BIT

PIN ID

10D

10C

11D

11B

11C

10B

11A

10A

BIT

PIN ID

100

101

102

103

104

105

106

107

BIT

PIN ID

11P

10P

10N

10M

11N

11L

11M

10L

11K

10K

10J

11J

11H

10G

11F

11G

10F

11E

10E

BOUNDARY SCAN EXIT ORDER

512Kx36 & 1Mx18 QDR

b2 SRAM

- 16 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

JTAG DC OPERATING CONDITIONS

Note: 1. The input level of SRAM pin is to follow the SRAM DC specification

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

2.4

2.5

2.6

Input High Level

1.7

+0.3

Input Low Level

-0.3

0.7

Output High Voltage(I

=-2mA)

2.0

Output Low Voltage(I

=2mA)

0.4

JTAG TIMING DIAGRAM

JTAG AC Characteristics

Parameter

Symbol

Min

Max

Unit

Note

TCK Cycle Time

CHCH

TCK High Pulse Width

CHCL

TCK Low Pulse Width

CLCH

TMS Input Setup Time

MVCH

TMS Input Hold Time

CHMX

TDI Input Setup Time

DVCH

TDI Input Hold Time

CHDX

SRAM Input Setup Time

SVCH

SRAM Input Hold Time

CHSX

Clock Low to Output Valid

CLQV

JTAG AC TEST CONDITIONS

Note: 1. See SRAM AC test output load on page 11.

Parameter

Symbol

Min

Unit

Note

Input High/Low Level

2.5/0.0

Input Rise/Fall Time

TR/TF

1.0/1.0

Input and Output Timing Reference Level

1.25

TCK

TMS

TDI

CHCH

MVCH

CHMX

CHCL

CLCH

DVCH

CHDX

CLQV

TDO

(SRAM)

SVCH

CHSX

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