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- 1 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

Document Title

512Kx36-bit,1Mx18-bit QDR

II b4 SRAM

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Revision History

Rev. No.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

1.0

2.0

3.0

3.1

Remark

Advance

Preliminary

Final

History

1. Initial document.

1. Change the Boundary scan exit order.
2. Correct the Overshoot and Undershoot timing diagram.

1. Change JTAG Block diagram

1. Add the speed bin (-25)

1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)

1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.

1. Add the power up/down sequencing comment.
2. Update the DC current parameter (Icc and Isb).
3. Change the Max. speed bin from -33 to -30.

1. Change the ISB1.

1. Final spec release

1. Delete the x8 Org.
2. Delete the 300MHz speed bin

1. Add the 300MHz speed bin

1. Change the stand-by current(I

SB1

)

before after
Isb1 -30 : 230 260
-25 : 210 240
-20 : 190 220
-16 : 170 200

Speed Bin

From

-30

200

230

-25

180

210

-20

160

190

-16

140

170

Draft Date

Oct. 17. 2002

Dec. 16, 2002

Dec. 26, 2002

Jan. 27, 2003

Mar. 20, 2003

April. 4, 2003

June. 20, 2003

Oct. 20. 2003

Oct. 31, 2003

Nov. 28, 2003

June. 18, 2004

July. 28, 2004

- 2 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

36 (or 18)

Q(Data Out)

(Echo Clock out)

CQ, CQ

512Kx36-bit, 1Mx18-bit QDR

II b4 SRAM

FEATURES

FUNCTIONAL BLOCK DIAGRAM

1.8V+0.1V/-0.1V Power Supply.

DLL circuitry for wide output data valid window and future

freguency scaling.

· I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,

1.8V+0.1V/-0.1V for 1.8V I/O

Separate independent read and write data ports

with concurrent read and write operation
· HSTL I/O
· Full data coherency, providing most current data .
· Synchronous pipeline read with self timed late write.
· Registered address, control and data input/output.
· DDR(Double Data Rate) Interface on read and write ports.
· Fixed 4-bit burst for both read and write operation.
· Clock-stop supports to reduce current.
·

Two input clocks(K and K) for accurate DDR timing at clock

rising edges only.

Two input clocks for output data(C and C) to minimize

clock-skew and flight-time mismatches.

Two echo clocks (CQ and CQ) to enhance output data

traceability.

Single address bus.

Byte write (x18, x36) function.

· Sepatate read/write control pin(R and W)
· Simple depth expansion with no data contention.
·

Programmable output impenance.

· JTAG 1149.1 compatible test access port.
· 165FBGA(11x15 ball array FBGA) with body size of 13x15mm

ADDRESS

D(Data in)

ADD
REG

DATA

REG

CLK

GEN

CTRL

LOGIC

512Kx36

(1Mx18)

MEMORY

ARRAY

WRITE DRIVER

K
K

36 (or 18)

SELECT OUTPUT CONTROL

SEN

SE A

/
RE

AD DE

OUT

DRIV

Notes: 1. Numbers in ( ) are for x18 device

17 (or 18)

4 (or 2)

72(or 36)

144

Organization

Part

Number

Cycle

Time

Access

Time

Unit

X36

K7R163684B-FC30

3.3

0.45

K7R163684B-FC25

4.0

0.45

K7R163684B-FC20

5.0

0.45

K7R163684B-FC16

6.0

0.50

X18

K7R161884B-FC30

3.3

0.45

K7R161884B-FC25

4.0

0.45

K7R161884B-FC20

5.0

0.45

K7R161884B-FC16

6.0

0.50

QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.

(or 18)

(or 36)

(or 72)

- 3 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

PIN CONFIGURATIONS

(TOP VIEW) K7R163684B(512Kx36)

Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 72Mb, 10A for 144Mb and 2A for 288Mb.
2. BW

controls write to D0:D8, BW

controls write to D9:D17, BW

controls write to D18:D26 and BW

controls write to D27:D35.

/SA*

NC/SA*

/SA*

Q27

Q18

D18

D17

Q17

D27

Q28

D19

D16

D28

D20

Q19

Q16

D15

Q29

D29

Q20

DDQ

Q15

Q30

Q21

D21

DDQ

D14

Q14

D30

D22

Q22

DDQ

Q13

D13

Doff

REF

DDQ

REF

D31

Q31

D23

DDQ

D12

Q32

D32

Q23

DDQ

Q12

Q33

Q24

D24

DDQ

D11

Q11

D33

Q34

D25

D10

D34

D26

Q25

Q10

Q35

D35

Q26

TDO

TCK

TMS

TDI

PIN NAME

Notes: 1. C, C, K or K cannot be set to V

REF

voltage.

2. When ZQ pin is directly connected to V

output impedance is set to minimum value

and it cannot be connected to ground or left unconnected.

3. Not connected to chip pad internally.

SYMBOL

PIN NUMBERS

DESCRIPTION

NOTE

K, K

6B, 6A

Input Clock

C, C

6P, 6R

Input Clock for Output Data

CQ, CQ

11A, 1A

Output Echo Clock

Doff

DLL Disable when low

4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

Address Inputs

D0-35

10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N

1C,1D,2E,1G,1J,2K,1M,1N,2P

Data Inputs

Q0-35

11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L

9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N

3P,1B,2C,1E,1F,2J,1K,1L,2M,1P

Data Outputs

Write Control Pin,active when low

Read Control Pin,active when low

, BW

7B,7A,5A,5B

Block Write Control Pin,active when low

REF

2H,10H

Input Reference Voltage

11H

Output Driver Impedance Control Input

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

Power Supply ( 1.8 V )

DDQ

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output Power Supply ( 1.5V or 1.8V )

2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,

8M,4N,8N

Ground

TMS

10R

JTAG Test Mode Select

TDI

11R

JTAG Test Data Input

TCK

JTAG Test Clock

TDO

JTAG Test Data Output

3A,6C,9A

No Connect

- 4 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

PIN CONFIGURATIONS

(TOP VIEW) K7R161884B(1Mx18)

Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb.
2. BW

controls write to D0:D8 and BW

controls write to D9:D17.

/SA*

D10

D11

Q10

Q11

DDQ

Q12

D12

DDQ

D13

Q13

DDQ

Doff

REF

DDQ

REF

D14

DDQ

Q14

DDQ

Q15

D15

DDQ

D16

D17

Q16

Q17

TDO

TCK

TMS

TDI

PIN NAME

Notes: 1. C, C, K or K cannot be set to V

REF

voltage.

2. When ZQ pin is directly connected to V

output impedance is set to minimum value

and it cannot be connected to ground or left unconnected.

3. Not connected to chip pad internally.

SYMBOL

PIN NUMBERS

DESCRIPTION

NOTE

K, K

6B, 6A

Input Clock

C, C

6P, 6R

Input Clock for Output Data

CQ, CQ

11A, 1A

Output Echo Clock

Doff

DLL Disable when low

3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

Address Inputs

D0-17

10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D

3F,2G,3J,3L,3M,2N

Data Inputs

Q0-17

11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E

2F,3G,3K,2L,3N,3P

Data Outputs

Write Control Pin,active when low

Read Control Pin,active when low

, BW

7B, 5A

Block Write Control Pin,active when low

REF

2H,10H

Input Reference Voltage

11H

Output Driver Impedance Control Input

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

Power Supply ( 1.8 V )

DDQ

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output Power Supply ( 1.5V or 1.8V )

2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N

Ground

TMS

10R

JTAG Test Mode Select

TDI

11R

JTAG Test Data Input

TCK

JTAG Test Clock

TDO

JTAG Test Data Output

3A,7A,1B,5B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E,1F

9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M

2M,9M,1N,9N,10N,1P,2P,9P

No Connect

- 5 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

The K7R163684B and K7R161884B are 18,874,368-bits QDR(Quad Data Rate)
Synchronous Pipelined Burst SRAMs.
They are organized as 524,288 words by 36bits for K7R163684B and 1,048,576 words by 18 bits for K7R161884B.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram
on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.
And totally independent read and write ports eliminate the need for high speed bus turn around.

Address for read and write are latched on alternate rising edges of the input clock K.
Data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 4-bit sequential for both read and write operations, reguiring tow full clock bus cycles.
Any request that attempts to interrupt a burst operation in progress is ignored.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW

and BW

( BW

and BW

3 )

pins.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.

The K7R163684B and K7R161884B are implemented with SAMSUNG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

GENERAL DESCRIPTION

Read Operations

Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.

For 4-bit burst DDR operation, it will access four 36-bit or 18-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
The process continues until all four data are transfered.

Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.

When the R is disabled after a read operation, the K7R163684B and K7R161884B will first complete
burst read operation
before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.

Echo clock operation

To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.

- 6 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with K clock.

For 4-bit burst DDR operation, it will write four 36-bit or 18-bit data words with each write command.
The first "late" data is transfered and registered in to the device synchronous with next K clock rising edge.
Next burst data is transfered and registered synchronous with following K clock rising edge.
The process continues until all four data are transfered and registered.

Continuous write operations are initated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks.

The device disregards input data presented on the same cycle W disabled.
When the W is disabled after a read operation, the K7R163684B and K7R161884B will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.

The K7R163684B and K7R161884B support byte write operations.
With activating BW

or BW

( BW

or BW

3 )

in write cycle, only one byte of input data is presented.

In K7R161884B, BW

controls write operation to D0:D8, BW

controls write operation to D9:D17.

And in K7R163684B BW

controls write operation to D18:D26, BW

controls write operation to D27:D35.

Write Operations

Depth Expansion

The K7R163684B and K7R161884B can be operated with the single clock pair K and K,
insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device can't change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.

Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently
and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.

The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V

through a precision resistor(RQ).

The value of RQ (within 15%) is five times the output impedance desired.

For example, 250

resistor will give an output impedance of 50

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs"
or other anomalous behavior in the SRAM.

There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up,
the SRAM needs 1024 non-read cycles.

Singel Clock Mode

Programmable Impedance Output Buffer Opration

The following power-up supply voltage application is recommended: V

, V

DDQ

, V

REF

, then V

. V

and V

DDQ

can be applied

simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

Power-Up/Power-Down Supply Voltage Sequencing

- 7 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

STATE DIAGRAM

Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case.
3. Read and write state machine can be active simulateneously.
4. State machine control timing sequence is controlled by K.

READ

DDR READ

D count=D count+1

POWER-UP

WRITE NOP

LOAD NEW

READ ADDRESS

D count=0

ALWAYS

WRITE

ALWAYS

READ

WRITE

READ
D count=2

INCREMENT

READ ADDRESS

READ NOP

INCREMENT

WRITE ADDRESS

DDR WRITE

D count=D count+1

LOAD NEW

WRITE ADDRESS

D count=0

ALWAYS

READ
D count=1

READ
D count=2

ALWAYS

WRITE
D count=2

WRITE
D count=1

WRITE
D count=2

- 8 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

WRITE TRUTH TABLE

(x18)

Notes: 1. X means "Don

t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (

3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.

OPERATION

WRITE ALL BYTEs ( K

)

WRITE ALL BYTEs ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 1 ( K

)

WRITE BYTE 1 ( K

)

WRITE NOTHING ( K

)

WRITE NOTHING ( K

)

WRITE TRUTH TABLE

(x36)

Notes: 1. X means "Don

t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (

3. Assumes a WRITE cycle was initiated.

OPERATION

WRITE ALL BYTEs ( K

)

WRITE ALL BYTEs ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 0 ( K

)

WRITE BYTE 1 ( K

)

WRITE BYTE 1 ( K

)

WRITE BYTE 2 and BYTE 3 ( K

)

WRITE BYTE 2 and BYTE 3 ( K

)

WRITE NOTHING ( K

)

WRITE NOTHING ( K

)

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

Notes: 1. X means "Don

t Care".

2. The rising edge of clock is symbolized by (

3. Before enter into clock stop status, all pending read and write operations will be completed.
4. This signal was HIGH on previous K clock rising edge. Initating consecutive READ or WRITE operations on consecutive K clock rising edges
is not permitted. The device will ignore the second request.
5. If this signal was LOW to inititate the previous cycle, this signal becomes a don

t care for this operation however it is strongly recommended

that this signal is brought HIGH as shown in the truth table.

OPERATION

D(A1)

D(A2)

D(A3)

D(A4)

Q(A1)

Q(A2)

Q(A3)

Q(A4)

Stopped

state

Clock Stop

High-Z

No Operation

OUT

at C(t+1)

OUT

at C(t+2)

OUT

at C(t+2)

OUT

at C(t+3)

Read

Din

at K(t+1)

Din

at K(t+1)

Din

at K(t+2)

Din

at K(t+2)

Write

- 9 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

DC ELECTRICAL CHARACTERISTICS

=1.8V

±0.1V, T

°C to +70°C)

Notes: 1. Minimum cycle. I

OUT

=0mA.

2. |I

|=(V

DDQ

/2)/(RQ/5)

±15% for 175 RQ 350.

3. |I

|=(V

DDQ

/2)/(RQ/5)

±15% for 175 RQ 350.

4. Minimum Impedance Mode when ZQ pin is connected to V

DDQ

5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.

8. These are DC test criteria. DC design criteria is V

REF

±50mV. The AC V

levels are defined separately for measuring

timing parameters.
9. V

(Min)DC=

0.3V, V

(Min)AC=-1.5V(pulse width

3ns).

10. V

(Max)DC=

DDQ

+0.3, V

(Max)AC=

DDQ

+0.85V(pulse width

3ns).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT NOTE

Input Leakage Current

=Max ; V

to V

DDQ

-2

µA

Output Leakage Current

Output Disabled,

-2

µA

Operating Current
(x36) : DDR

=Max , I

OUT

=0mA

Cycle Time

KHKH

Min

-30

550

1,5

-25

500

-20

450

-16

400

Operating Current
(x18) : DDR

=Max , I

OUT

=0mA

Cycle Time

KHKH

Min

-30

450

1,5

-25

400

-20

350

-16

300

Standby Current(NOP): DDR

SB1

Device deselected,
I

OUT

=0mA, f=Max,

All Inputs

0.2V or

-0.2V

-30

260

1,6

-25

240

-20

220

-16

200

Output High Voltage

OH1

DDQ

/2-0.12

DDQ

/2+0.12

2,7

Output Low Voltage

OL1

DDQ

/2-0.12

DDQ

/2+0.12

3,7

Output High Voltage

OH2

=-1.0mA

DDQ

-0.2

DDQ

Output Low Voltage

OL2

=1.0mA

0.2

Input Low Voltage

-0.3

REF

-0.1

8,9

Input High Voltage

REF

+0.1

DDQ

+0.3

8,10

ABSOLUTE MAXIMUM RATINGS*

*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V

DDQ

must not exceed V

during normal operation.

PARAMETER

SYMBOL

RATING

UNIT

Voltage on V

Supply Relative to V

-0.5 to 2.9

Voltage on V

DDQ

Supply Relative to V

DDQ

-0.5 to V

Voltage on Input Pin Relative to V

-0.5 to V

DD+

0.3

Storage Temperature

STG

-65 to 150

°C

Operating Temperature

OPR

0 to 70

°C

Storage Temperature Range Under Bias

BIAS

-10 to 85

°C

- 10 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

Note: For power-up, V

DDQ

+0.3V and V

1.7V and V

DDQ

1.4V t

200ms

DDQ

+0.5V

20% t

KHKH

(MIN)

-0.5V

20% t

KHKH

(MIN)

Undershoot Timing

Overershoot Timing

OPERATING CONDITIONS

°C T

70°C)

PARAMETER

SYMBOL

MIN

MAX

UNIT

Supply Voltage

1.7

1.9

DDQ

1.4

1.9

Reference

Voltage

REF

0.68

0.95

Ground

DDQ

SRAM

Zo=50

0.75V

REF

250

AC TEST OUTPUT LOAD

AC TEST CONDITIONS

Note: Parameters are tested with RQ=250

Parameter

Symbol

Value

Unit

Core Power Supply Voltage

1.7~1.9

Output Power Supply Voltage

DDQ

1.4~1.9

Input High/Low Level

1.25/0.25

Input Reference Level

REF

0.75

Input Rise/Fall Time

0.3/0.3

Output Timing Reference Level

DDQ

AC ELECTRICAL CHARACTERISTICS

=1.8V

±0.1V, T

°C to +70°C)

Notes: 1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transitioning edge of the input must :
a) Sustain a constant slew rate from the current AC level through the target AC level, V

IL(AC)

or V

IH(AC)

b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, V

IL(DC)

or V

IH(DC)

PARAMETER

SYMBOL

MIN

MAX

UNIT

NOTES

Input High Voltage

(AC)

REF

+ 0.2

1,2

Input Low Voltage

(AC)

REF

- 0.2

1,2

DDQ

+0.25V

-0.25V

- 11 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

AC TIMING CHARACTERISTICS

=1.8V

±0.1V, T

°C to +70°C)

Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW

,BW

and (NW

, NW

, for x8) and (BW

, BW

, also for x36)

3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX

is bigger than tCHQZ.

The specs as shown do not imply bus contention beacuse tCHQX

is a MIN parameter that is worst case at totally different test conditions

°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a

± 0.1 ns variation from echo clock to data.

The data sheet parameters reflect tester guardbands and test setup variations.

PARAMETER

SYMBOL

-30

-25

-20

-16

UNIT NOTE

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Clock

Clock Cycle Time (K, K, C, C)

KHKH

3.30

5.25

4.00

6.30

5.00

7.88

6.00

8.40

Clock Phase Jitter (K, K, C, C)

KC var

0.20

Clock High Time (K, K, C, C)

KHKL

1.32

1.60

2.00

2.40

Clock Low Time (K, K, C, C)

KLKH

1.32

1.60

2.00

2.40

Clock to Clock (K

K, C C)

KHKH

1.49

1.80

2.20

2.70

Clock to data clock (K

C, K C)

KHCH

0.00

1.45

0.00

1.80

0.00

2.30

0.00

2.80

DLL Lock Time (K, C)

KC lock

1024

cycle

K Static to DLL reset

KC reset

Output Times

C, C High to Output Valid

CHQV

0.45

0.50

C, C High to Output Hold

CHQX

-0.45

-0.50

C, C High to Echo Clock Valid

CHCQV

0.45

0.50

C, C High to Echo Clock Hold

CHCQX

-0.45

-0.50

CQ, CQ High to Output Valid

CQHQV

0.27

0.30

0.35

0.40

CQ, CQ High to Output Hold

CQHQX

-0.27

-0.30

-0.35

-0.40

C, High to Output High-Z

CHQZ

0.45

0.50

C, High to Output Low-Z

CHQX1

-0.45

-0.50

Setup Times

Address valid to K rising edge

AVKH

0.40

0.50

0.60

0.70

Control inputs valid to K rising edge

IVKH

0.40

0.50

0.60

0.70

Data-in valid to K, K rising edge

DVKH

0.30

0.35

0.40

0.50

Hold Times

K rising edge to address hold

KHAX

0.40

0.50

0.60

0.70

K rising edge to control inputs hold

KHIX

0.40

0.50

0.60

0.70

K, K rising edge to data-in hold

KHDX

0.30

0.35

0.40

0.50

- 12 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

APPLICATION INRORMATION

THERMAL RESISTANCE

Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. T

+ P

PRMETER

SYMBOL

TYP

Unit

NOTES

Junction to Ambient

17.1

°C

Junction to Case

3.3

°C

PIN CAPACITANCE

Note: 1. Parameters are tested with RQ=250

and V

DDQ

=1.5V.

2. Periodically sampled and not 100% tested.

PRMETER

SYMBOL

TESTCONDITION

TYP

MAX

Unit

NOTES

Address Control Input Capacitance

=0V

Input and Output Capacitance

OUT

=0V

Clock Capacitance

CLK

SRAM#1

SA R W BW

C C

SRAM#4

R=50

Vt=V

REF

R=250

RW BW

C C

Data In

Data Out

Address

Return CLK

Source CLK

Return CLK

Source CLK

MEMORY
CONTROLLER

ZQ R=250

SRAM1 Input CQ
SRAM1 Input CQ
SRAM4 Input CQ
SRAM4 Input CQ

- 13 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

KLKH

KHKH

KHKL

AVKH

KHAX

IVKH

KHIX

Q1-1

Q1-2

Q1-3

Q1-4

Q2-3

CHQX

KHCH

CHQV

CHQX

CQHQV

CQHQX

CHCQX

CHCQV

CHQV

CHCQX

CHCQV

KLKH

KHKH

KHKL

KHKH

Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.

2. Outputs are disabled one cycle after a NOP.

TIMING WAVE FORMS OF READ AND NOP

Don

t Care Undefined

Q2-1

Q2-2

D1-1

D1-2

D1-3

D1-4

D(Data In)

TIMING WAVE FORMS OF WRITE AND NOP

D2-1

D2-2

DVKH

KHDX

Don

t Care Undefined

Note: 1. D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1, i.e the next internal burst address following A1+0.

2. BWx ( NWx ) assumed active.

KLKH

KHKH

KHKL

AVKH

KHAX

IVKH

KHIX

D2-3

D2-4

KHIX

(Data Out)

Q2-4

CHQZ

READ

NOP

READ

WRITE

NOP

WRITE

- 15 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to V

to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to V

through a resistor. TDO should be left unconnected.

TAP Controller State Diagram

JTAG Block Diagram

Test Logic Reset

Run Test Idle

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

JTAG Instruction Coding

NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to V

when BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.

5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.

IR2 IR1 IR0

Instruction

TDO Output

Notes

EXTEST

Boundary Scan Register

IDCODE

Identification Register

SAMPLE-Z

Boundary Scan Register

RESERVED Do Not Use

SAMPLE

Boundary Scan Register

RESERVED Do Not Use

BYPASS

Bypass Register

SRAM
CORE

BYPASS Reg.
Identification Reg.
Instruction Reg.

Control Signals

TAP Controller

TDO

TDI

TMS

TCK

K,K

C,C

A,D

- 16 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

ID REGISTER DEFINITION

Note : Part Configuration
/def=001 for 18Mb, /wx=11 for x36, 10 for x18
/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O

Part

Revision Number

(31:29)

Part Configuration

(28:12)

Samsung JEDEC Code

(11: 1)

Start Bit(0)

512Kx36

000

00def0wx0t0q0b0s0

00001001110

1Mx18

000

00def0wx0t0q0b0s0

00001001110

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

ID Register

Boundary Scan

512Kx36

3 bits

1 bit

32 bits

107 bits

1Mx18

3 bits

1 bit

32 bits

107 bits

Note: 1. NC pins are read as "X" ( i.e. don

t care.)

ORDER

PIN ID

10D

10C

11D

11B

11C

10B

11A

Internal

ORDER

PIN ID

100

101

102

103

104

105

106

107

ORDER

PIN ID

11P

10P

10N

10M

11N

11L

11M

10L

11K

10K

10J

11J

11H

10G

11F

11G

10F

11E

10E

BOUNDARY SCAN EXIT ORDER

- 17 -

Rev 3.1

July. 2004

512Kx36 & 1Mx18 QDR

II b4 SRAM

K7R163684B

K7R161884B

JTAG DC OPERATING CONDITIONS

Note: 1. The input level of SRAM pin is to follow the SRAM DC specification

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

1.7

1.8

1.9

Input High Level

1.3

+0.3

Input Low Level

-0.3

0.5

Output High Voltage(I

=-2mA)

1.4

Output Low Voltage(I

=2mA)

0.4

JTAG TIMING DIAGRAM

JTAG AC Characteristics

Parameter

Symbol

Min

Max

Unit

Note

TCK Cycle Time

CHCH

TCK High Pulse Width

CHCL

TCK Low Pulse Width

CLCH

TMS Input Setup Time

MVCH

TMS Input Hold Time

CHMX

TDI Input Setup Time

DVCH

TDI Input Hold Time

CHDX

SRAM Input Setup Time

SVCH

SRAM Input Hold Time

CHSX

Clock Low to Output Valid

CLQV

JTAG AC TEST CONDITIONS

Note: 1. See SRAM AC test output load on page 11.

Parameter

Symbol

Min

Unit

Note

Input High/Low Level

1.8/0.0

Input Rise/Fall Time

TR/TF

1.0/1.0

Input and Output Timing Reference Level

0.9

TCK

TMS

TDI

CHCH

MVCH

CHMX

CHCL

CLCH

DVCH

CHDX

CLQV

TDO

(SRAM)

SVCH

CHSX

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