FLASH MEMORY
1
K9F2G08U0M
K9K4G08U1M
K9XXG08UXM
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FLASH MEMORY
2
K9F2G08U0M
K9K4G08U1M
Document Title
256M x 8 Bit / 512M x 8 Bit NAND Flash Memory
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
Revision No
0.0
0.1
0.2
0.3
0.4
Remark
Advance
Preliminary
Preliminary
Preliminary
Preliminary
History
1. Initial issue
1. Add the Rp vs tr ,tf & Rp vs Ibusy graph for 1.8V device (Page 34)
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 35)
The min. Vcc value 1.8V devices is changed.
K9F2GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V
Few current value is changed.
Before Unit : us
After
1. The 3rd Byte ID after 90h ID read command is don't cared.
The 5th Byte ID after 90h ID read command is deleted.
2. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
3. Pb-free Package is added.
K9F2G08Q0M-PCB0,PIB0
K9F2G08U0M-PCB0,PIB0
K9F2G16U0M-PCB0,PIB0
K9F2G16Q0M-PCB0,PIB0
K9F2GXXQ0M
K9F2GXXU0M
Typ.
Max.
Typ.
Max.
I
SB
2
20
100
20
100
I
LI
-
20
-
20
I
LO
-
20
-
20
K9F2GXXQ0M
K9F2GXXU0M
Typ.
Max.
Typ.
Max.
I
SB
2
10
50
10
50
I
LI
-
10
-
10
I
LO
-
10
-
10
Draft Date
Sep. 19.2001
Nov. 22. 2002
Mar. 6.2003
Apr. 2. 2003
Apr. 9. 2003
FLASH MEMORY
3
K9F2G08U0M
K9K4G08U1M
Document Title
256M x 8 Bit / 512M x 8 Bit NAND Flash Memory
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
Revision No
0.5
0.6
0.7
Remark
Preliminary
Preliminary
Preliminary
History
1. The value of AC parameters for K9F2G08U0M are changed.
2. The definition and value of setup and hold time are changed.
3. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns (Page 11, 22~25)
-
tADL is the time from the WE rising edge of final address cycle
to the WE rising edge of first data cycle at program operation.
4. Added addressing method for program operation
1. PKG(TSOP1, WSOP1) Dimension Change
1. Technical note is changed
2. Notes of the AC timing characteristics are added
3. The description of Copy-back program is changed
4. 52ULGA Package is added
ITEM
K9F2G08U0M
Before
After
t
WC
45
30
t
WP
25
15
t
WH
15
10
t
RC
50
30
t
RP
25
15
t
REH
15
10
t
REA
30
18
t
CEA
45
23
t
ADL
-
100
ITEM
K9F2G16U0M
K9F2GXXQ0M
K9F2G08U0M
t
CLS
25
10
t
CLH
10
5
t
CS
35
15
t
CH
10
5
t
ALS
25
10
t
ALH
10
5
t
DS
20
10
t
DH
10
5
Draft Date
Apr. 22.2004
May. 19. 2004
Jan. 21. 2005
FLASH MEMORY
4
K9F2G08U0M
K9K4G08U1M
Document Title
256M x 8 Bit / 512M x 8 Bit NAND Flash Memory
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
Revision No
0.8
0.9
1.0
1.1
1.2
Remark
Preliminary
History
1. CE access time : 23ns->35ns (p.13)
1. The value of tREA for 3.3V device is changed.(18ns->20ns)
2. EDO mode is added.
1. The flow chart to creat the initial invalid block table is changed.
1. LGA package for 2Gb mono is added
1. x16 device is removed
Draft Date
Feb. 14. 2005
May 4 2005
May 6 2005
Oct. 20 2005
Oct. 31 2005
FLASH MEMORY
5
K9F2G08U0M
K9K4G08U1M
GENERAL DESCRIPTION
FEATURES
Voltage Supply
-2.7 V ~3.6 V
Organization
- Memory Cell Array
-(256M + 8,192K)bit x 8bit
- Data Register
-(2K + 64)bit x8bit
- Cache Register
-(2K + 64)bit x8bit
Automatic Program and Erase
- Page Program
-(2K + 64)Byte
- Block Erase
-(128K + 4K)Byte
Page Read Operation
- Page Size
- 2K-Byte
- Random Read : 25
s(Max.)
- Serial Access : 30ns(Min.)
256M x 8 Bit / 512M x 8 Bit NAND Flash Memory
Fast Write Cycle Time
- Page Program time : 200
s(Typ.)
- Block Erase Time : 2ms(Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Command Register Operation
Cache Program Operation for High Performance Program
Power-On Auto-Read Operation
Intelligent Copy-Back Operation
Unique ID for Copyright Protection
Package :
- K9F2G08U0M-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F2G08U0M-PCB0/PIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F2G08U0M-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 1.0 mm pitch)
- K9K4G08U1M-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 1.0 mm pitch)
Offered in 256Mx8bit, the K9F2G08U0M is 2G bit with spare 64M bit capacity. Its NAND cell provides the most cost-effective solution
for the solid state mass storage market. A program operation can be performed in typical 200
s on the 2112-byte page and an erase
operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 30ns cycle time per byte.
The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates
all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the
write-intensive systems can take advantage of the K9F2G08U0M
s extended reliability of 100K program/erase cycles by providing
ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2G08U0M is an optimum solution for large nonvolatile
storage applications such as solid state file storage and other portable applications requiring non-volatility.
PRODUCT LIST
Part Number
Vcc Range
Organization
PKG Type
K9F2G08U0M-Y,P
2.7 ~ 3.6V
X8
TSOP1
K9F2G08U0M-I
52ULGA
K9K4G08U1M-I
FLASH MEMORY
6
K9F2G08U0M
K9K4G08U1M
PIN CONFIGURATION (TSOP1)
K9F2G08U0M-YCB0,PCB0/YIB0,PIB0
48-pin TSOP1
Standard Type
12mm x 20mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
PRE
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
0.787
0.008
20.00
0.20
#1
#24
0.1
6
+0.
0
7
-0
.
0
3
0.
00
8
+0.
003
-
0
.001
0.
50
0.
0197
#48
#25
0.
488
12
.40
MAX
12
.00
0.
472
0.1
0
0.
004
MAX
0.2
5
0.
010
()
0.039
0.002
1.00
0.05
0.002
0.05
MIN
0.047
1.20
MAX
0.45~0.75
0.018~0.030
0.724
0.004
18.40
0.10
0~8
0.
010
0.2
5
TYP
0.
125
+0
.
0
75
0.0
3
5
0.
00
5
+0
.
0
0
3
-0
.0
0
1
0.50
0.020
(
)
0.
20
+0.
0
7
-0
.
0
3
FLASH MEMORY
7
K9F2G08U0M
K9K4G08U1M
1.00
1.00
1.00
1.00
2.00
7 6 5 4 3 2 1
1.
00
1.0
0
1.0
0
12.00
0.10
#A1
17.
00
0.
10
17
.00
0.1
0
B
A
12.00
0.10
(Datum B)
(Datum A)
12.
0
0
10.00
2.
50
2.
50
2.
00
0.5
0
1.
30
A
B
C
D
E
F
G
H
J
K
L
M
N
12-
1.000.05
41-
0.70
0.05
Side View
0.
65
(
Max
.)
0.10 C
17.00
0.10
Top View
Bottom View
A
B
C
D E
F
G
H J
K
L
M
N
7
6
5
4
3
2
1
PIN CONFIGURATION (ULGA)
K9F2G08U0M-ICB0/IIB0
52-ULGA (measured in millimeters)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vcc
Vcc
Vss
Vss
Vss
/RE
NC
/CE
NC
CLE
NC
ALE
NC
/WE
NC
/WP
NC
R/B
NC
Vss
IO0
NC
IO1
NC
IO2
IO3
NC
NC
IO4
NC
IO5
NC
IO6
NC
IO7
NC
AB
C
M
0.1
AB
C
M
0.1
PACKAGE DIMENSIONS
FLASH MEMORY
8
K9F2G08U0M
K9K4G08U1M
1.00
1.00
1.00
1.00
2.00
7 6 5 4 3 2 1
1.
00
1.0
0
1.0
0
12.00
0.10
#A1
17.
00
0.
10
17
.00
0.1
0
B
A
12.00
0.10
(Datum B)
(Datum A)
12.
0
0
10.00
2.
50
2.
50
2.
00
0.5
0
1.
30
A
B
C
D
E
F
G
H
J
K
L
M
N
12-
1.000.05
41-
0.70
0.05
Side View
0.
65
(
Max
.)
0.10 C
17.00
0.10
Top View
Bottom View
A
B
C
D E
F
G
H J
K
L
M
N
7
6
5
4
3
2
1
PIN CONFIGURATION (ULGA)
K9K4G08U1M - ICB0/IIB0
52-ULGA (measured in millimeters)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vcc
Vcc
Vss
Vss
Vss
/RE1
/RE2
/CE1
/CE2
CLE1
CLE2
ALE1
ALE2
/WE1
/WE2
/WP1
/WP2
/RB1
/RB2
Vss
IO0-1
IO0-2
IO1-1
IO1-2
IO2-1
IO3-1
IO2-2
IO3-2
IO4-1
IO4-2
IO5-1
IO5-2
IO6-1
IO6-2
IO7-1
IO7-2
AB
C
M
0.1
AB
C
M
0.1
PACKAGE DIMENSIONS
FLASH MEMORY
9
K9F2G08U0M
K9K4G08U1M
PIN DESCRIPTION
NOTE : Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
Pin Name
Pin Function
I/O
0
~ I/O
7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to 'Page read' section of Device operation .
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
PRE
POWER-ON READ ENABLE
The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when
PRE pin is tied to Vcc.
Vcc
POWER
V
CC
is the power supply for device.
Vss
GROUND
N.C
NO CONNECTION
Lead is not internally connected.
FLASH MEMORY
10
K9F2G08U0M
K9K4G08U1M
2K Bytes
64 Bytes
Figure 1-1. K9F2G08U0M Functional Block Diagram
Figure 2-1. K9F2G08U0M Array Organization
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
2nd Cycle
A
8
A
9
A
10
A
11
*L
*L
*L
*L
3rd Cycle
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
4th Cycle
A
20
A
21
A
22
A
23
A
24
A
25
A
26
A
27
5th Cycle
A
28
*L
*L
*L
*L
*L
*L
*L
V
CC
X-Buffers
Command
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
V
SS
A
12
- A
28
A
0
- A
11
Command
CE
RE
WE
CLE
WP
I/0 0
I/0 7
V
CC
V
SS
128K Pages
(=2,048 Blocks)
2K Bytes
8 bit
64 Bytes
1 Block = 64 Pages
(128K + 4k) Byte
I/O 0 ~ I/O 7
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 2048 Blocks
= 2112 Mbits
Row Address
Page Register
ALE PRE
2048M + 64M Bit
NAND Flash
ARRAY
(2048 + 64)Byte x 131072
Y-Gating
Cache Register
Row Address
Column Address
Column Address
Data Register & S/A
Row Address
FLASH MEMORY
11
K9F2G08U0M
K9K4G08U1M
Product Introduction
The K9F2G08U0M is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8 columns. Spare 64 col-
umns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially con-
nected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer
between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells
that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND
structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read oper-
ations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 sep-
arately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F2G08U0M.
The K9F2G08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 264M byte physical space
requires 29 addresses, thereby requiring five cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-
ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the
command register. Table 1 defines the specific commands of the K9F2G08U0M.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers
are being programmed into memory cells in cache program mode. The program performance may be dramatically improved by cache
program when there are lots of pages of data to be programmed.
The device embodies power-on auto-read feature which enables serial access of data of the 1st page without command and address
input after power-on.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
NOTE : 1. Random Data Input/Output can be executed in a page.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 00h
30h
Read for Copy Back
00h
35h
Read ID
90h
-
Reset
FFh
-
O
Page Program
80h
10h
Cache Program
80h
15h
Copy-Back Program
85h
10h
Block Erase
60h
D0h
Random Data Input
*
85h
-
Random Data Output
*
05h
E0h
Read Status
70h
O
FLASH MEMORY
12
K9F2G08U0M
K9K4G08U1M
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
NOTE : V
IL
can undershoot to -0.4V and V
IH
can overshoot to V
CC
+0.4V for durations of 20 ns or less.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Operating
Current
Page Read with Serial
Access
I
CC
1
tRC=30ns, CE=V
IL
I
OUT
=0mA
-
15
30
mA
Program
I
CC
2
-
Erase
I
CC
3
-
Stand-by Current(TTL)
I
SB
1
CE=V
IH
, WP=PRE=0V/V
CC
-
-
1
Stand-by Current(CMOS)
I
SB
2
CE=V
CC
-0.2,
WP=PRE=0V/V
CC
-
10
50
A
Input Leakage Current
I
LI
V
IN
=0 to Vcc(max)
-
-
10
Output Leakage Current
I
LO
V
OUT
=0 to Vcc(max)
-
-
10
Input High Voltage
V
IH*
-
0.8xVcc
-
Vcc+0.3
V
Input Low Voltage, All inputs
V
IL*
-
-0.3
-
0.2xVcc
Output High Voltage Level
V
OH
K9F2G08U0M :I
OH
=-400
A
2.4
-
-
Output Low Voltage Level
V
OL
K9F2G08U0M :I
OL
=2.1mA
-
-
0.4
Output Low Current(R/B)
I
OL
(R/B)
K9F2G08U0M :V
OL
=0.4V
8
10
-
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F2G08U0M-XCB0
:
T
A
=0 to 70
C, K9F2G08U0M-XIB0
:
T
A
=-40 to 85
C)
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
V
CC
2.7
3.3
3.6
V
Supply Voltage
V
SS
0
0
0
V
ABSOLUTE MAXIMUM RATINGS
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V
CC,
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN/OUT
-0.6 to + 4.6
V
V
CC
-0.6 to + 4.6
Temperature Under Bias
K9F2G08U0M-XCB0
T
BIAS
-10 to +125
C
K9F2G08U0M-XIB0
-40 to +125
Storage Temperature
K9F2G08U0M-XCB0
T
STG
-65 to +150
C
K9F2G08U0M-XIB0
Short Circuit Current
Ios
5
mA
FLASH MEMORY
13
K9F2G08U0M
K9K4G08U1M
CAPACITANCE
(
T
A
=25
C, V
CC
=3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
VALID BLOCK
NOTE :
1. The
device
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
. Do not erase or pro-
gram factory-marked bad blocks.
Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
2,008
-
2,048
Blocks
AC TEST CONDITION
(K9F2G08U0M-XCB0 :TA=0 to 70
C, K9F2G08U0M-XIB0:TA=-40 to 85C
K9F2G08U0M : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F2G08U0M
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load
1 TTL GATE and CL=50pF
Program / Erase Characteristics
NOTE : 1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25
C
2. Max. time of
t
CBSY
depends on timing between internal program completion and data in
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
*1
-
200
700
s
Dummy Busy Time for Cache Program
t
CBSY
*2
3
700
s
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
-
4
cycles
Spare Array
-
-
4
cycles
Block Erase Time
t
BERS
-
2
3
ms
MODE SELECTION
NOTE : 1. X can be V
IL
or V
IH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
PRE
Mode
H
L
L
H
X
X
Read Mode
Command Input
L
H
L
H
X
X
Address Input(5clock)
H
L
L
H
H
X
Write Mode
Command Input
L
H
L
H
H
X
Address Input(5clock)
L
L
L
H
H
X
Data Input
L
L
L
H
X
X
Data Output
X
X
X
X
H
X
X
During Read(Busy)
X
X
X
X
X
H
X
During Program(Busy)
X
X
X
X
X
H
X
During Erase(Busy)
X
X
*1
X
X
X
L
X
Write Protect
X
X
H
X
X
0V/V
CC
*2
0V/V
CC
*2
Stand-by
FLASH MEMORY
14
K9F2G08U0M
K9K4G08U1M
AC Characteristics for Operation
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. For cache program operation, the whole AC Charcateristics must be same as that of K9F2G08U0M*.
Parameter
Symbol
Min
Max
Unit
K9F2G08U0M*
K9F2G08U0M
K9F2G08U0M*
K9F2G08U0M
Data Transfer from Cell to Register
t
R
-
-
25
25
s
ALE to RE Delay
t
AR
10
10
10
-
ns
CLE to RE Delay
t
CLR
10
10
-
-
ns
Ready to RE Low
t
RR
20
20
-
-
ns
RE Pulse Width
t
RP
25
15
-
-
ns
WE High to Busy
t
WB
-
-
100
100
ns
Read Cycle Time
t
RC
50
30
-
-
ns
RE Access Time
t
REA
-
-
30
20
ns
CE Access Time
t
CEA
-
-
45
35
ns
RE High to Output Hi-Z
t
RHZ
-
-
30
30
ns
CE High to Output Hi-Z
t
CHZ
-
-
20
20
ns
RE or CE High to Output hold
t
OH
15
15
-
-
ns
RE High Hold Time
t
REH
15
10
-
-
ns
Output Hi-Z to RE Low
t
IR
0
0
-
-
ns
RE High to WE Low
t
RHW
100
100
-
-
ns
WE High to RE Low
t
WHR
60
60
-
-
ns
Device Resetting Time
(Read/Program/Erase)
t
RST
-
-
5/10/500
*1
5/10/500
*1
s
AC Timing Characteristics for Command / Address / Data Input
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
3. For cache program operation, the whole AC Charcateristics must be same as that of K9F2G08U0M*.
Parameter
Symbol
Min
Max
Unit
K9F2G08U0M*
K9F2G08U0M
K9F2G08U0M*
K9F2G08U0M
CLE setup Time
t
CLS
*1
25
15
-
-
ns
CLE Hold Time
t
CLH
10
5
-
-
ns
CE setup Time
t
CS
*1
35
20
-
-
ns
CE Hold Time
t
CH
10
5
-
-
ns
WE Pulse Width
t
WP
25
15
-
-
ns
ALE setup Time
t
ALS
*1
25
15
-
-
ns
ALE Hold Time
t
ALH
10
5
-
-
ns
Data setup Time
t
DS
*1
20
15
-
-
ns
Data Hold Time
t
DH
10
5
-
-
ns
Write Cycle Time
t
WC
45
30
-
-
ns
WE High Hold Time
t
WH
15
10
-
-
ns
ALE to Data Loading Time
t
ADL
*2
100
100
-
-
ns
FLASH MEMORY
15
K9F2G08U0M
K9K4G08U1M
NAND Flash Technical Notes
Identifying Initial Invalid Block(s)
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The
information regarding the initial invalid block(s) is so called as the invalid block information. Devices with initial invalid block(s) have
the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does
not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor.
The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h
block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial
invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most
cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial
invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following sug-
gested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.
*
Check "FFh( or FFFFh)" at the column address
Figure 3. Flow chart to create initial invalid block table.
Start
Set Block Address = 0
Check "FFh
Increment Block Address
Last Block ?
End
No
Yes
Yes
Create (or update)
No
Initial Invalid Block(s) Table
2048 of the 1st and 2nd page in the block
or FFFFh" ?
FLASH MEMORY
16
K9F2G08U0M
K9K4G08U1M
NAND Flash Technical Notes
(Continued)
Program Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
Program Completed
or R/B = 1 ?
Program Error
Yes
No
Yes
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block
failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status
read failure after erase or program, block replacement should be done. Because program status fail during a page program does not
affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an
erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC
must be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should
be reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those
reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Write
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read
Single Bit Failure
Verify ECC -> ECC Correction
ECC
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
: If program operation results in an error, map out
the block including the page in error and copy the
*
target data to another block.
FLASH MEMORY
17
K9F2G08U0M
K9K4G08U1M
Erase Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 60h
Write Block Address
Write D0h
Read Status Register
or R/B = 1 ?
Erase Error
Yes
No
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Erase Completed
Yes
Read Flow Chart
Start
Verify ECC
No
Write 00h
Write Address
Read Data
ECC Generation
Reclaim the Error
Page Read Completed
Yes
NAND Flash Technical Notes
(Continued)
Write 30h
Block Replacement
* Step1
When an error happens in the nth page of the Block 'A' during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B')
* Step3
Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'.
* Step4
Do not erase or program to Block 'A' by creating an 'invalid Block' table or other appropriate scheme.
Buffer memory of the controller.
1st
Block A
Block B
(n-1)th
nth
(page)
{
1st
(n-1)th
nth
(page)
{
an error occurs.
1
2
FLASH MEMORY
18
K9F2G08U0M
K9K4G08U1M
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-
nificant bit) pages of the block. Random page address programming is prohibited.
From the LSB page to MSB page
DATA IN: Data (1)
Data (64)
(1)
(2)
(3)
(32)
(64)
Data register
Page 0
Page 1
Page 2
Page 31
Page 63
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (64)
(2)
(32)
(3)
(1)
(64)
Data register
Page 0
Page 1
Page 2
Page 31
Page 63
NAND Flash Technical Notes
(Continued)
Addressing for program operation
:
:
:
:
FLASH MEMORY
19
K9F2G08U0M
K9K4G08U1M
System Interface Using CE don't-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial access
would provide significant savings in power consumption.
Figure 4. Program Operation with CE don't-care.
CE
WE
t
WP
t
CH
t
CS
Address(5Cycles)
80h
Data Input
CE
CLE
ALE
WE
Data Input
CE don't-care
10h
Address(5Cycle)
00h
CE
CLE
ALE
WE
Data Output(serial access)
CE don't-care
R/B
t
R
RE
t
CEA
out
t
REA
CE
RE
I/O
0
~
7
Figure 5. Read Operation with CE don't-care.
30h
I/Ox
I/Ox
FLASH MEMORY
20
K9F2G08U0M
K9K4G08U1M
Command Latch Cycle
CE
WE
CLE
ALE
Command
Address Latch Cycle
t
CLS
t
CS
t
CLH
t
CH
t
WP
t
ALS
t
ALH
t
DS
t
DH
NOTE
Device
I/O
DATA
ADDRESS
I/Ox
Data In/Out
Col. Add1
Col. Add2
Row Add1
Row Add2
Row Add3
K9F2G08U0M
I/O 0 ~ I/O 7
~2112byte
A0~A7
A8~A11
A12~A19
A20~A27
A28
I/Ox
CE
WE
CLE
ALE
Col. Add1
t
CS
t
WC
t
WP
t
ALS
t
DS
t
DH
t
ALH
t
ALS
t
WH
t
WC
t
WP
t
DS
t
DH
t
ALH
t
ALS
t
WH
t
WC
t
WP
t
DS
t
DH
t
ALH
t
ALS
t
WH
t
DS
t
DH
t
WP
I/Ox
Col. Add2
Row Add1
Row Add2
t
WC
t
WH
t
ALH
t
ALS
t
DS
t
DH
Row Add3
t
ALH
t
CLS
FLASH MEMORY
21
K9F2G08U0M
K9K4G08U1M
Input Data Latch Cycle
CE
CLE
WE
DIN 0
DIN 1
DIN final*
ALE
t
CLH
t
WC
t
CH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
WP
t
WH
t
WP
t
WP
I/Ox
NOTES : DIN final means 2112
RE
CE
R/B
I/Ox
t
RR
t
CEA
t
REA
t
RP
t
REH
t
REA
t
RC
t
RHZ*
t
REA
Dout
t
OH
Dout
Dout
t
OH
t
RHZ*
t
CHZ*
Serial Access Cycle after Read
(CLE=L, WE=H, ALE=L)
NOTES : Transition is measured
200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
t
ALS
FLASH MEMORY
22
K9F2G08U0M
K9K4G08U1M
RE
CE
R/B
I/Ox
t
RR
t
CEA
t
REA
t
RP
t
REH
t
REA
t
RC
t
RHZ*
t
REA
Dout
t
OH
Dout
Dout
t
OH
t
RHZ*
t
CHZ*
Serial Access Cycle after Read
(CLE=L, WE=H, ALE=L)
NOTES : Transition is measured
200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
RE
CE
R/B
I/Ox
t
RR
t
CEA
t
REA
t
RP
t
REH
t
REA
t
RC
t
RHZ*
t
REA
Dout
t
OH
Dout
Dout
t
OH
t
RHZ*
t
CHZ*
Serial Access Cycle after Read
(CLE=L, WE=H, ALE=L)
NOTES : Transition is measured
200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
FLASH MEMORY
23
K9F2G08U0M
K9K4G08U1M
Status Read Cycle
CE
WE
CLE
RE
70h
Status Output
t
CLR
t
CLH
t
WP
t
CH
t
DS
t
DH
t
REA
t
IR*
t
OH
t
OH
t
WHR
t
CEA
t
CLS
I/Ox
t
CHZ*
t
RHZ*
t
CS
FLASH MEMORY
24
K9F2G08U0M
K9K4G08U1M
Read Operation
(Intercepted by CE)
CE
CLE
R/B
WE
ALE
RE
Busy
00h
Dout N
Dout N+1
Dout N+2
Row Address
Column Address
t
WB
t
AR
t
CHZ
t
R
t
RR
t
RC
30h
Read Operation
CE
CLE
R/B
WE
ALE
RE
Busy
00h
Col. Add1
Col. Add2
Row Add1
Dout N
Dout N+1
Column Address
Row Address
t
WB
t
AR
t
R
t
RC
t
RHZ
t
RR
Dout M
t
WC
Row Add2
30h
t
CLR
I/Ox
I/Ox
Col. Add1
Col. Add2 Row Add1
Row Add2
Row Add3
Row Add3
t
OH
FLASH MEMORY
25
K9F2G08U0M
K9K4G08U1M
Ra
ndom Dat
a
Outpu
t
In a Page
CE
CLE
R/B
WE
ALE
RE
Busy
00h
Dout
N
D
out
N
+
1
Ro
w Addr
ess
Co
lumn
Addr
ess
t
W
B
t
AR
t
R
t
RR
t
R
C
30h
05h
Column Add
r
ess
Do
u
t
M
Do
u
t
M+
1
I
/Ox
C
o
l
.
A
dd1
Co
l
.
A
d
d
2
Ro
w Ad
d
1
Ro
w Ad
d2
C
o
l A
dd1
Co
l Ad
d2
Row Add
3
t
CLR
E0
h
t
WHR
t
REA
FLASH MEMORY
26
K9F2G08U0M
K9K4G08U1M
m = 2112byte
Page Program Operation
CE
CLE
R/B
WE
ALE
RE
80h
70h
I/O
0
Din
N
Din
10h
M
SerialData
Input Command Column Address
Row Address
1 up to m Byte
Serial Input
Program
Command
Read Status
Command
I/O
0
=0 Successful Program
I/O
0
=1 Error in Program
t
PROG
t
WB
t
WC
t
WC
t
WC
I/Ox
Co.l Add1 Col. Add2
Row Add1 Row Add2 Row Add3
t
ADL
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
FLASH MEMORY
27
K9F2G08U0M
K9K4G08U1M
Pa
ge Program Operation with Rand
om Dat
a
In
put
CE
CLE
R/B
WE
ALE
RE
80
h
70
h
I/O
0
Di
n
N
Di
n
10h
M
Se
ri
al
D
a
ta
I
npu
t Command
Col
u
mn A
ddr
ess
R
ow
Addr
ess
Seri
al
Inp
u
t
Pr
ogr
am
Co
mm
a
n
d
Re
ad Stat
us
Co
m
m
a
n
d
t
PR
O
G
t
WB
t
WC
t
WC
85
h
Random Dat
a
Inp
u
t Command
Co
lu
m
n
Ad
dres
s
t
WC
Din
J
Di
n
K
Ser
i
al
I
nput
I
/Ox
Col
.
A
dd1
Col
.
A
dd2
Row Add1
Row Add2
Col
.
A
dd1
Col
.
A
dd2
Row A
d
d
3
t
ADL
NOTES
:
t
A
D
L
is t
h
e
t
i
m
e
fr
o
m
t
h
e
WE
r
i
sing edg
e
o
f
fi
nal add
ress
cycl
e
t
o
th
e WE
rising edg
e
o
f
f
i
rst dat
a cycle
.
t
ADL
FLASH MEMORY
28
K9F2G08U0M
K9K4G08U1M
Co
py-Back Program
Operatio
n W
i
th Random
Da
t
a
Input
CE
CLE
R/B
WE
ALE
RE
00
h
70
h
I/
O
0
85h
Colu
m
n
A
d
dr
ess
Ro
w
Ad
dr
es
s
Re
ad S
t
at
us
Co
mm
a
n
d
I/O
0
=
0
Succe
ssf
ul
Pr
og
ra
m
I/O
0
=1
Er
ro
r
i
n
Pro
g
r
a
m
t
PROG
t
WB
t
WC
Busy
t
WB
t
R
Busy
10
h
Co
py-
B
ac
k Da
ta
In
pu
t Co
mm
a
n
d
35
h
Co
lum
n
A
d
dr
es
s
Ro
w Ad
dres
s
D
a
ta
1
Da
ta
N
I/O
x
Co
l
A
d
d
1
Co
l
A
d
d
2
Ro
w A
d
d
1
Ro
w A
d
d
2
Co
l
A
d
d
1
Co
l
A
d
d
2
Ro
w A
d
d
1
Ro
w A
d
d
2
Ro
w A
d
d
3
Ro
w A
d
d
3
t
ADL
NOTES
:
t
A
D
L
is t
h
e
t
i
m
e
fr
o
m
t
h
e
WE
r
i
sing edg
e
o
f
fi
nal add
ress
cycl
e
t
o
th
e WE
rising edg
e
o
f
f
i
rst dat
a cycle
.
FLASH MEMORY
29
K9F2G08U0M
K9K4G08U1M
Cach
e Pro
g
ra
m Operation
(a
va
i
l
a
b
l
e
on
l
y
w
i
t
h
i
n a bl
o
ck)
CE
CLE
R/B
WE
ALE
RE
80
h
Di
n N
Di
n
15
h
M
S
e
r
i
al Data
I
n
put Co
m
m
and
C
o
l
u
mn A
d
dr
es
s
Ser
i
al I
n
put
P
r
ogra
m
Max.
63 ti
mes re
peat
abl
e
tC
BS
Y
tW
B
tW
C
C
o
mma
nd
L
a
st
Pa
ge
In
put
&
Pr
ogr
am
t
CBSY
:
ma
x. 7
0
0
u
s
(D
u
m
m
y
)
Di
n N
Di
n
10h
tCPROG
tW
B
I/
O
80h
Col
Add
1
,2 &
Row
Ad
d1,2
R/B
Da
ta
A
ddress &
Data
I
npu
t
15
h
80
h
A
d
dr
e
s
s
&
Da
ta
I
n
p
u
t
15h
80
h
Addr
ess &
Da
ta
I
n
p
u
t
15h
80
h
Addr
ess &
Da
ta
I
n
pu
t
10h
Ex.) Cach
e Pro
g
ra
m
t
CBS
Y
t
CBS
Y
t
CBSY
t
PRO
G
P
r
ogr
am Con
f
i
r
m
C
o
mma
nd
(Tr
ue)
80
h
70
h
70
h
M
R
o
w A
ddress
I
/Ox
I/O
x
C
o
l
Add1
Col
Add2
Row A
dd1
Row A
dd2
Col
Add1
Col
A
d
d2
Ro
w
A
d
d
1
Row A
d
d2
Ro
w A
d
d
3
Ro
w A
d
d
3
tA
D
L
tADL
NOTES
:
t
A
D
L
is t
h
e
t
i
m
e
fr
o
m
t
h
e
WE
r
i
sing edg
e
o
f
fi
nal add
ress
cycl
e
t
o
th
e WE
rising edg
e
o
f
f
i
rst dat
a cycle
.
FLASH MEMORY
30
K9F2G08U0M
K9K4G08U1M
BLOCK ERASE OPERATION
CE
CLE
R/B
WE
ALE
RE
60h
Erase Command
Read Status
Command
I/O
0
=1 Error in Erase
D0h
70h
I/O 0
Busy
t
WB
t
BERS
I/O
0
=0 Successful Erase
Row Address
t
WC
Auto Block Erase
Setup Command
I/Ox
Row Add1 Row Add2 Row Add3
FLASH MEMORY
31
K9F2G08U0M
K9K4G08U1M
Read ID Operation
CE
CLE
WE
ALE
RE
90h
Read ID Command
Maker Code Device Code
00h
ECh
Device
t
REA
Address. 1cycle
80h
4th cyc.*
ID Definition Table
90 ID : Access command = 90H
Description
1
st
Byte
2
nd
Byte
3
rd
Byte
4
th
Byte
Maker Code
Device Code
Don't care
Page Size, Block Size, Spare Size, Organization
I/Ox
t
AR
Device
Device Code*(2nd Cycle)
4th Cycle*
K9F2G08U0M
DAh
15h
Code*
FLASH MEMORY
32
K9F2G08U0M
K9K4G08U1M
4th ID Data
Description
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
Page Size
(w/o redundant area )
1KB
2KB
Reserved
Reserved
0 0
0 1
1 0
1 1
Block Size
(w/o redundant area )
64KB
128KB
256KB
Reserved
0 0
0 1
1 0
1 1
Redundant Area Size
( byte/512byte)
8
16
0
1
Organization
x8
x16
0
1
Serial AccessMinimum
50ns/30ns
25ns
Reserved
Reserved
0
1
0
1
0
0
1
1
FLASH MEMORY
33
K9F2G08U0M
K9K4G08U1M
Device Operation
PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data
within the selected page are transferred to the data registers in less than 25
s(t
R
). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read
out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
Address(5Cycle)
00h
Col Add1,2 & Row Add1,2,3
Data Output(Serial Access)
Data Field
Spare Field
CE
CLE
ALE
R/B
WE
RE
t
R
30h
I/Ox
FLASH MEMORY
34
K9F2G08U0M
K9K4G08U1M
Figure 7. Random Data Output In a Page
Address
00h
Data Output
R/B
RE
t
R
30h
Address
05h
E0h
5Cycles
2Cycles
Data Output
Data Field
Spare Field
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive
bytes up to 2112, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare
array(1time/16byte). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data
loading period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile programming period
where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-
ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-
gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
80h
R/B
Address & Data Input
I/O
0
Pass
Data
10h
70h
Fail
t
PROG
I/Ox
I/Ox
Col Add1,2 & Row Add1,2,3
"0"
"1"
Col Add1,2 & Row Add1,2,3
FLASH MEMORY
35
K9F2G08U0M
K9K4G08U1M
Cache Program
Figure 9. Random Data Input In a Page
80h
R/B
Address & Data Input
I/O
0
Pass
10h
70h
Fail
t
PROG
85h
Address & Data Input
Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block.
Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed
into memory cell.
After writing the first set of data up to 2112byte into the selected cache registers, Cache Program command (15h) instead of actual
Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache reg-
isters to data registers, the device remains in Busy state for a short period of time(tCBSY) and has its cache registers ready for the
next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may
be issued to find out when cache registers become ready by polling the Cache-Busy status bit(I/O 6). Pass/fail status of only the pre-
viouse page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command,
tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when
the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status
bit(I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the
progress of programming only with R/B, the last page of the target programming sequence must be progammed with actual Page
Program command (10h).
Figure 10. Cache Program
(available only within a block)
80h
R/B
80h
Address &
Data Input
15h
80h
Address &
Data Input
15h
80h
Address &
Data Input
10h
t
CBSY
t
CBSY
t
CBSY
t
PROG
70h
Address &
Data Input*
15h
I/Ox
Col Add1,2 & Row Add1,2,3
Col Add1,2
Data
Data
Col Add1,2 & Row Add1,2,3
Col Add1,2 & Row Add1,2,3
Col Add1,2 & Row Add1,2,3
Data
Data
Data
Col Add1,2 & Row Add1,2,3
Data
"0"
"1"
FLASH MEMORY
36
K9F2G08U0M
K9K4G08U1M
Copy-Back Program
Figure 11. Page Copy-Back program Operation
00h
R/B
Add.(5Cycles)
I/O
0
Pass
85h
70h
Fail
t
PROG
Add.(5Cycles)
t
R
Source Address
Destination Address
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-
efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-
ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves
the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input command
(85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actu-
ally begin the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is
allowed as shown in Figure 11. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status.
But if the soure page has an error bit by charge loss, accumulated copy-back operations could also accumulate bit errors.
In this case, verifying the source page for a bit error is recommended before Copy-back program"
35h
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the
previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after comple-
tion of the previous cycle, which can be expressed as the following formula.
tPROG= Program time for the last page+ Program time for the ( last -1 )th page
- (Program command cycle time + Last page data loading time)
10h
Figure 12. Page Copy-Back program Operation with Random Data Input
00h
R/B
Add.(5Cycles)
85h
70h
t
PROG
Add.(5Cycles)
t
R
Source Address
Destination Address
Data
35h
10h
85h
Data
Add.(2Cycles)
There is no limitation for the number of repetition.
I/Ox
I/Ox
Col. Add1,2 & Row Add1,2,3
Col. Add1,2 & Row Add1,2,3
Col. Add1,2 & Row Add1,2,3
Col. Add1,2 & Row Add1,2,3
Col Add1,2
NOTE: It's prohibited to operate Copy-Back program from an odd address page(source page) to an even address page(target page) or from an even
address page(source page) to an odd address page(target page). Therefore, the Copy-Back program is permitted just between odd address pages or
even address pages
FLASH MEMORY
37
K9F2G08U0M
K9K4G08U1M
Figure 13. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A
18
to A
28
is valid while A
12
to A
17
is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
60h
Block Add. : A
12
~ A
28
R/B
Address Input(3Cycle)
I/O
0
Pass
D0h
70h
Fail
t
BERS
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
Table2. Read Staus Register Definition
NOTE :
1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.
2. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
I/O No.
Page Program
Block Erase
Cache Prorgam
Read
Definition
I/O 0
Pass/Fail
Pass/Fail
Pass/Fail(N)
Not use
Pass : "0" Fail : "1"
I/O 1
Not use
Not use
Pass/Fail(N-1)
Not use
Pass : "0" Fail : "1"
I/O 2
Not use
Not use
Not use
Not use
Don't -cared
I/O 3
Not Use
Not Use
Not Use
Not Use
Don't -cared
I/O 4
Not Use
Not Use
Not Use
Not Use
Don't -cared
I/O 5
Ready/Busy
Ready/Busy
True Ready/Busy
Ready/Busy
Busy : "0" Ready : "1"
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Busy : "0" Ready : "1"
I/O 7
Write Protect
Write Protect
Write Protect
Write Protect
Protected : "0" Not Protected
I/Ox
"0"
"1"
FLASH MEMORY
38
K9F2G08U0M
K9K4G08U1M
Figure 14. Read ID Operation
CE
CLE
I/O
X
ALE
RE
WE
90h
00h
Address. 1cycle
Maker code
Device code
t
CEA
t
AR
t
REA
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, 50h respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Device
80h
4th Cyc.*
ECh
Figure 15. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after
the Reset command is written. Refer to Figure 15 below.
FFh
I/O
X
R/B
t
RST
t
WHR
t
CLR
Code*
Device
Device Code*(2nd Cycle)
3rd Cycle
4th Cycle*
K9F2G08U0M
DAh
80h
15h
Table3. Device Status
After Power-up
After Reset
PRE status
High
Low
Waiting for next command
Operation Mode
First page data access is ready
00h command is latched
FLASH MEMORY
39
K9F2G08U0M
K9K4G08U1M
Power-On Auto-Read
The device is designed to offer automatic reading of the first page without command and address input sequence during power-on.
An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto-
page read function. Auto-page read function is enabled only when PRE pin is tied to V
cc.
Serial access may be done after power-on
without latency.
Figure 16. Power-On Auto-Read
V
CC
CE
CLE
I/O
X
ALE
RE
WE
1st
~ 1.8V
PRE
R/B
2nd
3rd
....
n th
t
R
FLASH MEMORY
40
K9F2G08U0M
K9K4G08U1M
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can be
determined by the following guidance.
V
CC
R/B
open drain output
Device
GND
Rp
t
r
,
t
f [s
]
Ibusy [A]
Rp(ohm)
Figure 17. Rp vs tr ,tf & Rp vs ibusy
Ibusy
tr
ibusy
Busy
Ready Vcc
@ Vcc = 3.3V, Ta = 25
C , C
L
= 50pF
VOH
tf
tr
1K
2K
3K
4K
50n
100n
150n
3m
2m
1m
50
tf
100
150
200
1.8
1.8
1.8
1.8
2.4
1.2
0.8
0.6
VOL
where I
L
is the sum of the input currents of all devices tied to the R/B pin.
Rp value guidance
Rp(max) is determined by maximum permissible limit of tr
Rp(min, 3.3V part) =
V
CC
(Max.) - V
OL
(Max.)
I
OL
+
I
L
=
3.2V
8mA
+
I
L
3.3V device - V
OL
: 0.4V, V
OH
: 2.4V
C
L
FLASH MEMORY
41
K9F2G08U0M
K9K4G08U1M
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V
IL
during power-up and power-down. A recovery time of minimum 10
s is required before internal circuit gets ready for any command
sequences as shown in Figure 18. The two step command sequence for program/erase provides additional software protection.
Figure 18. AC Waveforms for Power Transition
V
CC
WP
High
WE
3.3V device : ~ 2.5V
3.3V device : ~ 2.5V
10
s
FLASH MEMORY
42
K9F2G08U0M
K9K4G08U1M
C
L
(F)
Figure 20. Rp vs tRHOH vs C
L
Rp = 10k
@ Vcc = 3.3V, Ta = 25
C
30p
50p
70p
100p
50n
100n
36
60
85
120
tRLOH / tRHOH value guidance
Figure 19. Serial Access Cycle after Read
(EDO Type, CLE=L, WE=H, ALE=L)
300n
500n
180
300
425
600
Rp = 100k
200n
400n
600n
360
600
V
CC
Device
GND
Rp
C
L
I/O Drive
tRHOH
Rp = 50k
30
42
60
18
Rp = 5k
RE
CE
R/B
I/Ox
t
RR
t
CEA
t
REA
t
RP
t
REH
t
RC
t
RHOH
t
RLOH
Dout
Dout
t
REA
NOTES : Transition is measured at
200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
t
RHOH
tRHOH = C
L
* V
OL
* Rp / Vcc
tRLOH(min, 3.3V part) = tRHOH - tREH
Extended Data Out Mode
For the EDO mode, the device should hold the data on the system memory bus until the beginning of the next cycle, so that controller
could fetch the data at the falling edge. However NAND flash dosen't support the EDO mode exactly.
The device stops the data input into the I/O bus after RE rising edge. But since the previous data remains in the I/O bus, the flow of I/
O data seems like Figure 18 and the system can access serially the data with EDO mode. tRLOH which is the parameter for fetching
data at RE falling time is necessary. Its appropriate value can be obtained with the reference chart as shown in Figure 19. The tRHOH
value depands on output load(C
L
) and I/O bus Pull-up resistor (Rp).
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