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K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
1
Document Title
4M x 8 Bit NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
0.0
0.1
0.2
0.3
0.4
0.5
Remark
Advance
History
Initial issue.
Data Sheet, 1999
1. Added CE don't care mode during the data-loading and reading
1. Revised real-time map-out algorithm(refer to technical notes)
2. Removed erase suspend/resume mode
1. Changed device name
- KM29W32000AT -> K9F3208W0A-TCB0
- KM29W32000AIT -> K9F3208W0A-TIB0
1. Changed invalid block(s) marking method prior to shipping
- The invalid block(s) information is written the 1st or 2nd page of the
invalid block(s) with 00h data
--->The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has
non-FFh
data at the column address of 517.
2. Changed SE pin description
- SE is recommended to coupled to GND or Vcc and should not be
toggled during reading or programming.
1.Powerup sequence is added
: Recovery time of minimum 1
s is required before internal circuit gets
ready for any command sequences
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. AC parameter tAR1 value : 150ns --> 20ns
4. #40 Pin Name : nSE --> GND
V
CC
WP
High
~ 2.5V
~ 2.5V
WE
1
Draft Date
April 10th 1998
April 10th 1999
July 23th 1999
Sep. 15th 1999
July 17th 2000
July 23th 2001
Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html.
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
2
4M x 8 Bit NAND Flash Memory
The K9F3208W0A is a 4M(4,194,304)x8bit NAND Flash Mem-
ory with a spare 128K(131,072)x8bit. Its NAND cell provides
the most cost-effective solution for the solid state mass storage
market. A program operation programs the 528-byte page in
typical 250
s and an erase operation can be performed in typi-
cal 2ms on an 8K-byte block.
Data in the page can be read out at 50ns cycle time per byte.
The I/O pins serve as the ports for address and data input/out-
put as well as command inputs. The on-chip write controller
automates all program and erase system functions, including
pulse repetition, where required, and internal verification and
margining of data. Even the write-intensive systems can take
advantage of the K9F3208W0A extended reliability of
1,000,000 program/erase cycles by providing ECC(Error Cor-
rection Code) with real time mapping-out algorithm. The
K9F3208W0A is an optimum solution for large nonvolatile stor-
age application such as solid state storage, digital voice
recorder, digital still camera and other portable applications
requiring nonvolatility.
GENERAL DESCRIPTION
FEATURES
Voltage Supply : 2.7V ~ 5.5V
Organization
- Memory Cell Array : (4M + 128K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (8K + 256)Byte
- Status Register
528-Byte Page Read Operation
- Random Access : 10
s(Max.)
- Serial Page Access : 50ns(Min.)
Fast Write Cycle Time
- Program Time : 250
s(Typ.)
- Block Erase Time : 2ms(Typ.)
Command/Address/Data Multiplexed I/O port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating-Gate Technology
- Endurance : 1Million Program/Erase Cycles
- Data Retention : 10 years
Command Register Operation
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
- Forward Type
PIN CONFIGURATION
NOTE : Connect all V
CC,
V
CC
Q and V
SS
pins of each device to power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
V
SS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
CC
Q
I/O4
I/O5
I/O6
I/O7
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
V
CC
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44(40) TSOP (II)
STANDARD TYPE
Pin Name
Pin Function
I/O0 ~ I/O7
Data Inputs/Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
SE
Spare area Enable
R/B
Ready/Busy output
GND
Ground Input
V
CC
Power(2.7V ~ 5.5V)
V
CC
Q
Output Butter Power(2.7V ~ 5.5V)
V
SS
Ground
N.C
No Connection
PIN DESCRIPTION
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
3
512Bytes
16Bytes
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Figure 2. ARRAY ORGANIZATION
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting Address of the 1st half of the Register.
01h Command(Read) : Defines the sarting Address of the 2nd half of the Register.
* A
8
is set to "Low" or "High" by the 00h or 01h Command.
* X can be High or Low.
* The device ignores any additional input of address cycles than reguired.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
2nd Cycle
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
3rd Cycle
A
17
A
18
A
19
A
20
A
21
*X
*X
*X
V
CC
X-Buffers
Y-Gating
32M + 1M Bit
Command
2nd half Page Register & S/A
NAND Flash
ARRAY
(512 + 16)Byte x 8192
Y-Gating
1st half Page Register & S/A
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
V
SS
A
9
- A
21
A
0
- A
7
Command
CE
RE
WE
CLE ALE WP
I/0 0
I/0 7
V
CC
Q
V
SS
A
8
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
32M : 8K Pages
(= 512 Blocks)
512Bytes
8 bit
16Bytes
1 Block =16 Pages
= (8K + 256) Byte
I/O 0 ~ I/O 7
1 Page = 528 Bytes
1 Block = 528 B x 16 Pages
= (8K + 256) Bytes
1 Device = 528Bytes x 16Pages x 512 Blocks
= 33 Mbits
Column Address
Row Address
(Page Address)
Page Register
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
4
PRODUCT INTRODUCTION
The K9F3208W0A is a 33Mbit(34,603,008 bit) memory organized as 8192 rows(pages) by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans-
fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells
that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16
pages formed by one NAND structures, totaling 4,224 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array
consists of 512 separately or grouped erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9F3208W0A.
The K9F3208W0A has addresses multiplexed into 8 I/O
s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O
s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 4M byte physical space requires 22 addresses, thereby requiring three cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F3208W0A.
Table 1. COMMAND SETS
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved
to the 1st half register(00h) on the next cycle.
2. The 50h command is valid only when the SE(pin 40) is low level.
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 1
00h/01h
(1)
-
Read 2
50h
(2)
-
Read ID
90h
-
Reset
FFh
-
O
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
O
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
5
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby
mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
Spare Area Enable(SE)
The SE input controls the access of the spare area. When SE is high, the spare area is not accessible for reading or programming.
SE is recommended to be coupled to GND or Vcc and should not be toggled during reading or programming.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
Power Line(V
CC
& V
CCQ
)
The V
CCQ
is the power supply for I/O interface logic. It is electrically isolated from main power line(V
CC
=2.7~5.5V) for supporting 5V
tolerant I/O with 5V power supply at V
CCQ
.
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
6
ABSOLUTE MAXIMUM RATINGS
NOTE :
1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V
CC
Q+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN
-0.6 to +7.0
V
Temperature Under Bias
K9F3208W0A-TCB0
T
BIAS
-10 to +125
C
K9F3208W0A-TIB0
-40 to +125
Storage Temperature
T
STG
-65 to +150
C
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Parameter
Symbol
Test Conditions
Vcc=2.7V ~ 3.6V
Vcc=3.6V ~ 5.5V
Unit
Min
Typ
Max
Min
Typ
Max
Operating
Current
Sequential Read
I
CC
1
tRC=80ns, CE=V
IL
, I
OUT
=0mA
-
10
20
-
15
30
mA
Program
I
CC
2
-
-
10
20
-
15
30
Erase
I
CC
3
-
-
10
20
-
25
40
Stand-by Current(TTL)
I
SB
1
CE=V
IH
, WP=SE=0V/V
CC
-
-
1
-
-
1
Stand-by Current(CMOS)
I
SB
2
CE=V
CC
-0.2, WP=SE=0V/V
CC
-
10
50
-
10
50
A
Input Leakage Current
I
LI
V
IN
=0 to 5.5V
-
-
10
-
-
10
Output Leakage Current
I
LO
V
OUT
=0 to 5.5V
-
-
10
-
-
10
Input High Voltage
V
IH
I/O pins
2.0
-
V
CC
Q+0.3
3.0
-
V
CC
Q+0.5
V
Except I/O pins
2.0
-
V
CC
+0.3
3.0
-
V
CC
+0.5
Input Low Voltage, All inputs
V
IL
-
-0.3
-
0.6
-0.3
-
0.8
Output High Voltage Level
V
OH
I
OH
=-400
A
2.4
-
-
2.4
-
-
Output Low Voltage Level
V
OL
I
OL
=2.1mA
-
-
0.4
-
-
0.4
Output Low Current(R/B)
I
OL
(R/B) V
OL
=0.4V
8
10
-
8
10
-
mA
RECOMMENDED OPERATING
CONDITIONS
(Voltage reference to GND, K9F3208W0A-TCB0:T
A
=0 to 70
C, K9F3208W0A-TIB0:T
A
=-40 to 85
C)
NOTE : 1. Vcc and VccQ pins are separated each other.
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
V
CC
2.7
-
5.5
V
Supply Voltage
V
CC
Q
2.7
-
5.5
V
Supply Voltage
V
SS
0
0
0
V
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
7
MODE SELECTION
NOTE : 1. X can be V
IL
or V
IH
2. WP should be biased to CMOS high or CMOS low for standby.
3. When SE is high, spare area is deselected.
CLE
ALE
CE
WE
RE
SE
WP
Mode
H
L
L
H
X
X
Read Mode
Command Input
L
H
L
H
X
X
Address Input(3clock)
H
L
L
H
X
H
Write Mode
Command Input
L
H
L
H
X
H
Address Input(3clock)
L
L
L
H
L/H
(3)
H
Data Input
L
L
L
H
L/H
(3)
X
Sequential Read & Data Output
L
L
L
H
H
L/H
(3)
X
During Read(Busy)
X
X
X
X
X
L/H
(3)
H
During Program(Busy)
X
X
X
X
X
X
H
During Erase(Busy)
X
X
(1)
X
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2)
0V/V
CC
(2)
Stand-by
CAPACITANCE
(T
A
=25
C, Vcc=5.0V f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
VALID BLOCK
NOTE :
1. The
K9F3208W0A
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
.
Do not
erase or program factory-market bad blocks.
Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
502
508
512
Blocks
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
-
0.25
1.5
ms
Number of Partial Program Cycles in the Same Page
Nop
-
-
10
cycles
Block Erase Time
t
BERS
-
2
10
ms
AC TEST CONDITION
(K9F3208W0A-TCB0:T
A
=0 to 70
C, K9F3208W0A-TIB0:T
A
=-40 to 85
C, V
CC
=2.7V ~ 5.5V unless otherwise noted)
Parameter
Value
Vcc=2.7V ~ 3.6V
Vcc=3.6V ~ 5.5V
Input Pulse Levels
0.4V to 2.4V
0.4V to 3.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
0.8V and 2.0V
Output Load
1 TTL GATE and
1 TTL GATE and CL=100pF
CL=50pF(3.0V+/-10%),100pF(3.0V~3.6V)
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
8
AC Characteristics for Operation
NOTE :
1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
Parameter
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
t
R
-
10
s
ALE to RE Delay(read ID)
t
AR1
20
-
ns
ALE to RE Delay(Read cycle)
t
AR2
50
-
ns
CLE to RE Delay
t
CLR
50
-
ns
CE to RE Delay(ID read)
t
CR
100
-
ns
Ready to RE Low
t
RR
20
-
ns
RE Pulse Width
t
RP
30
-
ns
WE High to Busy
t
WB
-
100
ns
Read Cycle Time
t
RC
50
-
ns
RE Access Time
t
REA
-
35
ns
RE High to Output Hi-Z
t
RHZ
15
30
ns
CE High to Output Hi-Z
t
CHZ
-
20
ns
RE High Hold Time
t
REH
15
-
ns
Output Hi-Z to RE Low
t
IR
0
-
ns
Last RE High to Busy(at sequential read)
t
RB
-
100
ns
CE High to Ready(in case of interception by CE at read)
t
CRY
-
50 +tr(R/B)
(1)
ns
CE High Hold Time(at the last serial read)
(2)
t
CEH
100
-
ns
RE Low to Status Output
t
RSTO
-
35
ns
CE Low to Status Output
t
CSTO
-
45
ns
RE High to WE Low
t
RHW
0
-
ns
WE High to RE Low
t
WHR
60
-
ns
RE access time(Read ID)
t
READID
-
35
ns
Device Resetting Time
(Read/Program/Erase)
t
RST
-
5/10/500
s
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLE Set-up Time
t
CLS
0
-
ns
CLE Hold Time
t
CLH
10
-
ns
CE Setup Time
t
CS
0
-
ns
CE Hold Time
t
CH
10
-
ns
WE Pulse Width
t
WP
25
-
ns
ALE Setup Time
t
ALS
0
-
ns
ALE Hold Time
t
ALH
10
-
ns
Data Setup Time
t
DS
20
-
ns
Data Hold Time
t
DH
10
-
ns
Write Cycle Time
t
WC
50
-
ns
WE High Hold Time
t
WH
15
-
ns
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
9
Identifying Invalid Block(s)
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar-
anteed to be a valid block, does not require Error Correction.
NAND Flash Technical Notes
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte in the spare area.
Samsung makes sure that either the 1st or 2nd page of every invalid
block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impos-
sible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based
on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any inten-
tional erasure of the original invalid block information is prohibited.
*
Figure 1. Flow chart to create invalid block table.
Start
Set Block Address = 0
Check "FFh" ?
Increment Block Address
Last Block ?
End
No
Yes
Yes
Create (or update)
No
Invalid Block(s) Table
Check "FFh" at the column address 517
of the 1st and 2nd page in the block
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
10
NAND Flash Technical Notes (Continued)
Program Flow Chart
Start
I/O 6 = 1 ?
Write 00h
I/O 0 = 0 ?
No
*
If ECC is used, this verification
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
Write Address
Wait for tR Time
Verify Data
No
Program Completed
or R/B = 1 ?
Program Error
Yes
No
Yes
*
Program Error
Yes
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
operation is not needed.
Error in write or read operation
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of mem-
ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Write
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Read
Single Bit Failure
Verify ECC -> ECC Correction
ECC
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
11
Erase Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 60h
Write Block Address
Write D0h
Read Status Register
or R/B = 1 ?
Erase Error
Yes
No
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Erase Completed
Yes
Read Flow Chart
Start
Verify ECC
No
Write 00h
Write Address
Read Data
ECC Generation
Reclaim the Error
Page Read Completed
Yes
NAND Flash Technical Notes (Continued)
Block Replacement
* Step1
When an error happens in the nth page of the Block 'A' during erase or program operation.
* Step2
Copy the nth page data of the Block 'A' in the buffer memory to the nth page of another free block. (Block 'B')
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block 'B'.
* Step4
Do not erase or program to Block 'A' by creating an 'invalid Block' table or other appropriate scheme.
Buffer memory of the controller.
1st
Block A
Block B
(n-1)th
nth
(page)
1
2
{
1st
(n-1)th
nth
(page)
{
an error occurs.
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
12
Pointer Operation of K9F3208W0A
The K9F3208W0A has three modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to "B"
area by the "01h" command, and to "C" area by the "50h" command. Table 1 shows the destination of the pointer, and figure 2 shows
the block diagram of its operations.
Examples of Programming with Successive Pointer Operation
50h
"C" area
(1) "A" area program
"A" area
Address / Data input
Table 1. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
Table 2. Pointer Status after each operation
* 01h command is valid just one time when it is used as a pointer for program/erase.
* Erase operation does not affect the pointer status. Previous pointer status is maintained.
Operation
Pointer status after operation
Program
Reset
Power up
With previous 00h, Device is set to 00h Plane
With previous 01h, Device is set to 00h Plane*
With previous 50h, Device is set to 50h Plane
"00h" Plane("A" area)
"00h" Plane("A" area)
00h
80h
"A" area program
00h
"A" area
(2) "B" area program
"B" area
Address / Data input
01h
80h
"A" area program
00h
"A" area
(3) "C" area program
"C" area
Address / Data input
50h
80h
"C" area program
10h
80h
10h
10h
80h
10h
10h
80h
10h
Address / Data input
Address / Data input
Address / Data input
"A" area program
"B" area program
"C" area program
"A" area
256 Byte
(00h plane)
"B" area
(01h plane)
"C" area
(50h plane)
256 Byte
16 Byte
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 2. Block Diagram of Pointer Operation
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
13
System Interface Using CE don't-care.
CE
WE
t
WP
t
CH
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
t
CS
(Min. 10ns)
Start Add.(3Cycle)
80h
Data Input
CE
CLE
ALE
WE
I/O
0
~
7
Data Input
CE don't-care
10h
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Start Add.(3Cycle)
00h
CE
CLE
ALE
WE
I/O
0
~
7
Data Output(sequential)
CE don't-care
R/B
t
R
RE
t
CEA
out
t
REA
(Max. 45ns)
CE
RE
I/O
0
~
7
Timing requirements : If CE is is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Figure 3. Program Operation with CE don't-care.
Figure 4. Read Operation with CE don't-care.
Must be held
low during tR.
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
14
* Command Latch Cycle
CE
WE
CLE
ALE
I/O
0
~
7
Command
* Address Latch Cycle
CE
WE
CLE
ALE
I/O
0
~
7
A
0
~A
7
A
9
~A
16
A
17
~A
21
t
CLS
t
CS
t
CLH
t
CH
t
WP
t
ALS
t
ALH
t
DS
t
DH
t
CLS
t
CS
t
WC
t
WC
t
WP
t
WP
t
WH
t
WH
t
ALS
t
ALH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
WP
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
15
* Input Data Latch Cycle
CE
CLE
WE
I/O
0
~
7
DIN 0
DIN 1
DIN 511
ALE
t
ALS
t
CLH
t
WC
t
CH
t
DS
t
DS
t
DH
t
DS
t
DH
t
WP
t
WH
t
WP
t
DH
t
WP
* Sequential Out Cycle after Read
(CLE=L, WE=H, ALE=L)
RE
CE
R/B
I/O
0
~
7
tRHZ*
Dout
Dout
Dout
t
RC
t
REA
t
RR
t
RHZ*
t
REA
t
REH
t
REA
t
CHZ*
t
RHZ
t
RP
NOTES : Transition is measured
200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
16
* Status Read Cycle
CE
WE
CLE
RE
I/O
0
~
7
70h
Status Output
t
CLR
t
CLH
t
CS
t
WP
t
CH
t
DS
t
DH
t
RSTO
t
IR
t
RHZ*
t
CHZ*
t
WHR
t
CSTO
t
CLS
READ1 OPERATION
(READ ONE PAGE)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
Busy
00h or 01h
A
0
~ A
7
A
9
~ A
16
A
17
~ A
21
Dout N
Dout N+1
Dout N+2
Dout N+3
Dout 527
Column
Address
Page(Row)
Address
t
WB
t
AR2
t
R
t
RC
t
RHZ
t
RR
t
CHZ
t
RB
t
CRY
t
WC
t
CEH
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
17
READ1 OPERATION
(INTERCEPTED BY CE)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
Busy
00h or 01h A
0
~ A
7
A
9
~ A
16
A
17
~ A
21
Dout N
Dout N+1
Dout N+2
Dout N+3
Page(Row)
Address
Address
Column
t
WB
t
AR2
t
CHZ
t
R
t
RR
t
RC
READ2 OPERATION
(READ ONE PAGE)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
50h
A
0
~ A
7
A
9
~ A
16
A
17
~ A
21
Dout
Dout 527
M Address
A
0
~ A
3
:Valid Address
A
4
~ A
7
:Don't care
511+M
Dout
511+M+1
Selected
Row
Start
address M
512
16
t
AR2
t
R
t
WB
t
RR
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
18
SEQUENTIAL ROW READ OPERATION
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
00h
A
0
~ A
7
Busy
M
Output
A
9
~ A
16
A
17
~ A
21
Dout
N
Dout
N+1
Dout
N+2
Dout
527
Dout
0
Dout
1
Dout
2
Dout
527
Busy
M+1
Output
N
PAGE PROGRAM OPERATION
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
80h
70h
I/O
0
Din
N
Din
Din
10h
527
N+1
A
0
~ A
7
A
17
~ A
21
A
9
~ A
16
Sequential Data
Input Command
Column
Address
Page(Row)
Address
1 up to 528 Byte Data
Sequential Input
Program
Command
Read Status
Command
I/O
0
=0 Successful Program
I/O
0
=1 Error in Program
t
PROG
t
WB
t
WC
t
WC
t
WC
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
19
BLOCK ERASE OPERATION
(ERASE ONE BLOCK)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
60h
A
17
~ A
21
A
9
~ A
16
Auto Block Erase Setup Command
Erase Command
Read Status
Command
I/O
0
=1 Error in Erase
DOH
70h
I/O
0
Busy
t
WB
t
BERS
t
WC
t
WC
Block
Address
I/O
0
=0 Successful Erase
MANUFACTURE & DEVICE ID READ OPERATION
CE
CLE
I/O
0
~
7
WE
ALE
RE
90h
Read ID Command
Maker Code
Device Code
00h
ECh
E3h
t
REAID
t
CLR
t
AR1
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
20
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 10
s(t
R
). The CPU can detect the completion of this data transfer(t
R
) by analyzing the output
of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE
with CE staying low. High to low transitions of the RE clock output the data starting from the selected column address up to the last
column address(column 511 or 527 depending on state of SE pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential read.
Waiting 10
s again allows for reading of the selected page. The sequential read operation is terminated by bringing CE high. The
way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes
512 to 527 may be selectively accessed by writing the Read2 command with SE pin low. Toggling SE during operation is prohibited.
Addresses A
0
to A
3
set the starting address of the spare area while addresses A
4
to A
7
are ignored. Unless the operation is aborted,
the page address is automatically incremented for sequential read as in Read1 operation and spare sixteen bytes of each page may
be sequentially read. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 3 through 6 show
typical sequence and timings for each read operation.
Figure 3. Read1 Operation
Start Add.(3Cycle)
00h
01h
A
0
~ A
7
& A
9
~ A
21
Data Output(Sequential)
(00h Command)
1st half array 2nd half array
CE
CLE
ALE
R/B
WE
Data Field
Spare Field
(01h Command)*
1st half array 2nd half array
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
I/O
0
~
7
RE
t
R
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
21
Figure 5. Sequential Row Read1 Operation
Figure 4. Read2 Operation
50h
A
0
~ A
3
& A
9
~ A
21
Data Output(Sequential)
Spare Field
CE
CLE
ALE
R/B
WE
1st half array 2nd half array
Data Field
Spare Field
(SE=L, 00h Command)
1st half array 2nd half array
Data Field
Spare Field
00h
01h
A
0
~ A
7
& A
9
~ A
21
I/O
0
~
7
R/B
Start Add.(3Cycle)
Start Add.(3Cycle)
Data Output
Data Output
Data Output
1st
2nd
Nth
(528 Byte)
(528 Byte)
(A
4
~ A
7
:
Don't Care)
1st
2nd
Nth
(SE=L, 01h Command)
1st half array 2nd half array
Data Field
Spare Field
1st
2nd
Nth
(SE=H, 00h Command)
1st half array 2nd half array
Data Field
Spare Field
1st
2nd
Nth
I/O
0
~
7
RE
t
R
t
R
t
R
t
R
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
22
Figure 6. Sequential Read2 Operation (SE=fixed low)
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed ten. The addressing may be done in any random order in a block. A
page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, fol-
lowed by a nonvolatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can
be started from 2nd half array. About the pointer operation, please refer to the attached technical notes.The serial data loading period
begins by inputting the Serial Data Input command(80H), followed by the three cycle address input and then serial data loading. The
bytes other than those to be programmed do not need to be loaded.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without perviously entering the
serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Regis-
ter command may be entered, with RE and CE low, to read the status register. The CPU can detect the completion of a program
cycle by monitoring the R/B output, or the Status bit(I/O
6
) of the Status Register. Only the Read Status command and Reset com-
mand are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O
0
) may be
checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
50h
A
0
~ A
3
& A
9
~ A
21
I/O
0
~
7
R/B
Start Add.(3Cycle)
Data Output
Data Output
Data Output
2nd
Nth
(16 Byte)
(16 Byte)
1st half array 2nd half array
Data Field
Spare Field
1st
2nd
Nth
(A
4
~ A
7
:
Don't Care)
1st
Figure 7. Program & Read Status Operation
80h
A
0
~ A
7
& A
9
~ A
21
Address & Data Input
I/O
0
Pass
528 Byte Data
10h
70h
Fail
I/O
0
~
7
R/B
t
R
t
R
t
R
t
PROG
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
23
Figure 8. Block Erase Operation
BLOCK ERASE
The Erase operation can erase on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A
13
to A
21
is valid while A
9
to A
12
is ignored. The addresses of the block to be erased to FFh.
The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence
of setup followed by execution ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O
0
) may be checked. Figure 8 details the sequence.
60h
Block Add. : A
9
~ A
21
I/O
0
~
7
R/B
Address Input(2Cycle)
I/O
0
Pass
D0h
70h
Fail
t
BERS
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether
the program or erase operation completed successfully. After writing 70h command to the command register, a read cycle outputs
the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table2. Read Status Register Definition
I/O #
Status
Definition
I/O
0
Program / Erase
"0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O
1
Reserved for Future
Use
"0"
I/O
2
"0"
I/O
3
"0"
I/O
4
"0"
I/O
5
"0"
I/O
6
Device Operation
"0" : Busy "1" : Ready
I/O
7
Write Protect
"0" : Protected "1" : Not Protected
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
24
Figure 9. Read ID Operation
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (E3h) respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
CE
CLE
I/O
0
~
7
ALE
RE
WE
90h
00h
ECh
E3h
Address. 1 cycle
Maker code
Device code
t
READID
t
AR1
t
CEA
Figure 10. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to
"1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is
high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted to by the command register. The R/B pin transitions to low for t
RST
after the Reset command is written. Reset command is
not necessary for normal operation. Refer to Figure 10 below.
Table3. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
FFh
I/O
0
~
7
R/B
t
RST
t
CLR
t
WHR
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
25
The device has a R/
B
output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is begin after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 11). Its value can
be determined by the following guidance.
READY/BUSY
V
CC
R/B
open drain output
Device
GND
where I
L
is the sum of the input currents of all devices tied to the R/B pin.
Rp
t
r
,
t
f
[
s
]
I
b
u
s
y
[
A
]
Rp(ohm)
Fig 11 Rp vs tr ,tf & Rp vs ibusy
Ibusy
tr
Rp value guidance
Rp(max) is determined by maximum permissible limit of tr
ibusy
Rp(min) =
V
CC
(Max.) - V
OL
(Max.)
I
OL
+
I
L
=
3.2V
8mA
+
I
L
Busy
Ready Vcc
@ Vcc = 3.3V, Ta = 25
C , C
L
= 100pF
2.0V
tf
tr
1K
2K
3K
4K
100n
200n
300n
3m
2m
1m
96
tf
189
290
381
4.2
4.2
4.2
4.2
3.3
1.65
1.1
0.825
0.8V
Package Dimensions
FLASH MEMORY
26
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V
IL
during power-up and power-down and recovery time of minimum 1
s is required before internal circuit gets ready for any command
sequences as shown in Figure 12. The two step command sequence for program/erase provides additional software protection.
Figure 12. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
V
CC
WP
High
WE
10
s
Package Dimensions
FLASH MEMORY
27
PACKAGE DIMENSIONS
Unit :mm/Inch
0~8
0
.
0
0
2
0.805
#1
44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II)
0
.
0
5
#22(20)
#44(40)
#23(21)
0.032
0.35
0.10
0.014
0.004
0.80
0.0315
M
i
n
.
0
.
0
4
7
1
.
2
0
M
a
x
.
0.741
18.81
Max.
18.41
0.10
0.725
0.004
+0.10
-0.05
+0.004
-0.002
0.15
0.006
1
0
.
1
6
0
.
4
0
0
44(40) - TSOP2 - 400F
0.10
0.004
0.50
0.020
0.25
0.010
TYP
0
.
4
5
~
0
.
7
5
0
.
0
1
8
~
0
.
0
3
0
0
.
0
3
9
0
.
0
0
4
1
.
0
0
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.
1
0
MAX
1
1
.
7
6
0
.
2
0
0
.
4
6
3
0
.
0
0
8
(
)
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