K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
1
Document Title
512K x 8 bit NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
0.0
1.0
1.1
1.2
1.3
Remark
Preliminary
History
Initial issue.
1. Changed Operating Voltage 2.7V ~ 5.5V
3.0V ~ 5.5V
Data Sheet 1999
1. Added CE don't care mode during the data-loading and reading
1. Changed device name
- KM29W040AT -> K9F4008W0A-TCB0
- KM29W040AIT -> K9F4008W0A-TIB0
1.Powerup sequence is added
: Recovery time of minimum 1
s is required before internal circuit gets
ready for any command sequences
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3.
AC parameter tAR is devided into tAR1, tAR2 (before revision)
(after revision)
ALE to RE Delay
t
AR
250
-
ns
ALE to RE Delay(ID Delay)
t
AR1
20
-
ns
ALE to RE Delay(Read Cycle)
t
AR2
250
-
ns
V
CC
WP
High
~ 2.5V
~ 2.5V
WE
1
Draft Date
April 10th 1998
July 14th 1998
April 10th 1999
Sep. 15th 1999
Jul. 23th 2001
Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
2
512K x 8 Bit NAND Flash Memory
The K9F4008W0A is a 512Kx8bit NAND Flash Memory. Its
NAND cell structure provides the most cost-effective solution
for Digital Audio Recording. A Program operation programs a
32-byte frame in typical 500
s and an Erase operation erase a
4K-byte block in typical 6ms. Data in a frame can be read out at
a burst cycle rate of 120ns/byte. The I/O pins serve as the ports
for address and data input/output as well as for command
inputs. The on-chip write controller automates the program and
erase operations, including program or erase pulse repetition
where required, and performs internal verification of cell data.
The K9F4008W0A is an optimum solution for flash memory
application that do not require the high performance levels or
capacity of larger density flash memories. These application
include data storage in digital Telephone Answering
Devices(TAD) and other consumer applications that require
voice data storage.
GENERAL DESCRIPTION
FEATURES
Voltage Supply: 3.0V~5.5V
Organization
- Memory Cell Array : 512K x 8 bit
- Data Register : 32 x 8 bit
Automatic Program and Erase (Typical)
- Frame Program : 32 Byte in 500
s
- Block Erase : 4K Byte in 6ms
32-Byte Frame Read Operation
- Random Access : 15
s(Max.)
- Serial Frame Access : 120ns(Min.)
Command/Address/Data Multiplexed I/O port
Low Operation Current (Typical)
- 10
A Standby Current
- 10mA Read/ Program/Erase Current
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
Package
- 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
PIN CONFIGURATION
VSS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
I/O4
I/O5
I/O6
I/O7
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
VCC
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44(40) TSOP (II)
NOTE : Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC,
V
SS
or GND inputs disconnected.
PIN DESCRIPTION
Pin Name
Pin Function
I/O
0
~ I/O
7
Data Inputs/Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
GND
Ground Input
R/B
Ready/Busy output
V
CC
Power
V
SS
Ground
N.C
No Connection
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
3
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Figure 2. ARRAY ORGANIZATION
NOTE : *(1) : X can be V
IL
or V
IH
* The device ignores any additional input of address cycles than reguired.
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
1st Cycle
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
2nd Cycle
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
3rd Cycle
A
16
A
17
A
18
X*
(1)
X*
X*
*X
*X
Column Address (A
0
-A
4
)
Frame Address (A
5
-A
6
)
Row Address (A
7
-A
11
)
Block Address (A
12
-A
18
)
128Bytes
4K Rows
(=128 Blocks)
32 Bytes
8 bit
Good Block
I/O
0
~ I/O
7
1 Frame = 32 Bytes
1 Row = 4 Frames = 128 Bytes
1 Block = 32 Rows = 4K Bytes
1 Device = 32Bytes x 4Frames x 32Rows x 128Blocks
= 4Mbits
Frame Register
1
2
3
4
X-Buffers
4M Bit
Command
NAND Flash ARRAY
32Byte x 4Frames x 4096Rows
Y-Gating
Page Register & S/A
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator
Global Buffers
A
7
- A
18
A
0
- A
6
Command
CE
RE
WE
CLE ALE WP
I/O
0
I/O
7
The 1st Block (4KB)
1Block = 32 Rows
= 4K Bytes
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
4
PRODUCT INTRODUCTION
The K9F4008W0A is a 4M bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell
arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The
memory array is composed of unit NAND structures in which 8 cells are connected serially.
Each of the 8 cells reside in a different row. A block consists of the 32 rows, totaling 4096 unit NAND structures of 8bits each. The
array organization is shown in Figure 2. The program and read operations are executed on a frame basis, while the erase operation is
executed on a block basis. The memory array consists of 128 separately erasable 4K-byte blocks.
The K9F4008W0A has addresses multiplexed into 8 I/O pins. This scheme not only reduces pin count but allows systems upgrades to
higher density flash memories by maintaining consistency in system board design. Command, address and data are all written
through I/O
s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus
cycle except for Block Erase command which requires two cycles. For byte-level addressing, the 512K byte physical space requires a
19-bit address, low row address and high row address. Frame Read and frame Program require the same three address cycles fol-
lowing by a command input. In the Block Erase operation, however, only the two row address cycles are required.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F4008W0A.
Table 1. COMMAND SETS
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read
00h
-
Reset
FFh
-
O
Frame Program
80h
10h
Block Erase
60h
D0h
Status read
70h
-
O
Read ID
90h
-
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
5
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t
REA
after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O
0
~ I/O
7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
PDF 
ZIP