FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

K9XXG08UXA

* Samsung Electronics reserves the right to change products or specification without notice.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

GENERAL DESCRIPTION

FEATURES

· Voltage Supply
- 2.70V ~ 3.60V
· Organization
- Memory Cell Array : (512M + 16M) x 8bit
- Data Register : (2K + 64) x 8bit
· Automatic Program and Erase
- Page Program : (2K + 64)Byte
- Block Erase : (128K + 4K)Byte
· Page Read Operation
- Page Size : (2K + 64)Byte
- Random Read : 25

µs(Max.)

- Serial Access : 25ns(Min.)

512M x 8 Bit / 1G x 8 Bit NAND Flash Memory

· Fast Write Cycle Time
- Page Program time : 200

µs(Typ.)

- Block Erase Time : 1.5ms(Typ.)
· Command/Address/Data Multiplexed I/O Port
· Hardware Data Protection
- Program/Erase Lockout During Power Transitions
· Reliable CMOS Floating-Gate Technology
-Endurance : 100K Program/Erase Cycles(with 1bit/512Byte
ECC)
- Data Retention : 10 Years
· Command Driven Operation
· Intelligent Copy-Back with internal 1bit/528Byte EDC
· Unique ID for Copyright Protection
· Package :
- K9F4G08U0A-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F4G08U0A-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 1.00 mm pitch)
- K9K8G08U1A-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 1.00 mm pitch)

Offered in 512Mx8bit, the K9F4G08U0A is a 4G-bit NAND Flash Memory with spare 128M-bit. Its NAND cell provides the most cost-
effective solution for the solid state application market. A program operation can be performed in typical 200

µs on the (2K+64)Byte

page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out
at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip
write controller automates all program and erase functions including pulse repetition, where required, and internal verification and
margining of data. Even the write-intensive systems can take advantage of the K9F4G08U0A

s extended reliability of 100K program/

erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F4G08U0A is an optimum solu-
tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

PRODUCT LIST

Part Number

Vcc Range

Organization

PKG Type

K9F4G08U0A-P

2.70 ~ 3.60V

TSOP1

K9F4G08U0A-I

52ULGA

K9K8G08U1A-I

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

PIN CONFIGURATION (TSOP1)

K9F4G08U0A-PCB0/PIB0

PACKAGE DIMENSIONS

48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F

Unit :mm/Inch

0.787

±0.008

20.00

±0.20

#24

.
0
7

-0

008

0
.003

-0

019

#48

#25

488

.40

MAX

.00

472

0.1

004

MAX

0.2

010

()

0.039

±0.002

1.00

±0.05

0.002

0.05

MIN

0.047

1.20

MAX

0.45~0.75

0.018~0.030

0.724

±0.004

18.40

±0.10

0~8

010

0.2

TYP

125

.
0
75

0.0

3
5

.
0

0
3

-0

0
1

0.50

0.020

(

)

48-pin TSOP1

Standard Type
12mm x 20mm

N.C

R/B

N.C

Vcc

Vss

N.C

CLE

ALE

N.C

I/O7

I/O6

I/O5

I/O4

N.C

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

1.00

2.00

7 6 5 4 3 2 1

1.0

12.00

±0.10

#A1

17.

±
0.

.00

0.1

12.00

±0.10

(Datum B)

(Datum A)

12.

10.00

0.5

12-

1.00±0.05

41-

0.70

0.05

Side View

(
Max

0.10 C

17.00

±0.10

Top View

Bottom View

D E

H J

PIN CONFIGURATION (ULGA)

K9F4G08U0A-ICB0/IIB0

52-ULGA (measured in millimeters)

Vcc

Vss

/RE

/CE

CLE

ALE

/WE

/WP

R/B

Vss

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

0.1

PACKAGE DIMENSIONS

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

1.00

2.00

7 6 5 4 3 2 1

1.0

12.00

±0.10

#A1

17.

±
0.

.00

0.1

12.00

±0.10

(Datum B)

(Datum A)

12.

10.00

0.5

12-

1.00±0.05

41-

0.70

0.05

Side View

(
Max

0.10 C

17.00

±0.10

Top View

Bottom View

D E

H J

K9K8G08U1A-ICB0/IIB0

52-ULGA (measured in millimeters)

Vcc

Vss

/RE1

/RE2

/CE1

/CE2

CLE1

CLE2

ALE1

ALE2

/WE1

/WE2

/WP1

/WP2

R/B1

R/B2

Vss

IO0-1

IO0-2

IO1-1

IO1-2

IO2-1

IO3-1

IO2-2

IO3-2

IO4-1

IO4-2

IO5-1

IO5-2

IO6-1

IO6-2

IO7-1

IO7-2

0.1

PACKAGE DIMENSIONS

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

PIN DESCRIPTION

NOTE : Connect all V

and V

pins of each device to common power supply outputs.

Do not leave V

or V

disconnected.

Pin Name

Pin Function

I/O

~ I/O

DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.

CLE

COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ALE

ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.

CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation.

READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.

WRITE PROTECT
The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-
age generator is reset when the WP pin is active low.

R/B

READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.

Vcc

POWER
V

is the power supply for device.

Vss

GROUND

N.C

NO CONNECTION
Lead is not internally connected.

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

2K Bytes

64 Bytes

Figure 1. K9F4G08U0A Functional Block Diagram

Figure 2. K9F4G08U0A Array Organization

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".
* The device ignores any additional input of address cycles than required.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

X-Buffers

Command

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

- A

Command

CE
RE
WE

CLE

I/0 0

I/0 7

256K Pages
(=4,096 Blocks)

2K Bytes

8 bit

64 Bytes

1 Block = 64 Pages
(128K + 4k) Byte

I/O 0 ~ I/O 7

1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 4,096 Blocks
= 4,224 Mbits

Row Address

Page Register

ALE

4,096M + 128M Bit

NAND Flash

ARRAY

(2,048 + 64)Byte x 262,144

Y-Gating

Row Address

Column Address

Row Address

Data Register & S/A

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Product Introduction

The K9F4G08U0A is a 4,224Mbit(4,429,185,024 bit) memory organized as 262,144 rows(pages) by 2,112x8 columns. Spare 64x8
columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-
dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made
up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists
of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program
and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-
sists of 4,096 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F4G08U0A.

The K9F4G08U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 528M byte physical space
requires 30 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-
ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the
command register. Table 1 defines the specific commands of the K9F4G08U0A.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

NOTE : 1. Random Data Input/Output can be executed in a page.
2. Read EDC Status is only available on Copy Back operation.
3. Any command between 11h and 81h is prohibited except 70h and FFh.

Caution :

Any undefined command inputs are prohibited except for above command set of Table 1.

Function

1st Cycle

2nd Cycle

Acceptable Command during Busy

Read 00h

30h

Read for Copy Back

00h

35h

Read ID

90h

Reset

FFh

Page Program

80h

10h

Two-Plane Page Program

(3)

80h---11h

81h---10h

Copy-Back Program

85h

10h

Two-Plane Copy-Back Program

(3)

85h---11h

81h---10h

Block Erase

60h

D0h

Two-Plane Block Erase

60h---60h

D0h

Random Data Input

(1)

85h

Random Data Output

(1)

05h

E0h

Read Status

70h

Read EDC Status

(2)

7Bh

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions otherwise noted.)

NOTE : 1. V

can undershoot to -0.4V and V

can overshoot to V

+0.4V for durations of 20 ns or less.

2. Typical value is measured at Vcc=3.3V, T

=25

°C. Not 100% tested.

3. The typical value of the K9K8G08U1A's

is 20

µA

and the maximum value is 100

µA.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Operating

Current

Page Read with
Serial Access

tRC=25ns
CE=V

IL,

OUT

=0mA

Program

Erase

Stand-by Current(TTL)

CE=V

, WP=0V/V

Stand-by Current(CMOS)

CE=V

-0.2, WP=0V/V

µA

Input Leakage Current

=0 to Vcc(max)

±10

Output Leakage Current

OUT

=0 to Vcc(max)

±10

Input High Voltage

(1)

0.8xVcc

Vcc+0.3

Input Low Voltage, All inputs

(1)

-0.3

0.2xVcc

Output High Voltage Level

=-400

µA

2.4

Output Low Voltage Level

=2.1mA

0.4

Output Low Current(R/B)

(R/B)

=0.4V

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9XXG08UXA-XCB0

=0 to 70

°C, K9XXG08UXA-XIB0

=-40 to 85

°C)

Parameter

Symbol

Min

Typ.

Max

Unit

Supply Voltage

2.7

3.3

3.6

Supply Voltage

ABSOLUTE MAXIMUM RATINGS

NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V

+0.3V which, during transitions, may overshoot to V

+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter

Symbol

Rating

Unit

Voltage on any pin relative to VSS

-0.6 to +4.6

I/O

-0.6 to Vcc + 0.3 (< 4.6V)

Temperature Under Bias

K9XXG08UXA-XCB0

BIAS

-10 to +125

°C

K9XXG08UXA-XIB0

-40 to +125

Storage Temperature

K9XXG08UXA-XCB0

STG

-65 to +150

°C

K9XXG08UXA-XIB0

Short Circuit Current

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

CAPACITANCE

(

=25

°C, V

=3.3V, f=1.0MHz)

NOTE : Capacitance is periodically sampled and not 100% tested.

Item

Symbol

Test Condition

Min

Max

Unit

Input/Output Capacitance

I/O

=0V

Input Capacitance

=0V

VALID BLOCK

NOTE :
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is

presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-
gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.
* : Each K9F4G08U0A chip in the K9K8G08U1A has Maximun 80 invalid blocks.

Parameter

Symbol

Min

Typ.

Max

Unit

K9F4G08U0A

4,016

4,096

Blocks

K9K8G08U1A

8,032*

8,192*

Blocks

AC TEST CONDITION

(K9XXG08UXA-XCB0 :T

=0 to 70

°C, K9XXG08UXA-XIB0:T

=-40 to 85

°C, K9XXG08UXA: Vcc=2.7V~3.6V unless otherwise noted)

Parameter

K9XXG08UXA

Input Pulse Levels

0V to Vcc

Input Rise and Fall Times

5ns

Input and Output Timing Levels

Vcc/2

Output Load

1 TTL GATE and CL=50pF

MODE SELECTION

NOTE : 1. X can be V

or V

IH.

2. WP should be biased to CMOS high or CMOS low for standby.

CLE

ALE

Mode

Read Mode

Command Input

Address Input(5clock)

Write Mode

Command Input

Address Input(5clock)

Data Input

Data Output

During Read(Busy)

During Program(Busy)

During Erase(Busy)

(1)

Write Protect

0V/V

(2)

Stand-by

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

AC Timing Characteristics for Command / Address / Data Input

NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle

Parameter

Symbol

Min

Max

Unit

CLE Setup Time

CLS

(1)

CLE Hold Time

CLH

CE Setup Time

(1)

CE Hold Time

WE Pulse Width

ALE Setup Time

ALS

(1)

ALE Hold Time

ALH

Data Setup Time

(1)

Data Hold Time

Write Cycle Time

WE High Hold Time

Address to Data Loading Time

ADL

(2)

Program / Erase Characteristics

NOTE : 1. Typical value is measured at Vcc=3.3V, T

=25

°C. Not 100% tested.

2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25

C temperature

Parameter

Symbol

Min

Typ

Max

Unit

Program Time

PROG

200

700

µs

Dummy Busy Time for Two-Plane Page Program

DBSY

0.5

µs

Number of Partial Program Cycles

Nop

cycles

Block Erase Time

BERS

1.5

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

AC Characteristics for Operation

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5

Parameter

Symbol

Min

Max

Unit

Data Transfer from Cell to Register

µs

ALE to RE Delay

CLE to RE Delay

CLR

Ready to RE Low

RE Pulse Width

WE High to Busy

100

Read Cycle Time

RE Access Time

REA

CE Access Time

CEA

RE High to Output Hi-Z

RHZ

100

CE High to Output Hi-Z

CHZ

RE High to Output Hold

RHOH

RE Low to Output Hold

RLOH

CE High to Output Hold

COH

RE High Hold Time

REH

Output Hi-Z to RE Low

RE High to WE Low

RHW

100

WE High to RE Low

WHR

Device Resetting Time(Read/Program/Erase)

RST

5/10/500

(1)

µs

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

NAND Flash Technical Notes

Identifying Initial Invalid Block(s)

Initial Invalid Block(s)

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)
have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)
does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-
sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on
00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit

/512Byte

ECC.

All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-
tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in
most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the
initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following
suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.

Check "FFh" at the column address 2048

Figure 3. Flow chart to create initial invalid block table

Start

Set Block Address = 0

Check "FFh"

Increment Block Address

Last Block ?

End

Yes

Create (or update)

Initial

of the 1st and 2nd page in the block

Invalid Block(s) Table

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

NAND Flash Technical Notes

(Continued)

Program Flow Chart

Start

I/O 6 = 1 ?

I/O 0 = 0 ?

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

Program Completed

or R/B = 1 ?

Program Error

Yes

: If program operation results in an error, map out
the block including the page in error and copy the

target data to another block.

Error in write or read operation

Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be
reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode

Detection and Countermeasure sequence

Write

Erase Failure

Status Read after Erase --> Block Replacement

Program Failure

Status Read after Program --> Block Replacement

Read

Single Bit Failure

Verify ECC -> ECC Correction

ECC

: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Erase Flow Chart

Start

I/O 6 = 1 ?

I/O 0 = 0 ?

Write 60h

Write Block Address

Write D0h

Read Status Register

or R/B = 1 ?

Erase Error

Yes

: If erase operation results in an error, map out

the failing block and replace it with another block.

Erase Completed

Yes

Read Flow Chart

Start

Verify ECC

Write 00h

Write Address

Read Data

ECC Generation

Reclaim the Error

Page Read Completed

Yes

NAND Flash Technical Notes

(Continued)

Write 30h

Block Replacement

* Step1
When an error happens in the nth page of the Block 'A' during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B')
* Step3
Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'.
* Step4
Do not erase or program to Block 'A' by creating an 'invalid block' table or other appropriate scheme.

Buffer memory of the controller.

1st

Block A

Block B

(n-1)th
nth

(page)

{

1st

(n-1)th
nth

(page)

{

an error occurs.

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

NAND Flash Technical Notes

(Continued)

Copy-Back Operation with EDC & Sector Definition for EDC

Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source
page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate
bit errors.
K9F4G08U0A supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation
should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input
before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial
modification smaller than a sector corrupts the on-chip EDC codes.
A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte
spare area.

"A" area

512 Byte

(1'st sector)

"H" area

(4'th sector)

Main Field (2,048 Byte)

16 Byte

"G" area

(3'rd sector)

16 Byte

"F" area

(2'nd sector)

16 Byte

"E" area

(1'st sector)

16 Byte

"B" area

512 Byte

(2'nd sector)

"C" area

512 Byte

(3'rd sector)

"D" area

512 Byte

(4'th sector)

Spare Field (64 Byte)

Table 2. Definition of the 528-Byte Sector

Sector

Main Field (Column 0~2,047)

Spare Field (Column 2,048~2,111)

Area Name

Column Address

Area Name

Column Address

1'st 528-Byte Sector

"A"

0 ~ 511

"E"

2,048 ~ 2,063

2'nd 528-Byte Sector

"B"

512 ~ 1,023

"F"

2,064 ~ 2,079

3'rd 528-Byte Sector

"C"

1,024 ~ 1,535

"G"

2,080 ~ 2,095

4'th 528-Byte Sector

"D"

1,536 ~ 2,047

"H"

2,096 ~ 2,111

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-
nificant bit) pages of the block. Random page address programming is prohibited.

From the LSB page to MSB page

DATA IN: Data (1)

Data (64)

(1)

(2)

(3)

(32)

(64)

Data register

Page 0

Page 1

Page 2

Page 31

Page 63

Ex.) Random page program (Prohibition)

DATA IN: Data (1)

Data (64)

(2)

(32)

(3)

(1)

(64)

Data register

Page 0

Page 1

Page 2

Page 31

Page 63

Addressing for program operation

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

System Interface Using CE don't-care.

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of

µ-seconds, de-activating CE during the data-loading and serial access

would provide significant savings in power consumption.

Figure 4. Program Operation with CE don't-care.

Address(5Cycles)

80h

Data Input

CLE

ALE

Data Input

CE don't-care

10h

Address(5Cycle)

00h

CLE

ALE

Data Output(serial access)

CE don't-care

R/B

CEA

out

REA

I/O

Figure 5. Read Operation with CE don't-care.

30h

I/Ox

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Command Latch Cycle

CLE

ALE

Command

Address Latch Cycle

CLS

CLH

ALS

ALH

NOTE

Device

I/O

DATA

ADDRESS

I/Ox

Data In/Out

Col. Add1

Col. Add2

Row Add1

Row Add2

Row Add3

K9F4G08U0A

I/O 0 ~ I/O 7

2,112byte

A0~A7

A8~A11

A12~A19

A20~A27

A28~A29

I/Ox

CLE

ALE

Col. Add1

ALS

ALH

ALS

ALH

ALS

ALH

ALS

I/Ox

Col. Add2

Row Add1

Row Add2

ALH

ALS

Row Add3

ALH

CLS

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Status Read Cycle & EDC Status Read Cycle

CLE

70h or 7Bh

Status Output

CLR

CLH

REA

RHOH

COH

WHR

CEA

CLS

I/Ox

CHZ

RHZ

R/B

I/Ox

CEA

REA

REH

RHZ

CHZ

Serial Access Cycle after Read

(EDO Type, CLE=L, WE=H, ALE=L)

RHOH

COH

RLOH

Dout

REA

NOTES : Transition is measured at

±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.
tRLOH is valid when frequency is higher than 33MHz.
tRHOH starts to be valid when frequency is lower than 33MHz.

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

ge Program Operation with Rand

om Dat

a
In

put

CLE

R/B

ALE

I/O

10h

ri
al

a
ta

I
npu

t Command

Col

u
mn A

ddr

ess

Addr

ess

Ser

i
al

I
nput

ogr

a
n
d

ad Stat

a
n
d

Rand

om Da

I
nput

a
n
d

Col

u
mn Ad

dre

s
s

Din

Ser

i
al

put

I
/Ox

Col

.
A

dd1

Col

.
A

dd2

Row Add1

Row Add2

Col

.
A

dd1

Col

.
A

dd2

Row A

d
d
3

NOTES

.

tA

is t

h
e

tim

r
i
si

ng edge

fin

l addr

ess cycle

t
o

r
i
sing edge

o
f
fi

rst dat

a cycle.

ADL

For EDC

o
perat

ion

,
onl

y one

t
i
me ran

dom dat

a input

ssib

le at t

he sa

me addre

s
s.

ADL

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Copy

-Ba

ck Program Operation

i
th

ndom Dat

a
Input

CLE

R/B

ALE

I/
O

Colu

d
dr

ess

o
w A

d
dr

t
at

Com

a
n
d

I/O

=
0
Succe

ssf

I/O

r i

n
Pro

g
r
a
m

PROG

Busy

Cop

y
-Back

Dat

I
n
pu

t C

o
mma

Colu

n
A

d
dr

ess

w Ad

dress

a
ta

Dat

a
N

I
/Ox

l
A

d
d
1

l A

d
d
2

w A

d
d
1

w A

d
d
2

l
A

d
d
1

l A

d
d
2

w A

d
d
1

w A

d
d
2

w A

d
d
3

w A

d
d
3

h
/70

I/O

1 ~

I/
O

:
ED

C St

u
s
(
7
Bh

)

TES :

DL is t

he ti

f
r
om t

he WE

rising edge of

final address

cycle t

o

the WE

rising

i
rst

cycl

ADL

o
r

erat

ion

,
only one

t
i
me rand

om dat

i
nput

is po

ssibl

a
t
t
he sa

a
ddre

s
s.

WHR

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

T
w

-
Pl

ane Page

Program

Ope

r
a
t
ion

80h

I/
O

R/B

11h

o-P

l
a
n

e
Pa

r
o

DBS

Addr

ess & Dat

Inp

dress &

Dat

I
nput

PRO

Col Add1

,2 & Row Add 1,

2
112 Byt

CLE

R/B

ALE

80h

n N

11h

e
r
i
al Data

Input Com

and

o
l
u
mn A

d
dr

P
r
ogr

Comm

and

(Dum

y
)

10h

tPROG

I/
O

Pro

g
ra

m Co

n
f
ir
m

C
o
mma

(Tr

ue)

70h

Page Row Add

r
es

I
/Ox

1 u

t
o

Byt

Ser

i
al

I
n

Read Statu

s
Command

DBSY

p. 500ns

a
x. 1

µ
s

l
A

d
d1

Col

Add2

R
o
w A

d
d1

Row A

dd2

A
d
d
3

C
o
l
Add1

Col

dd2

Row A

d
d1

Row

d
d2

w A

d
d3

l
A

dd1,

2 & Row

dd 1,

2,3

12 Byte

Dat

11 :

lid

7
:

Fixe

d 'Low'

Fixed 'Lo

Fixed 'Low'

Valid

lid

Fixed 'High

lid

Not

e
:
Any command betwe

en 1

1h and

81h is pr

ohib

i
ted except 70h an

d FF

Note

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

T
w

-
Pl

ane Block

Eras

e Op

eration

ock Era

s
e

S

p C

o
mmand1

ase Co

nfi

rm Co

a
n

ad St

atu

Comman

Row Add1

I/O

R/B

~ A

BERS

Ex.) Add

r
es

s Restriction

r Tw

o-Plan

e Blo

c
k

Era

se Op

atio

CLE

R/B

I/
O

ALE

w Ad

D0h

O 0

Busy

BERS

7
0h

s
s

r
e

o
w Ad

d1,

I
/
O

sfu

l
E

r
as

= 1

rror

ase

w Ad

Row

Fixe

d 'Low'

Fixed 'Lo

i
xe

'
Low'

Fixed 'Low'

Fixed

'High

Vali

Row A

d
d

D0h

Row

w A

d
d

Row Add

r
ess

l
ock

r
ase Set

up Command

Row Add

r
ess

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

4th ID Data

Description

I/O7

I/O6

I/O5 I/O4

I/O3

I/O2

I/O1 I/O0

Page Size
(w/o redundant area )

1KB
2KB
4KB
8KB

0 0
0 1
1 0
1 1

Block Size
(w/o redundant area )

64KB
128KB
256KB
512KB

0 0
0 1
1 0
1 1

Redundant Area Size
( byte/512byte)

8
16

0
1

Organization

x8
x16

0
1

Serial Access Minimum

50ns/30ns
25ns
Reserved
Reserved

0
1
0
1

0
0
1
1

ID Definition Table

90 ID : Access command = 90H

Description

Byte

Maker Code
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc
Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum
Plane Number, Plane Size

3rd ID Data

Description

I/O7

I/O6

I/O5 I/O4

I/O3 I/O2

I/O1 I/O0

Internal Chip Number

1
2
4
8

0 0
0 1
1 0
1 1

Cell Type

2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell

0 0
0 1
1 0
1 1

Number of
Simultaneously
Programmed Pages

1
2
4
8

0 0
0 1
1 0
1 1

Interleave Program
Between multiple chips

Not Support
Support

0
1

Cache Program

Not Support
Support

0
1

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Device Operation

PAGE READ

Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data
within the selected page are transferred to the data registers in less than 20

µs(t

). The system controller can detect the completion of

this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read
out in 25ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.

Figure 6. Read Operation

Address(5Cycle)

00h

Col. Add.1,2 & Row Add.1,2,3

Data Output(Serial Access)

Data Field

Spare Field

CLE

ALE

R/B

30h

I/Ox

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Figure 7. Random Data Output In a Page

Address

00h

Data Output

R/B

30h

Address

05h

E0h

5Cycles

2Cycles

Data Output

Data Field

Spare Field

Data Field

Spare Field

I/Ox

Col. Add.1,2 & Row Add.1,2,3

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive
bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential
order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into
the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector
and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-
ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-
gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.

Figure 8. Program & Read Status Operation

80h

R/B

Address & Data Input

I/O0

Pass

Data

10h

70h

Fail

PROG

I/Ox

Col. Add.1,2 & Row Add.1,2,3

"0"

"1"

Col. Add.1,2

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Figure 9. Random Data Input In a Page

80h

R/B

Address & Data Input

I/O0

Pass

10h

70h

Fail

PROG

85h

Address & Data Input

I/Ox

Col. Add.1,2 & Row Add1,2,3

Col. Add.1,2

Data

"0"

"1"

Copy-Back Program

The Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-
efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-
ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves
the whole 2,112-byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input com-
mand (85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to
actually begin the programming operation. During tPROG, the device executes EDC of itself. Once the program process starts, the
Read Status Register command (70h) or Read EDC Status command (7Bh) may be entered to read the status register. The system
controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register.
When the Copy-Back Program is complete, the Write Status Bit(I/O 0) and EDC Status Bits (I/O 1 ~ I/O 2) may be checked(Figure 10
& Figure 11& Figure 12). The internal write verification detects only errors for "1"s that are not successfully programmed to "0"s and
the internal EDC checks whether there is only 1-bit error for each 528-byte sector of the source page. More than 2-bit error detection
is not available for each 528-byte sector. The command register remains in Read Status command mode or Read EDC Status com-
mand mode until another valid command is written to the command register.
During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11. But EDC
status bits are not available during copy back for some bits or bytes modified by Random Data Input operation.
However, in case of the 528 byte sector unit modification, EDC status bits are available.

Figure 10. Page Copy-Back Program Operation

00h

R/B

Add.(5Cycles)

I/O0

Pass

85h

70h/7Bh

Fail

PROG

Add.(5Cycles)

Source Address

Destination Address

35h

10h

I/Ox

Col. Add.1,2 & Row Add.1,2,3

Figure 11. Page Copy-Back Program Operation with Random Data Input

00h

R/B

Add.(5Cycles)

85h

70h

PROG

Add.(5Cycles)

Source Address

Destination Address

Data

35h

10h

85h

Data

Add.(2Cycles)

There is no limitation for the number of repetition.

I/Ox

Col. Add.1,2 & Row Add.1,2,3

Col. Add.1,2

Note: 1. For EDC operation, only one time random data input is possible at the same address.

Note

1. Copy-Back Program operation is allowed only within the same memory plane.

"0"

"1"

Note: 1. For EDC operation, only one time random data input is possible at the same address.

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Figure 12. Page Copy-Back Program Operation with EDC & Read EDC Status

00h

R/B

Add.(5Cycles)

85h

7Bh

PROG

Add.(5Cycles)

Source Address

Destination Address

35h

10h

I/Ox

Col. Add.1,2 & Row Add.1,2,3

EDC Status Output

Figure 13. Block Erase Operation

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A

to A

is valid while A

to A

is ignored. The Erase Confirm command(D0h) following the block

address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.

60h

Row Add 1,2,3

R/B

Address Input(3Cycle)

I/O0

Pass

D0h

70h

Fail

BERS

I/Ox

"0"

"1"

EDC OPERATION

Note that for the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during
Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data
input at the same address.

Two-Plane Page Program

Two-Plane Page Program is an extension of Page Program, for a single plane with 2112 byte page registers. Since the device is
equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two
pages.
After writing the first set of data up to 2112 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved,
R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device
returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the
81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy
Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the
same as that of Page Program. Althougth two planes are programmed simultaneously, pass/fail is not available for each page when
the program operation completes. Status bit of I/O 0 is set to "1" when any of the pages fails.
Restriction in addressing with Two-Plane Page Program is shown is Figure14.

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Figure 14. Two-Plane Page Program

80h

11h

Data

Input

Plane 0

(2048 Block)

Block 0
Block 2

Block 4094

Block 4092

80h

I/O

0 ~ 7

R/B

Address & Data Input

11h

81h

10h

DBSY

PROG

70h

Address & Data Input

NOTE :1. It is noticeable that same row address except for A

is applied to the two blocks

81h

10h

Plane 1

(2048 Block)

Block 1
Block 3

Block 4095

Block 4093

Figure 15. Two-Plane Block Erase Operation

60h

I/O

R/B

60h

D0h

I/O0

Pass

Fail

BERS

Address (3 Cycle)

70h

"0"

"1"

~ A

17 :

Fixed 'Low'

18 :

Fixed 'Low'

~ A

29 :

Fixed 'Low'

~ A

17 :

Fixed 'Low'

18 :

Fixed 'High'

~ A

29 :

valid

Two-Plane Block Erase

Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by
three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane.
The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/
Busy status bit (I/O 6).

~ A

11 :

Valid

~ A

17 :

Fixed 'Low'

18 :

Fixed 'Low'

~ A

29 :

Fixed 'Low'

~ A

11 :

Valid

~ A

17 :

Valid

18 :

Fixed 'High'

~ A

29 :

Valid

2. Any command between 11h and 81h is prohibited except 70h and FFh.

Note*

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Figure 16. Two-Plane Copy-Back Program Operation

R/B

85h

70h

PROG

Add.(5Cycles)

Destination Address

10h

I/Ox

Col. Add.1,2 & Row Add.1,2,3

81h

Add.(5Cycles)

Destination Address

Col. Add.1,2 & Row Add.1,2,3

00h

R/B

Add.(5Cycles)

Source Address On Plane0

35h

I/Ox

Col. Add.1,2 & Row Add.1,2,3

00h

Add.(5Cycles)

Source Address On Plane1

35h

Col. Add.1,2 & Row Add.1,2,3

11h

DBSY

Two-Plane Copy-Back Program

Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2112 byte page registers. Since the
device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous program-
ming of two pages.

Data Field

Spare Field

Data Field

Spare Field

(1)

(2)

(3)

Plane0

Plane1

Source page

Target page

Source page

Target page

(1) : Read for Copy Back On Plane0

(2) : Read for Copy Back On Plane1

(3) : Two-Plane Copy-Back Program

~ A

11 :

Fixed 'Low'

~ A

17 :

Fixed 'Low'

18 :

Fixed 'Low'

~ A

29 :

Fixed 'Low'

~ A

11 :

Fixed 'Low'

~ A

17 :

Valid

18 :

Fixed 'High'

~ A

29 :

Valid

Note

1. Copy-Back Program operation is allowed only within the same memory plane.

Any command between 11h and 81h is prohibited except 70h and FFh.

Note3

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

R/B

85h

11h

DBSY

Add.(5Cycles)

Data

85h

Data

I/Ox

Col. Add.1,2 & Row Add.1,2,3

Col. Add.1,2

Add.(2Cycles)

00h

R/B

Add.(5Cycles)

Source Address On Plane0

35h

I/Ox

Col. Add.1,2 & Row Add.1,2,3

00h

Add.(5Cycles)

Source Address On Plane1

35h

Col. Add.1,2 & Row Add.1,2,3

R/B

81h

10h

PROG

Add.(5Cycles)

Data

85h

Data

I/Ox

Col. Add.1,2 & Row Add.1,2,3

Col. Add.1,2

Add.(2Cycles)

Destination Address

~ A

11 :

Valid

~ A

17 :

Fixed 'Low'

18 :

Fixed 'Low'

~ A

29 :

Fixed 'Low'

Destination Address

~ A

11 :

Valid

~ A

17 :

Valid

18 :

Fixed 'High'

~ A

29 :

Valid

Figure 17. Two-Plane Copy-Back Program Operation with Random Data Input

Note

1. Copy-Back Program operation is allowed only within the same memory plane.

2. On the same plane, It's prohibited to operate copy-back program from an odd address page(source page) to an even
address page(target page) or from an even address page(source page) to an odd address page(target page).
Therefore, the copy-back program is permitted just between odd address pages or even address pages.
3. EDC status Bits are not available during copy back for some bits or bytes modified by Random Data Input operation.
In case of the 528 byte plane unit modification, EDC status bits are available.

Any command between 11h and 81h is prohibited except 70h and FFh.

Note4

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to Table 3 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.

Table 3. Status Register Definition for 70h Command

NOTE :

1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.

I/O

Page Program

Block Erase

Read

Definition

I/O 0

Pass/Fail

Not use

Pass : "0" Fail : "1"

I/O 1

Not use

Don't -cared

I/O 2

Not use

Don't -cared

I/O 3

Not Use

Don't -cared

I/O 4

Not Use

Don't -cared

I/O 5

Not Use

Don't -cared

I/O 6

Ready/Busy

Busy : "0" Ready : "1"

I/O 7

Write Protect

Protected : "0" Not Protected : "1"

READ EDC STATUS

Read EDC status operation is only available on 'Copy Back Program'. The device contains an EDC Status Register which may be
read to find out whether there is error during 'Read for Copy Back'. After writing 7Bh command to the command register, a read cycle
outputs the content of the EDC Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line
control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired.
RE or CE does not need to be toggled for updated status. Refer to Table 4 for specific Status Register definitions. The command reg-
ister remains in EDC Status Read mode until further commands are issued to it.

Table 4. Status Register Definition for 7Bh Command

NOTE :

1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.

2. More than 2-bit error detection isn't available for each 528 Byte sector.
That is to say, only 1-bit error detection is avaliable for each 528 Byte sector.

I/O

Copy Back Program

Page Program Block Erase

Read

Definition

I/O 0

Pass/Fail of Copy Back Program

Pass/Fail

Not use

Pass : "0", Fail : "1"

I/O 1

EDC Status

Not use

No Error : "0", Error : "1"

I/O 2

Validity of EDC Status

Not use

Valid : "1", Invalid : "0"

I/O 3

Not Use

Don't -cared

I/O 4

Not Use

Don't -cared

I/O 5

Not Use

Don't -cared

I/O 6 Ready/Busy of Copy Back Program

Ready/Busy

Ready/Busy Busy : "0", Ready : "1"

I/O 7 Write Protect of Copy Back Program

Write Protect

Write Protect Protected : "0", Not Protected :"1"

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Figure 18. Read ID Operation

CLE

I/O

ALE

90h

00h

Address. 1cycle

Maker code

Device code

CEA

REA

Read ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence.

Figure 19. RESET Operation

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be
accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 19
below.

FFh

I/O

R/B

RST

WHR

CLR

Device

Device Code (2nd Cycle)

3rd Cycle

4th Cycle

5th Cycle

K9F4G08U0A

DCh

10h

95h

54h

K9K8G08U1A

Same as each K9F4G08U0A in it

Device

4th Cyc.

Code

ECh

3rd Cyc.

5th Cyc.

Table 5. Device Status

After Power-up

After Reset

Operation mode

00h Command is latched

Waiting for next command

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.20). Its value can be
determined by the following guidance.

R/B

open drain output

Device

GND

t
r
,
t
f [s

]

Ibusy [A]

Rp(ohm)

Figure 20. Rp vs tr ,tf & Rp vs ibusy

Ibusy

ibusy

Busy

Ready Vcc

@ Vcc = 3.3V, Ta = 25

°C , C

= 50pF

VOH

50n

100n

150n

100

150

200

1.8

2.4

1.2

0.8

0.6

VOL

where I

is the sum of the input currents of all devices tied to the R/B pin.

Rp value guidance

Rp(max) is determined by maximum permissible limit of tr

Rp(min, 3.3V part) =

(Max.) - V

(Max.)

3.2V

8mA

3.3V device - V

: 0.4V, V

: 2.4V

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Data Protection & Power up sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V

during power-up and power-down. A recovery time of minimum 100

µs is required before internal circuit gets ready for any command

sequences as shown in Figure 21. The two step command sequence for program/erase provides additional software protection.

Figure 21. AC Waveforms for Power Transition

High

3.3V device : ~ 2.5V

100

µs

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K9F4G08U0A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: K9F4G08U0A