FLASH MEMORY
1
K9F6408U0C
K9F6408Q0C
Document Title
8M x 8 Bit NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the
SAMSUNG branch office near you.
Revision No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Remark
Advance
Preliminary
History
Initial issue.
1. I
OL
(R/B) of 1.8V device is changed.
-min. Value: 7mA -->3mA
-typ. Value: 8mA -->4mA
2. Package part number is modified.
K9F6408U0C-Y ---> K9F6408U0C_T
3. AC parameter is changed.
tRP(min.) : 30ns --> 25ns
1. TBGA package is changed.
- 9mmX11mm 63ball TBGA ---> 6mmX8.5mm 48ball TBGA
2. Part number(TBGA package part number) is changed
- K9F6408Q0C-D ----> K9F6408Q0C-B
- K9F6408U0C-D -----> K9F6408U0C-B
3. K9F6408U0C-BCB0,BIB0 products are added
1. WSOP1 package is added.
- Part number : K9F6408U0C_VCB0,VIBO
1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 28)
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 29)
The min. Vcc value 1.8V devices is changed.
K9F64XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V
Pb-free Package is added.
K9F6408U0C-QCB0,QIB0
K9F6408U0C-HCB0,HIB0
K9F6408Q0C-HCB0,HIB0
K9F6408U0C-FCB0,FIB0
Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
Draft Date
Jul. 24 . 2001
Nov. 5 . 2001
Nov. 12 . 2001
Mar. 13 . 2002
Nov, 21th 2002
Mar. 5th 2003
Mar. 13 . 2003
Jul. 4th. 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
FLASH MEMORY
2
K9F6408U0C
K9F6408Q0C
GENERAL DESCRIPTION
FEATURES
Voltage Supply
- 1.8V device(K9F6408Q0C) : 1.70~1.95V
- 3.3V device(K9F6408U0C) : 2.7 ~ 3.6 V
Organization
- Memory Cell Array : (8M + 256K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (8K + 256)Byte
528-Byte Page Read Operation
- Random Access : 10
s(Max.)
- Serial Page Access
- 1.8V device(K9F6408Q0C) : 50ns
- 3.3V device(K9F6408U0C) : 50ns
Fast Write Cycle Time
- Program Time
- 1.8V device(K9F6408Q0C) : 200
s(Typ.)
- 3.3V device(K9F6408U0C) : 200
s(Typ.)
- Block Erase Time : 2ms(Typ.)
8M x 8 Bit Bit NAND Flash Memory
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Command Register Operation
Package
- K9F6408U0C-TCB0/TIB0 :
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
- K9F6408Q0C-BCB0/BIB0
48- Ball TBGA ( 6 x 8.5 /0.8mm pitch , Width 1.0 mm)
- K9F6408U0C-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)
- K9F6408U0C-QCB0/QIB0 : Pb-free Package
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
- K9F6408Q0C-HCB0/HIB0 : Pb-free Package
48- Ball TBGA ( 6 x 8.5 /0.8mm pitch , Width 1.0 mm)
- K9F6408U0C-FCB0/FIB0 : Pb-free Package
48 - Pin WSOP I (12X17X0.7mm)
* K9F6408U0C-V,F(WSOPI ) is the same device as
K9F6408U0C-T,Q(TSOPII) except package type.
The K9F6408X0C is a 8M(8,388,608)x8bit NAND Flash Memory with a spare 256K(262,144)x8bit. The device is offered in 1.8V or
3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation pro-
grams the 528-byte page in typical 200
s and an erase operation can be performed in typical 2ms on an 8K-byte block. Data in the
page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as com-
mand inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and
internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F6408X0C
s extended reli-
ability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. These algo-
rithms have been implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512
bytes can be utilized by system-level ECC. The K9F6408X0C is an optimum solution for large nonvolatile storage applications such
as solid state file storage, digital voice recorder, digital still camera and other portable applications requiring non-volatility.
PRODUCT LIST
Part Number
Vcc Range
Organization
PKG Type
K9F6408Q0C-B,H
1.70 ~ 1.95V
X8
TBGA
K9F6408U0C-B,H
2.7 ~ 3.6V
K9F6408U0C-T,Q
TSOP II
K9F6408U0C-V,F
WSOP I
FLASH MEMORY
3
K9F6408U0C
K9F6408Q0C
PIN CONFIGURATION (TSOP II )
K9F6408U0C-TCB0,QCB0/TIB0,QIB0
PACKAGE DIMENSIONS
V
SS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
CC
I/O4
I/O5
I/O6
I/O7
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
V
CC
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Unit :mm/Inch
0~8
0
.
0
0
2
0.805
#1
44(40) LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II)
0
.
0
5
#22(20)
#44(40)
#23(21)
0.032
0.35
0.10
0.014
0.004
0.80
0.0315
M
i
n
.
0
.
0
4
7
1
.
2
0
M
a
x
.
0.741
18.81
Max.
18.41
0.10
0.725
0.004
+0.10
-0.05
+0.004
-0.002
0.15
0.006
1
0
.
1
6
0
.
4
0
0
44(40) - TSOP II - 400F
0.10
0.004
0.50
0.020
0.25
0.010 TYP
0
.
4
5
~
0
.
7
5
0
.
0
1
8
~
0
.
0
3
0
0
.
0
3
9
0
.
0
0
4
1
.
0
0
0
.
1
0
MAX
1
1
.
7
6
0
.
2
0
0
.
4
6
3
0
.
0
0
8
(
)
FLASH MEMORY
4
K9F6408U0C
K9F6408Q0C
K9F6408X0C-BCB0,HCB0/BIB0,HIB0
PIN CONFIGURATION (TBGA)
PACKAGE DIMENSIONS
WP
ALE
WE
R/B
N.C
RE
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O
0
N.C
N.C
N.C
V
CC
I/O
1
N.C
V
CC
Q
I/O
5
V
SS
I/O
2
I/O
3
I/O
4
I/O
6
V
SS
1
2
3
4
5
6
A
B
C
D
E
F
G
H
CE
CLE
N.C
N.C
N.C
I/O
7
6.00
0.10
6.00
0.10
Ball #A1
Side View
Top View
48-Ball TBGA (measured in millimeters)
0
.
3
2
0
.
0
5
0.45
0.05
6
5
4
3
2
1
C
D
E
F
G
H
Bottom View
A
B
8
.
5
0
0
.
1
0
48-
0.45
0.05
0
.
8
0
x
7
=
5
.
6
0
0
.
8
0
8
.
5
0
0
.
1
0
0.80 x5= 4.00
0.80
0
.
9
0
0
.
1
0
0.08MAX
B
A
2
.
8
0
2.00
6.00
0.10
(Datum B)
(Datum A)
0.20
M
A B
(Top View)
FLASH MEMORY
5
K9F6408U0C
K9F6408Q0C
PIN CONFIGURATION (WSOP1)
K9F6408U0C-VCB0,FCB0/VIB0,FIB0
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F
Unit :mm
15.40
0.10
#1
#24
0
.
2
0
+
0
.
0
7
-
0
.
0
3
0
.
1
6
+
0
.
0
7
-
0
.
0
3
0
.
5
0
T
Y
P
(
0
.
5
0
0
.
0
6
)
#48
#25
1
2
.
0
0
0
.
1
0
0
.
1
0
+
0
.
0
7
5
-
0
.
0
3
5
0.58
0.04
0.70 MAX
(0.1Min)
17.00
0.20
0
~8
0.45~0.75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
CE
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
FLASH MEMORY
6
K9F6408U0C
K9F6408Q0C
PIN DESCRIPTION
Pin Name
Pin Function
I/O
0
~ I/O
7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during read
operation, refer to 'Page read' section of Device operation .
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
V
CC
Q is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
V
CC
is the power supply for device.
Vss
GROUND
N.C
NO CONNECTION
Lead is not internally connected.
GND
GND INPUT FOR ENABLING SPARE AREA
To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state .
DNU
DO NOT USE
Leave it disconnected.
NOTE : Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
FLASH MEMORY
7
K9F6408U0C
K9F6408Q0C
512Byte
16 Byte
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Figure 2. ARRAY ORGANIZATION
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A
8
is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
2nd Cycle
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
3rd Cycle
A
17
A
18
A
19
A
20
A
21
A
22
*L
*L
V
CC
X-Buffers
Y-Gating
64M + 2M Bit
Command
2nd half Page Register & S/A
NAND Flash
ARRAY
(512 + 16)Byte x 16384
Y-Gating
1st half Page Register & S/A
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
V
SS
A
9
- A
22
A
0
- A
7
Command
CE
RE
WE
CLE
WP
I/0 0
I/0 7
V
SS
A
8
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
16K Pages
(=1,024 Blocks)
512 Byte
8 bit
16 Byte
1 Block =16 Pages
= (8K + 256) Byte
I/O 0 ~ I/O 7
1 Page = 528 Byte
1 Block = 528 Byte x 16 Pages
= (8K + 256) Byte
1 Device = 528 Byte x 16Pages x 1024 Blocks
= 66 Mbits
Column Address
Row Address
(Page Address)
Page Register
ALE
Vcc/V
CC
Q
FLASH MEMORY
8
K9F6408U0C
K9F6408Q0C
PRODUCT INTRODUCTION
The K9F6408X0C is a 66Mbit(69,206,016 bit) memory organized as 16,384 rows(pages) by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND struc-
tured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in
Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis.
The memory array consists of 1024 separately erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on
the K9F6408X0C.
The K9F6408X0C has addresses multiplexed into 8 I/O
s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O
s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 8M byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: column
address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles
following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F6408X0C.
Table 1. COMMAND SETS
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. The 50h command is valid only when the GND input(pin #40) is low level.
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 1
00h/01h
(1)
-
Read 2
50h
(2)
-
Read ID
90h
-
Reset
FFh
-
O
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
O
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
FLASH MEMORY
9
K9F6408U0C
K9F6408Q0C
ABSOLUTE MAXIMUM RATINGS
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins and -0.2V on Vcc and VccQ pins. During transitions, this level may undershoot to -2.0V for periods
<20ns. Maximum DC voltage on input/output pins is V
CCQ
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
K9F6408Q0C(1.8V)
K9F6408U0C(3.3V)
Voltage on any pin relative to V
SS
V
IN/OUT
-0.6 to + 2.45
-0.6 to + 4.6
V
V
CC
-0.2 to + 2.45
-0.6 to + 4.6
V
V
CC
Q
-0.2 to + 2.45
-0.6 to + 4.6
V
Temperature
Under Bias
K9F6408X0C-XCB0
T
BIAS
-10 to + 125
C
K9F6408X0C-XIB0
-40 to + 125
Storage Temperature
T
STG
-65 to + 150
C
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F6408X0C-XCB0:TA=0 to 70
C, K9F6408X0C-XIB0:TA=-40 to 85
C)
Parameter
Symbol
K9F6408Q0C(1.8V)
K9F6408U0C(3.3V)
Unit
Min
Typ.
Max
Min
Typ.
Max
Supply Voltage
V
CC
1.70
1.8
1.95
2.7
3.3
3.6
V
Supply Voltage
V
CC
Q
1.70
1.8
1.95
2.7
3.3
3.6
V
Supply Voltage
V
SS
0
0
0
0
0
0
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
Parameter
Symbol
Test Conditions
K9F6408Q0C(1.8V)
K9F6408U0C(3.3V)
Unit
Min
Typ
Max
Min
Typ
Max
Operat-
ing
Current
Sequential Read
I
CC
1
CE=V
IL,
I
OUT
=0mA
tRC=50ns
-
5
10
-
10
20
mA
Program
I
CC
2
-
-
8
15
-
10
20
Erase
I
CC
3
-
-
8
15
-
10
20
Stand-by Current(TTL)
I
SB
1
CE=V
IH
, WP=0V/V
CC
-
-
1
-
-
1
Stand-by Current(CMOS)
I
SB
2
CE=V
CC
-0.2, WP=0V/V
CC
-
10
50
-
10
50
A
Input Leakage Current
I
LI
V
IN
=0 to Vcc(max)
-
-
10
-
-
10
Output Leakage Current
I
LO
V
OUT
=0 to Vcc(max)
-
-
10
-
-
10
Input High Voltage
V
IH*
I/O pins
VccQ-0.4
VccQ
+0.3
2.0
-
V
CC
Q+0.3
V
Except I/O pins
V
CC
-0.4
-
VCC
+0.3
2.0
-
V
CC
+0.3
Input Low Voltage, All inputs
V
IL*
-
-0.3
-
0.4
-0.3
-
0.8
Output High Voltage Level
V
OH
K9F6408Q0C :I
OH
=-100
A
K9F6408U0C :I
OH
=-400
A
V
CC
Q-0.1
-
-
2.4
-
-
Output Low Voltage Level
V
OL
K9F6408Q0C :I
OL
=100uA
K9F6408U0C :I
OL
=2.1mA
-
-
0.1
-
-
0.4
Output Low Current(R/B)
I
OL
(R/B)
K9F6408Q0C :V
OL
=0.1V
K9F6408U0C :V
OL
=0.4V
3
4
-
8
10
-
mA
FLASH MEMORY
10
K9F6408U0C
K9F6408Q0C
MODE SELECTION
NOTE : 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
Mode
H
L
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input(3clock)
H
L
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input(3clock)
L
L
L
H
H
Data Input
L
L
L
H
X
Data Output
L
L
L
H
H
X
During Read(Busy) on K9F6408U0C_T,Q or K9F6408U0C_V,F
X
X
X
X
H
X
During Read(Busy) on the devices except K9F6408U0C_T,Q
and K9F6408U0C_V,F
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X
(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2)
Stand-by
CAPACITANCE
(
T
A
=25
C, V
CC
=1.8V/3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
VALID BLOCK
NOTE :
1. The
K9F6408X0C
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
. Do not erase or
program factory-marked bad blocks.
Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
1014
1020
1024
Blocks
AC TEST CONDITION
(K9F6408X0C-XCB0:TA=0 to 70
C, K9F6408X0C-XIB0:TA=-40 to 85
C
K9F6408Q0C: Vcc=1.70V~1.95V , K9F6408U0C: Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F6408Q0C
K9F6408U0C
Input Pulse Levels
0V to VccQ
0.4V to 2.4V
Input Rise and Fall Times
5ns
5ns
Input and Output Timing Levels
VccQ/2
1.5V
K9F6408Q0C:Output Load (VccQ:1.8V +/-10%)
K9F6408U0C:Output Load (VccQ:3.0V +/-10%)
1 TTL GATE and CL=30pF
1 TTL GATE and CL=50pF
K9F6408U0C:Output Load (VccQ:3.3V +/-10%)
-
1 TTL GATE and CL=100pF
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
-
200
500
s
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
-
2
cycles
Spare Array
-
-
3
cycles
Block Erase Time
t
BERS
-
2
3
ms
FLASH MEMORY
11
K9F6408U0C
K9F6408Q0C
AC Timing Characteristics for Command / Address / Data Input
NOTE :
1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
Parameter
Symbol
K9F6408Q0C
K9F6408U0C
Unit
Min
Max
Min
Max
CLE Set-up Time
t
CLS
0
-
0
-
ns
CLE Hold Time
t
CLH
10
-
10
-
ns
CE Setup Time
t
CS
0
-
0
-
ns
CE Hold Time
t
CH
10
-
10
-
ns
WE Pulse Width
t
WP
25
(1)
-
25
(1)
-
ns
ALE Setup Time
t
ALS
0
-
0
-
ns
ALE Hold Time
t
ALH
10
-
10
-
ns
Data Setup Time
t
DS
20
-
20
-
ns
Data Hold Time
t
DH
10
-
10
-
ns
Write Cycle Time
t
WC
50
-
50
-
ns
WE High Hold Time
t
WH
15
-
15
-
ns
AC Characteristics for Operation
NOTE :
1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
Parameter
Symbol
K9F6408Q0C
K9F6408U0C
Unit
Min
Max
Min
Max
Data Transfer from Cell to Register
t
R
-
10
-
10
s
ALE to RE Delay( ID read )
t
AR1
20
-
20
-
ns
ALE to RE Delay(Read cycle)
t
AR2
50
-
50
-
ns
CLE to RE Delay
t
CLR
50
-
50
-
ns
Ready to RE Low
t
RR
20
-
20
-
ns
RE Pulse Width
t
RP
25
-
25
-
ns
WE High to Busy
t
WB
-
100
-
100
ns
Read Cycle Time
t
RC
50
-
50
-
ns
CE Access Time
t
CEA
-
45
-
45
ns
RE Access Time
t
REA
-
35
-
35
ns
RE High to Output Hi-Z
t
RHZ
-
30
-
30
ns
CE High to Output Hi-Z
t
CHZ
-
20
-
20
ns
RE or CE High to Output hold
t
OH
15
-
15
-
ns
RE High Hold Time
t
REH
15
-
15
-
ns
Output Hi-Z to RE Low
t
IR
0
-
0
-
ns
WE High to RE Low
t
WHR
60
-
60
-
ns
Device Resetting Time
(Read/Program/Erase)
t
RST
-
5/10/500
(1)
-
5/10/500
(1)
s
K9F6408U0C-
T,Q,V,F only
Last RE High to Busy
(at sequential read)
t
RB
-
100
-
100
ns
CE High to Ready(in case of inter-
ception by CE at read)
t
CRY
-
50 +tr(R/B)
(3)
-
50 +tr(R/B)
(3)
ns
CE High Hold Time(at the last
serial read)
(2)
t
CEH
100
-
100
-
ns
FLASH MEMORY
12
K9F6408U0C
K9F6408Q0C
Identifying Invalid Block(s)
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The informa-
tion regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to
be a valid block.
NAND Flash Technical Notes
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block
has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impossible to
recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the
original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any intentional
erasure of the original invalid block information is prohibited.
*
Figure 1. Flow chart to create invalid block table.
Start
Set Block Address = 0
Check "FFh" ?
Increment Block Address
Last Block ?
End
No
Yes
Yes
Create (or update)
No
Invalid Block(s) Table
Check "FFh" at the column address 517
of the 1st and 2nd page in the block
FLASH MEMORY
13
K9F6408U0C
K9F6408Q0C
NAND Flash Technical Notes (Continued)
Program Flow Chart
Start
I/O 6 = 1 ?
Write 00h
I/O 0 = 0 ?
No
*
If ECC is used, this verification
Write 80h
Write Address
Write Data
Write 10h
Read Status Registe
Write Address
Wait for tR Time
Verify Data
No
Program Completed
or R/B = 1 ?
Program Error
Yes
No
Yes
*
Program Error
Yes
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
operation is not needed.
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that
the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block
failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Write
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Read
Single Bit Failure
Verify ECC -> ECC Correction
ECC
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
FLASH MEMORY
14
K9F6408U0C
K9F6408Q0C
Erase Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 60h
Write Block Address
Write D0h
Read Status Register
or R/B = 1 ?
Erase Error
Yes
No
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Erase Completed
Yes
Read Flow Chart
Start
Verify ECC
No
Write 00h
Write Address
Read Data
ECC Generation
Reclaim the Error
Page Read Completed
Yes
NAND Flash Technical Notes (Continued)
Block Replacement
* Step1
When an error happens in the nth page of the Block 'A' during erase or program operation.
* Step2
Copy the nth page data of the Block 'A' in the buffer memory to the nth page of another free block. (Block 'B')
* Step3
Then, Copy the 1st ~ (n-1)th data to the same location of the Block 'B'.
* Step4
Do not further erase Block 'A' by creating a 'invalid Block' table or other appropriate scheme.
Buffer memory of the controller.
1st
Block A
Block B
(n-1)th
nth
(page)
1
2
{
1st
(n-1)th
nth
(page)
{
FLASH MEMORY
15
K9F6408U0C
K9F6408Q0C
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. '00h'
command sets the pointer to 'A' area(0~255byte), '01h' command sets the pointer to 'B' area(256~511byte), and '50h' command sets
the pointer to 'C' area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). '00h' or '50h' is sustained until another address pointer command is inputted. '01h' command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with '01h' command, the
address pointer returns to 'A' area by itself. To program data starting from 'A' or 'C' area, '00h' or '50h' command must be inputted
before '80h' command is written. A complete read operation prior to '80h' command is not necessary. To program data starting from
'B' area, '01h' command must be inputted right before '80h' command is written.
00h
(1) Command input sequence for programming 'A' area
Address / Data input
80h
10h
00h
80h
10h
Address / Data input
The address pointer is set to 'A' area(0~255), and sustained
01h
(2) Command input sequence for programming 'B' area
Address / Data input
80h
10h
01h
80h
10h
Address / Data input
'B', 'C' area can be programmed.
It depends on how many data are inputted.
'01h' command must be rewritten before
every program operation
The address pointer is set to 'B' area(256~512), and will be reset to
'A' area after every program operation is executed.
50h
(3) Command input sequence for programming 'C' area
Address / Data input
80h
10h
50h
80h
10h
Address / Data input
Only 'C' area can be programmed.
'50h' command can be omitted.
The address pointer is set to 'C' area(512~527), and sustained
'00h' command can be omitted.
It depends on how many data are inputted.
'A','B','C' area can be programmed.
Pointer Operation of K9F6408U0C
Table 1. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
256 Byte
(00h plane)
"B" area
(01h plane)
"C" area
(50h plane)
256 Byte
16 Byte
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 2. Block Diagram of Pointer Operation
FLASH MEMORY
16
K9F6408U0C
K9F6408Q0C
System Interface Using CE don't-care.
CE
WE
t
WP
t
CH
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
t
CS
Start Add.(3Cycle)
80h
Data Input
CE
CLE
ALE
WE
I/O
0
~
7
Data Input
CE don't-care
10h
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading
would provide significant savings in power consumption.
t
CEA
out
t
REA
CE
RE
I/O
0
~
7
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Figure 3. Program Operation with CE don't-care.
Figure 4. Read Operation with CE don't-care.
Start Add.(3Cycle)
00h
CE
CLE
ALE
WE
I/O
0
~
7
Data Output(sequential)
CE don't-care
R/B
t
R
RE
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
low during tR
FLASH MEMORY
17
K9F6408U0C
K9F6408Q0C
Command Latch Cycle
CE
WE
CLE
ALE
I/O
0
~
7
Command
Address Latch Cycle
t
CLS
t
CS
t
CLH
t
CH
t
WP
t
ALS
t
ALH
t
DS
t
DH
CE
WE
CLE
ALE
I/O
0
~
7
A
0
~A
7
t
CLS
t
CS
t
WC
t
WP
t
ALS
t
DS
t
DH
t
ALH
t
ALS
t
WH
A
9
~A
16
t
WC
t
WP
t
DS
t
DH
t
ALH
t
ALS
t
WH
A
17
~A
22
t
WP
t
DS
t
DH
t
ALH
FLASH MEMORY
18
K9F6408U0C
K9F6408Q0C
Input Data Latch Cycle
CE
CLE
WE
I/O
0
~
7
DIN 0
DIN 1
DIN 511
ALE
t
ALS
t
CLH
t
WC
t
CH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
WP
t
WH
t
WP
t
WP
Serial access Cycle after Read
(CLE=L, WE=H, ALE=L)
RE
CE
R/B
I/O
0
~
7
Dout
Dout
Dout
t
RC
t
REA
t
RR
t
RHZ*
t
REA
t
REH
t
REA
t
CHZ*
t
RHZ*
NOTES : Transition is measured
200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
t
OH
t
OH
FLASH MEMORY
19
K9F6408U0C
K9F6408Q0C
Status Read Cycle
CE
WE
CLE
RE
I/O
0
~
7
70h
Status Output
t
CLR
t
CLH
t
CS
t
WP
t
CH
t
DS
t
DH
t
RSTO
t
IR
t
OH
t
OH
t
WHR
t
CSTO
t
CLS
READ1 OPERATION
(READ ONE PAGE)
NOTES : 1) is only valid on K9F6408U0C_T,Q or K9F6408U0C_V,F
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
Busy
00h or 01h A
0
~ A
7
A
9
~ A
16
A
17
~ A
24
Dout N
Dout N+1 Dout N+2
Dout N+3
Column
Address
Page(Row)
Address
t
WB
t
AR2
t
R
t
RC
t
RHZ
t
RR
t
CHZ
Dout 527
t
RB
t
CRY
t
WC
1)
1)
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
low during tR
t
CEH
t
CHZ*
t
RHZ*
t
OH
t
OH
FLASH MEMORY
20
K9F6408U0C
K9F6408Q0C
READ1 OPERATION
(INTERCEPTED BY CE)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
Busy
00h or 01h A
0
~ A
7
A
9
~ A
16
A
17
~ A
22
Dout N
Dout N+1 Dout N+2
Dout N+3
Page(Row)
Address
Address
Column
t
WB
t
AR2
t
OH
t
R
t
RR
t
RC
READ2 OPERATION
(READ ONE PAGE)
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
50h
A
0
~ A
7
A
9
~ A
16
A
17
~ A
22
Dout
Dout 527
M Address
511+M
Dout
511+M+1
t
AR2
t
R
t
WB
t
RR
A
0
~A
3
: Valid Address
A
4
~A
7
: Don
t
care
Selected
Row
Start
address M
512
16
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
low during tR
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
low during tR
t
CHZ
FLASH MEMORY
21
K9F6408U0C
K9F6408Q0C
PAGE PROGRAM OPERATION
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
80h
70h
I/O
0
Din
N
Din
Din
10h
527
N+1
A
0
~ A
7
A
17
~ A
22
A
9
~ A
16
Sequential Data
Input Command
Column
Address
Page(Row)
Address
1 up to 528 Byte Data
Serial Input
Program
Command
Read Status
Command
I/O
0
=0 Successful Program
I/O
0
=1 Error in Program
t
PROG
t
WB
t
WC
t
WC
t
WC
SEQUENTIAL ROW READ OPERATION
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
00h
A
0
~ A
7
Busy
M
Output
A
9
~ A
16
A
17
~ A
22
Dout
N
Dout
N+1
Dout
N+2
Dout
527
Dout
0
Dout
1
Dout
2
Dout
527
Busy
M+1
Output
N
Ready
(only for K9F6408U0C-T,Q and K9F6408U0C-V,F valid within a block)
FLASH MEMORY
22
K9F6408U0C
K9F6408Q0C
BLOCK ERASE OPERATION
(ERASE ONE BLOCK)
MANUFACTURE & DEVICE ID READ OPERATION
CE
CLE
R/B
I/O
0
~
7
WE
ALE
RE
60h
A
17
~ A
22
A
9
~ A
16
Auto Block Erase
Erase Command
Read Status
Command
I/O
0
=1 Error in Erase
DOh
70h
I/O 0
Busy
t
WB
t
BERS
I/O
0
=0 Successful Erase
Page(Row)
Address
t
WC
Setup Command
CE
CLE
I/O 0 ~ 7
WE
ALE
RE
90h
Read ID Command
Maker Code
Device Code
00h
ECh
Device
t
REA
Address. 1cycle
t
AR1
t
CLR
Device
Device Code*
K9F6408Q0C
39h
K9F6408U0C
E6h
Code*
FLASH MEMORY
23
K9F6408U0C
K9F6408Q0C
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred
to the data registers in less than 10
s(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B
pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to
low transitions of the RE clock output the data stating from the selected column address up to the last column address(column 511 or
527 depending on the state of GND input pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10
s again allows reading the selected page.The sequential row read operation is terminated by bringing CE high. The way
the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to
527 may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A
0
to A
3
set the starting address
of the spare area while addresses A
4
to A
7
are ignored. Unless the operation is aborted, the page address is automatically incre-
mented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1
command(00h/01h) is needed to move the pointer back to the main area. Figures 3 through 6 show typical sequence and timings for
each read operation.
Sequential Row Read is available only on K9F6408U0C_T,Q or K9F6408U0C_V,F :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10
s
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 5, 6 show typical sequence and timings for sequential row read oper-
ation.
Figure 3. Read1 Operation
Start Add.(3Cycle)
00h
01h
A
0
~ A
7
& A
9
~ A
22
Data Output(Sequential)
(00h Command)
1st half array 2nd half array
Data Field
Spare Field
(01h Command)*
1st half array 2nd half array
Data Field
Spare Field
* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
CE
CLE
ALE
R/B
WE
I/O
0
~
7
RE
t
R
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
low during tR
FLASH MEMORY
24
K9F6408U0C
K9F6408Q0C
Figure 5. Sequential Row Read1 Operation
Figure 4. Read2 Operation
50h
A
0
~ A
3
& A
9
~ A
22
Data Output(Sequential)
Spare Field
CE
CLE
ALE
R/B
WE
1st half array 2nd half array
Data Field
Spare Field
(GND Input=L, 00h Command)
1st half array 2nd half array
Data Field
Spare Field
00h
01h
A
0
~ A
7
& A
9
~ A
22
I/O
0
~
7
R/B
Start Add.(3Cycle)
Start Add.(3Cycle)
Data Output
Data Output
Data Output
1st
2nd
Nth
(528 Byte)
(528 Byte)
(A
4
~ A
7
:
Don't Care)
1st
2nd
Nth
(GND Input=L, 01h Command)
1st half array 2nd half array
Data Field
Spare Field
1st
2nd
Nth
(GND Input=H, 00h Command)
1st half array 2nd half array
Data Field
Spare Field
1st
2nd
Nth
I/O
0
~
7
RE
t
R
t
R
t
R
t
R
(only for K9F6408U0C-T,Q and K9F6408U0C-V,F valid within a block)
FLASH MEMORY
25
K9F6408U0C
K9F6408Q0C
Figure 6. Sequential Row Read2 Operation (GND Input=Fixed Low)
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done
in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be
loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropri-
ate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with
RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or
the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7). The internal write verify
detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command
mode until another valid command is written to the command register.
50h
A
0
~ A
3
& A
9
~ A
22
I/O
0
~
7
R/B
Start Add.(3Cycle)
Data Output
Data Output
Data Output
2nd
Nth
(16 Byte)
(16 Byte)
1st half array 2nd half array
Data Field
Spare Field
1st
2nd
Nth
(A
4
~ A
7
:
Don
t Care)
1st
Figure 7. Program & Read Status Operation
80h
A
0
~ A
7
& A
9
~ A
22
I/O
0
~
7
R/B
Address & Data Input
I/O
0
Pass
528 Byte Data
10h
70h
Fail
t
R
t
R
t
R
t
PROG
(only for K9F6408U0C-T,Q and K9F6408U0C-V,F valid within a block)
FLASH MEMORY
26
K9F6408U0C
K9F6408Q0C
Figure 8. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A
13
to A
22
is valid while A
9
to A
12
is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked.
Figure 8 details the sequence.
60h
Block Add. : A
9
~ A
22
I/O
0
~
7
R/B
Address Input(2Cycle)
I/O
0
Pass
D0h
70h
Fail
t
BERS
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table2. Read Status Register Definition
I/O #
Status
Definition
I/O
0
Program / Erase
"0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O
1
Reserved for Future
Use
"0"
I/O
2
"0"
I/O
3
"0"
I/O
4
"0"
I/O
5
"0"
I/O
6
Device Operation
"0" : Busy "1" : Ready
I/O
7
Write Protect
"0" : Protected "1" : Not Protected
FLASH MEMORY
27
K9F6408U0C
K9F6408Q0C
Figure 9. Read ID Operation
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
CE
CLE
I/O
0
~
7
ALE
RE
WE
90h
00h
ECh
Device
Address. 1 cycle
Maker code
Device code
t
CEA
t
AR1
tREA
Figure 10. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to
"1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is
high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted to by the command register. The R/B pin transitions to low for t
RST
after the Reset command is written. Reset command is
not necessary for normal operation. Refer to Figure 10 below.
Table3. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
FFh
I/O
0
~
7
R/B
t
RST
t
CLR
Device
Device Code*
K9F6408Q0C
39h
K9F6408U0C
E6h
Code*
FLASH MEMORY
28
K9F6408U0C
K9F6408Q0C
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 11). Its value can be
determined by the following guidance.
V
CC
R/B
open drain output
Device
GND
Rp
t
r
,
t
f
[
s
]
I
b
u
s
y
[
A
]
Rp(ohm)
Figure 11. Rp vs tr ,tf & Rp vs ibusy
Ibusy
tr
ibusy
Busy
Ready Vcc
@ Vcc = 3.3V, Ta = 25
C , C
L
= 100pF
VOH
tf
tr
1K
2K
3K
4K
100n
200n
300n
3m
2m
1m
100
tf
200
300
400
3.6
3.6
3.6
3.6
2.4
1.2
0.8
0.6
VOL
Rp(min, 1.8V part) =
V
CC
(Max.) - V
OL
(Max.)
I
OL
+
I
L
=
1.85V
3mA
+
I
L
where I
L
is the sum of the input currents of all devices tied to the R/B pin.
Rp value guidance
Rp(max) is determined by maximum permissible limit of tr
Rp(min, 3.3V part) =
V
CC
(Max.) - V
OL
(Max.)
I
OL
+
I
L
=
3.2V
8mA
+
I
L
1.8V device - V
OL
: 0.1V, V
OH
: V
CC
q-0.1V
3.3V device - V
OL
: 0.4V, V
OH
: 2.4V
t
r
,
t
f
[
s
]
I
b
u
s
y
[
A
]
Rp(ohm)
Ibusy
tr
@ Vcc = 1.8V, Ta = 25
C , C
L
= 30pF
1K
2K
3K
4K
100n
200n
300n
3m
2m
1m
30
tf
60
90
120
1.7
1.7
1.7
1.7
1.7
0.85
0.57
0.43
C
L
FLASH MEMORY
29
K9F6408U0C
K9F6408Q0C
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V/2V(K9F6408Q0C:1.1V, K9F6408U0C:2V). WP pin provides hardware pro-
tection and is recommended to be kept at V
IL
during power-up and power-down and recovery time of minimum 10
s is required
before internal circuit gets ready for any command sequences as shown in Figure 12. The two step command sequence for program/
erase provides additional software protection.
Figure 12. AC Waveforms for Power Transition
V
CC
WP
High
1.8V device : ~ 1.5V
WE
Data Protection & Powerup sequence
3.3V device : ~ 2.5V
1.8V device : ~ 1.5V
3.3V device : ~ 2.5V
10
s
PDF 
ZIP