PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
1
99-06-15
INTRODUCTION
The KB8821/22/23 are high performance dual frequency syn-
thesizers with integrated prescalers designed for RF operation
up to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz.
The KB8821/22/23 contain dual-modulus prescalers. The RF
synthesizer adopts a 64/65 or an 128/129 prescaler(32/33 or
64/65 for the KB8823) and the IF synthesizer adopts an 8/9 or
a 16/17 prescaler.
Using a proprietary digital phase-locked-loop technique, the
KB8821/22/23 have linear phase detector characteristic and
can be used for very stable, low noise local oscillator signal.
Supply voltage can range from 2.7V to 4.0V. The KB8821/22/
23 are now available
in a
20-TSSOP/24-QFN package.
FEATURES
Very low current consumption
(8821:3.5mA, 22:4.5mA, 23:5.5mA)
Operating voltage range : 2.7 ~ 4.0V
Selectable power saving mode(Icc=1uA typical @3V)
Dual modulus prescaler :
KB8821/22 (RF) 64/65 or 128/129
KB8823 (RF) 32/33 or 64/65
KB8821/22/23 (IF) 8/9 or 16/17
Programmability via serial bus interface
No dead-zone PFD
Variable charge pump output current
High speed lock mode
ORDERING INFORMATION
* QFN : Quad Flat Non-leaded(see Addendum).
Device
Package
Tem. Range
KB8821/22/23
20-TSSOP-225 -40 ~ +85
C
KB8821/22/23
24-QFN*
-40 ~ +85
C
20-TSSOP-225
APPLICATIONS
Cellular telephone systems : KB8821
Portable wireless communications : KB8822
(PCS/PCN, cordless)
Wireless Local Area Networks (W-LANs)
: KB8823
Other wireless communication systems
BLOCK DIAGRAM
Figure 1. BLOCK DIAGRAM
RF
Serial Data Control
Charge
Pump
finRF
foLD
N Counter
CLOCK
LE
DATA
RF
Phase
Detector
RF
RF
Prescaler
finRF
+
-
RF
LD
CPoRF
finIF
finIF
OSCin
RF
R Counter
IF
R Counter
IF
Prescaler
IF
N Counter
Detector
IF
Phase
Pump
IF
Charge
CPoIF
IF
LD
+
-
foLD
Data Out
Multiplexer
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
3
99-06-15
PIN CONFIGURATION
V
DD
1
Vp1
CPoRF
GND
finRF
finRF
GND
OSCin
GND
foLD
V
DD
2
Vp2
CPoIF
GND
finIF
finIF
GND
LE
DATA
CLOCK
1
20
2
3
4
5
6
7
8
20-Lead(0.173 Wide) Thin Shrink Small
9
10
19
18
17
16
15
14
13
12
11
Outline Package(20-TSSOP)
KB8821
KB8822
KB8823
20-TSSOP
Top View
(Digital)
(Analog)
(Digital)
(Digital)
(Analog)
1. pin #9 = pin #17(internally connected).
2. Do not tie up Vp and V
DD
:
Vp is the source of digital noises. The power
for analog part is supplied by V
DD.
If Vp and
V
DD
are tied together, noisy Vp corrupts the
power source for the analog part.
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
4
99-06-15
PIN DESCRIPTION
Pin No
Symbol
I / O
Description
1
V
DD
1
-
Power supply voltage input for the RF PLL part. V
DD
1 must equal V
DD
2. In
order to reject supply noise, bypass capacitors must be placed as close as
possible to this pin and be connected directly to the ground plane.
2
Vp1
-
Power supply voltage input for RF charge pump(
V
DD
1).
3
CPoRF
O
Internal RF charge pump output for connection to an external loop filter whose
filtered output drives an external VCO.
4
GND
-
Ground for RF digital blocks.
5
finRF
I
RF prescaler input. The signal comes from the external VCO.
6
finRF
I
The complementary input of the RF prescaler. A bypass capacitor must be
placed as close as possible to this pin and be connected directly to the ground
plane. The bypass capacitor is optional with some loss of sensitivity.
7
GND
-
Ground for RF analog blocks.
8
OSCin
I
Reference counter input. TCXO is connected via a coupling capacitor.
9
GND
-
Ground for IF digital blocks.
10
f
oLD
O
Multiplexed output of the RF/IF programmable counters, the reference
counters, the lock detect signals and the shift registers. The output level is
CMOS level. (see f
out
Programmable Truth Table)
11
CLOCK
I
CMOS clock input. Serial data for the various counters is transfered into the
22-bit shift register on the rising edge of the clock signal.
12
DATA
I
Binary serial data input. The MSB of CMOS input data is entered first. The
control bits are on the last two bits. CMOS input.
13
LE
I
Load enable CMOS input. When LE becomes high, the data in the shift
register is loaded into one of the four latches(by the control bits).
14
GND
-
Ground for IF analog blocks.
15
finIF
I
The complementary input of the IF prescaler. A bypass capacitor must be
placed as close as possible to this pin and be connected directly to the ground
plane. The bypass capacitor is optional with some loss of sensitivity.
16
finIF
I
IF prescaler input. The signal comes from the external VCO.
17
GND
-
Ground for IF digital blocks.
18
CPoIF
O
Internal IF charge pump output for connection to an external loop filter whose
filtered output drives an external VCO.
19
Vp2
-
Power supply voltage input for IF charge pump(
V
DD
2)
20
V
DD
2
-
Power supply voltage input for the IF PLL part. V
DD
1 must equal V
DD
2. In
order to reject supply noise, bypass capacitors must be placed as close as
possible to this pin and be connected directly to the ground plane.
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