KM416C4000B,
KM416C4100B
CMOS DRAM
This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6) are optional features of this family. All of this fam-
ily have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 Fast Page Mode DRAM family is fabri-
cated using Samsung
s advanced CMOS process to realize high band-width, low power consumption and high reliability.
Part Identification
- KM416C4000B(5.0V, 8K Ref.)
- KM416C4100B(5.0V, 4K Ref.)
Fast Page Mode operation
2CAS Byte/Word Read/Write operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Fast parallel test mode capability
TTL(5.0V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in Plastic TSOP(II) package
+5.0V
10% power supply
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
4M x 16bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FEATURES
Refresh Cycles
Part
NO.
Refresh
cycle
Refresh time
Normal
KM416C4000B*
8K
64ms
KM416C4100B
4K
Performance Range
Speed
t
RAC
t
CAC
t
RC
t
PC
-45
45ns
12ns
80ns
31ns
-5
50ns
13ns
90ns
35ns
-6
60ns
15ns
110ns
40ns
Active Power Dissipation
Speed
8K
4K
-45
550
715
-5
495
660
-6
440
605
Unit : mW
Control
Clocks
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc
Vss
DQ0
to
DQ7
A0~A12
(A0~A11)*1
A0~A8
(A0~A9)*1
Memory Array
4,194,304 x 16
Cells
FUNCTIONAL BLOCK DIAGRAM
Note) *1 : 4K Refresh
S
e
n
s
e
A
m
p
s
&
I
/
O
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
DQ8
to
DQ15
OE
* Access mode & RAS only refresh mode
: 8K cycle/64ms
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms
Row Decoder
Column Decoder
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
KM416C4000B,
KM416C4100B
CMOS DRAM
PIN CONFIGURATION (Top Views)
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
N.C
V
CC
W
RAS
N.C
N.C
N.C
N.C
A0
A1
A2
A3
A4
A5
V
CC
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
V
SS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A7
A6
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Pin Name
Pin function
A0 - A12
Address Inputs(8K Product)
A0 - A11
Address Inputs(4K Product)
DQ0 - 15
Data In/Out
V
SS
Ground
RAS
Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
V
CC
Power(+5.0V)
N.C
No Connection
(400mil TSOP(II))
*(N.C) : N.C for 4K Refresh Product
KM416C40(1)00BS
KM416C4000B,
KM416C4100B
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Parameter
Symbol
Rating
Units
Voltage on any pin relative to V
SS
V
IN,
V
OUT
-1.0 to +7.0
V
Voltage on V
CC
supply relative to V
SS
V
CC
-1.0 to +7.0
V
Storage Temperature
Tstg
-55 to +150
C
Power Dissipation
P
D
1
W
Short Circuit Output Current
I
OS
Address
50
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70
C)
*1 : V
CC
+2.0V at pulse width
20ns which is measured at V
CC
*2 : -2.0 at pulse width
20ns which is measured at V
SS
Parameter
Symbol
Min
Typ
Max
Units
Supply Voltage
V
CC
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.4
-
V
CC
+1.0
*1
V
Input Low Voltage
V
IL
-1.0
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0
V
IN
V
CC
+0.5V,
all other pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-5mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=4.2mA)
V
OL
-
0.4
V
*2
KM416C4000B,
KM416C4100B
CMOS DRAM
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one fast page mode cycle time,
t
PC
.
DC AND OPERATING CHARACTERISTICS
(Continued)
I
CC1
* : Operating Current (RAS and UCAS, LCAS, Address cycling @
t
RC
=min.)
I
CC2
: Standby Current (RAS=UCAS=LCAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (UCAS=LCAS=V
IH
, RAS, Address cycling @
t
RC
=min.)
I
CC4
* : Fast Page Mode Current (RAS=V
IL
, UCAS or LCAS, Address cycling @
t
PC
=min.)
I
CC5
: Standby Current (RAS=UCAS=LCAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @
t
RC
=min)
Symbol
Power
Speed
Max
Units
KM416C4000B
KM416C4100B
I
CC1
Don
t care
-45
-5
-6
100
90
80
130
120
110
mA
mA
mA
I
CC2
Normal
Don
t care
2
2
mA
I
CC3
Don
t care
-45
-5
-6
100
90
80
130
120
110
mA
mA
mA
I
CC4
Don
t care
-45
-5
-6
70
60
50
80
70
60
mA
mA
mA
I
CC5
Normal
Don
t care
1
1
mA
I
CC6
Don
t care
-45
-5
-6
100
90
80
130
120
110
mA
mA
mA
KM416C4000B,
KM416C4100B
CMOS DRAM
CAPACITANCE
(T
A
=25
C, V
CC
=5.0V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A12]
C
IN1
-
5
pF
Input capacitance [RAS, UCAS, LCAS, W, OE]
C
IN2
-
7
pF
Output capacitance [DQ0 - DQ15]
C
DQ
-
7
pF
Test condition : V
CC
=5.0V
10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Parameter
Symbol
-45
-5
-6
Units
Note
Min
Max
Min
Max
Min
Max
Random read or write cycle time
t
RC
80
90
110
ns
Read-modify-write cycle time
t
RWC
115
133
153
ns
Access time from RAS
t
RAC
45
50
60
ns
3,4,10
Access time from CAS
t
CAC
12
13
15
ns
3,4,5
Access time from column address
t
AA
23
25
30
ns
3,10
CAS to output in Low-Z
t
CLZ
0
0
0
ns
3
Output buffer turn-off delay
t
OFF
0
13
0
13
0
13
ns
6
Transition time (rise and fall)
t
T
1
50
1
50
1
50
ns
2
RAS precharge time
t
RP
25
30
40
ns
RAS pulse width
t
RAS
45
10K
50
10K
60
10K
ns
RAS hold time
t
RSH
12
13
15
ns
CAS hold time
t
CSH
45
50
60
ns
CAS pulse width
t
CAS
12
10K
13
10K
15
10K
ns
RAS to CAS delay time
t
RCD
18
33
20
37
20
45
ns
4
RAS to column address delay time
t
RAD
13
22
15
25
15
30
ns
10
CAS to RAS precharge time
t
CRP
5
5
5
ns
Row address set-up time
t
ASR
0
0
0
ns
Row address hold time
t
RAH
8
10
10
ns
Column address set-up time
t
ASC
0
0
0
ns
13
Column address hold time
t
CAH
8
10
10
ns
13
Column address to RAS lead time
t
RAL
23
25
30
ns
Read command set-up time
t
RCS
0
0
0
ns
Read command hold time referenced to CAS
t
RCH
0
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
0
0
0
ns
8
Write command hold time
t
WCH
8
10
10
ns
Write command pulse width
t
WP
8
10
10
ns
Write command to RAS lead time
t
RWL
13
15
15
ns
Write command to CAS lead time
t
CWL
12
13
15
ns
16
Data set-up time
t
DS
0
0
0
ns
9,19
Data hold time
t
DH
10
10
10
ns
9,19
AC CHARACTERISTICS
(0
C
T
A
70
C, See note 1,2)
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