KM416S1020C
CMOS SDRAM
- 1 -
Rev. 0.6 (Sep. 1998)
1M x 16 SDRAM
Revision 0.6
September 1998
512K x 16bit x 2 Banks
Synchronous DRAM
LVTTL
Samsung Electronics reserves the right to change products or specification without notice.
KM416S1020C
CMOS SDRAM
- 2 -
Rev. 0.6 (Sep. 1998)
Revision History
Revision 0.6 (September 10, 1998)
Removed KM416S1020C-H/L product (-H: 100MHz @ CL=2, -L: 100MHz @ CL3 )
Changed the clock cycle time of KM416S1020C-8 @ CL2 from 12ns to 10ns, accordingly, the AC and DC parameters of
KM416S1020C-8 @ CL2 are changed in AC/DC CHARACTERISTICS. For this part, the VDD condition of AC Operat-
ing Test is 3.135V ~ 3.6V
Changed ICC1 of KM416S1020C-7 @ CL2 from 115mA to 120mA in DC CHARACTERISTICS.
Changed ICC1 of KM416S1020C-10 @ CL3 from 80mA to 85mA in DC CHARACTERISTICS.
Changed tRDL of KM416S1020C-10 @ CL3 from 2CLK to 1CLK in OPERATING AC PARAMETER.
Removed CL2 from KM416S1020C-6
Revision 0.5 (July 13, 1998)
- Prelimianry
Added -6(166MHz) binning product. For this part, the VDD condition of AC Operating Test is 3.135V ~ 3.6V.
Changed the clock cycle time of KM416S1020C-7 @ CL2 from 12ns to 8.7ns, accordingly, the AC and DC parameters of
KM416S1020C-7 @ CL2 are changed in AC/DC CHARACTERISTICS. For this part, the VDD condition of AC Operat-
ing Test is 3.135V ~ 3.6V.
Changed ICC1 of KM416S1020C-7 @ CL3 from 95mA to 105mA in DC CHARACTERISTICS.
Changed DC/AC Test Output Load of KM416S1020C-7/6 from 50pF to 30pF in AC OPERATING TEST CONDITIONS.
Defined tMRSmin(Mode Register Set cycle time) as 2 CLK in AC CHARACTERISTICS.
Revision 0.4 (April 17, 1998)
Changed DC/AC Test Output Load from 30pF to 50pF in AC OPERATING TEST CONDITIONS.
Changed tOH from 2.5ns to 3ns in KM416S1020C-8/H/L/10 in AC CHARACTERISTICS.
Revision 0.3 (April 2, 1998)
Changed DC/AC Test Output Load from 50pF to 30pF in AC OPERATING TEST CONDITIONS.
Changed tSAC from 6ns to 7ns, tSHZ from 6ns to 7ns @ CL=2 in KM416S1020C-8, tOH from 3ns to 2.5ns in
KM416S1020C-8/H/L/10 in AC CHARACTERISTICS.
Revision 0.2 (February 1998)
Input Leakage Currents (Inputs / DQ) are changed(IIL(Inputs) :
5uA to
1uA, IIL(DQ) :
5uA to
1.5uA.).
Cin to be measured at VDD = 3.3V, TA = 23
C, f = 1MHz, VREF =1.4V
200 mV.
Bining -7 is added.
Refresh cycle changed 2K/32ms to 4K/64ms.
AC Operating Condition is changed as defined :
- VIH(max) = 5.6V AC. The overshoot voltage duration is
3ns.
- VIL(min) = -2.0V AC. The undershoot voltage duration is
3ns.
Revision 0.1 (November 1997)
tRDL has changed 10ns to 12ns.
KM416S1020C
CMOS SDRAM
- 3 -
Rev. 0.6 (Sep. 1998)
The KM416S1020C is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
512K x 16Bit x 2 Banks Synchronous DRAM
ORDERING INFORMATION
Part NO.
MAX Freq.
Interface Package
KM416S1020CT-G/F6
166MHz
LVTTL
50
TSOP(II)
KM416S1020CT-G/F7
143MHz
KM416S1020CT-G/F8
125MHz
KM416S1020CT-G/F10
100MHz
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
512K x 16
512K x 16
S
e
n
s
e
A
M
P
O
u
t
p
u
t
B
u
f
f
e
r
I
/
O
C
o
n
t
r
o
l
Column Decoder
Latency & Burst Length
Programming Register
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
R
o
w
B
u
f
f
e
r
R
e
f
r
e
s
h
C
o
u
n
t
e
r
R
o
w
D
e
c
o
d
e
r
C
o
l
.
B
u
f
f
e
r
L
R
A
S
L
C
B
R
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
Timing Register
KM416S1020C
CMOS SDRAM
- 4 -
Rev. 0.6 (Sep. 1998)
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PIN CONFIGURATION (TOP VIEW)
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
50PIN TSOP (II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A
0
~ A
10
/AP
Address
Row / column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
10
, column address : CA
0
~ CA
7
BA
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
L(U)DQM
Data Input/Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ
0
~
15
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power Supply/Ground
Power and ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output Power/Ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU
No Connection/
Reserved for Future Use
This pin is recommended to be left No Connection on the device.
KM416S1020C
CMOS SDRAM
- 5 -
Rev. 0.6 (Sep. 1998)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
3.0
3.3
3.6
V
5
Input logic high votlage
V
IH
2.0
3.0
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.8
V
2
Output logic high voltage
V
OH
2.4
-
-
V
I
OH
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current(Inputs)
I
IL
-1
-
1
uA
3
Input leakage current (I/O pins)
I
IL
-1.5
-
1.5
uA
3,4
Note :
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23
C, f = 1MHz, V
REF
=1.4V
200
mV)
Pin
Symbol
Min
Max
Unit
Clock
C
CLK
2.5
4.0
pF
RAS, CAS, WE, CS, CKE, L(U)DQM
C
IN
2.5
5.0
pF
Address
C
ADD
2.5
5.0
pF
DQ
0
~ DQ
15
C
OUT
4.0
6.5
pF
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
V
OUT
V
DDQ.
5. The VDD condition of KM416S1020C-7/8@CL2 and KM416S1020C-6@CL3 is 3.135V~3.6V.
Note :
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between V
DD
and V
SS
C
DC1
0.1 + 0.01
uF
Decoupling Capacitance between V
DDQ
and V
SSQ
C
DC2
0.1 + 0.01
uF
1. V
DD
and V
DDQ
pins are separated each other.
All V
DD
pins are connected in chip. All V
DDQ
pins are connected in chip.
2. V
SS
and V
SSQ
pins are separated each other
All V
SS
pins are connected in chip. All V
SSQ
pins are connected in chip.
Note :
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