KM416C1004C, KM416C1204C
CMOS DRAM
KM416V1004C, KM416V1204C
This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K
Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung
s advanced CMOS process to
realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal
computer and portable machines.
Part Identification
- KM416C1004C/C-L (5V, 4K Ref.)
- KM416C1204C/C-L (5V, 1K Ref.)
- KM416V1004C/C-L (3.3V, 4K Ref.)
- KM416V1204C/C-L (3.3V, 1K Ref.)
Extended Data Out Mode operation
(Fast Page Mode with Extended Data Out)
2 CAS Byte/Word Read/Write operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in plastic SOJ 400mil and TSOP(II) packages
Single +5V
10% power supply (5V product)
Single +3.3V
0.3V power supply (3.3V product)
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Column Decoder
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc
Vss
DQ0
to
DQ7
A0-A11
(A0 - A9)
*1
A0 - A7
(A0 - A9)
*1
Memory Array
1,048,576 x16
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
1M x 16Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles
Part
NO.
V
CC
Refresh
cycle
Refresh period
Normal
L-ver
C1004C
5V
4K
64ms
128ms
V1004C
3.3V
C1204C
5V
1K
16ms
V1204C
3.3V
Performance Range
Speed
t
RAC
t
CAC
t
RC
t
HPC
Remark
-45
45ns
13ns
69ns
16ns
5V/3.3V
-5
50ns
15ns
84ns
20ns
5V/3.3V
-6
60ns
17ns
104ns
25ns
5V/3.3V
Active Power Dissipation
Speed
3.3V
5V
4K
1K
4K
1K
-45
-
-
550
825
-5
324
504
495
770
-6
288
468
440
715
Unit : mW
S
e
n
s
e
A
m
p
s
&
I
/
O
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
DQ8
to
DQ15
OE
Note)
*1
: 1K Refresh
KM416C1004C, KM416C1204C
CMOS DRAM
KM416V1004C, KM416V1204C
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
V
CC
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
PIN CONFIGURATION (Top Views)
Pin Name
Pin Function
A0 - A11
Address Inputs (4K Product)
A0 - A9
Address Inputs (1K Product)
DQ0 - 15
Data In/Out
V
SS
Ground
RAS
Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
V
CC
Power(+5V)
Power(+3.3V)
N.C
No Connection
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
V
CC
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
*A10 and A11 are N.C for KM416C/V1204C(5V/3.3V, 1K Ref. product)
J : 400mil 42 SOJ
T : 400mil 50(44) TSOP II
KM416C/V10(2)04CJ
KM416C/V10(2)04CT
KM416C1004C, KM416C1204C
CMOS DRAM
KM416V1004C, KM416V1204C
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Parameter
Symbol
Rating
Units
3.3V
5V
Voltage on any pin relative to V
SS
V
IN,
V
OUT
-0.5 to +4.6
-1.0 to +7.0
V
Voltage on V
CC
supply relative to V
SS
V
CC
-0.5 to +4.6
-1.0 to +7.0
V
Storage Temperature
Tstg
-55 to +150
-55 to +150
C
Power Dissipation
P
D
1
1
W
Short Circuit Output Current
I
OS
50
50
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70
C)
*1 : V
CC
+1.3V/15ns(3.3V), V
CC
+2.0V/20ns(5V), Pulse width is measured at V
CC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V
SS
Parameter
Symbol
3.3V
5V
Units
Min
Typ
Max
Min
Typ
Max
Supply Voltage
V
CC
3.0
3.3
3.6
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
0
0
0
V
Input High Voltage
V
IH
2.0
-
V
CC
+0.3
*1
2.4
-
V
CC
+1.0
*1
V
Input Low Voltage
V
IL
-0.3
*2
-
0.8
-1.0
*2
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Max
Parameter
Symbol
Min
Max
Units
3.3V
Input Leakage Current (Any input 0
V
IN
V
IN
+0.3V,
all other input pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-2mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=2mA)
V
OL
-
0.4
V
5V
Input Leakage Current (Any input 0
V
IN
V
IN
+0.5V,
all other input pins not under test=0 Volt)
I
I(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V
V
OUT
V
CC
)
I
O(L)
-5
5
uA
Output High Voltage Level(I
OH
=-5mA)
V
OH
2.4
-
V
Output Low Voltage Level(I
OL
=4.2mA)
V
OL
-
0.4
V
KM416C1004C, KM416C1204C
CMOS DRAM
KM416V1004C, KM416V1204C
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Hyper page mode cycle time, t
HPC
.
DC AND OPERATING CHARACTERISTICS
(Continued)
I
CC1
* : Operating Current (RAS and UCAS, LCAS, Address cycling @t
RC
=min.)
I
CC2
: Standby Current (RAS=UCAS=LCAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (UCAS=LCAS=V
IH
, RAS, Address cycling @t
RC
=min.)
I
CC4
* : Hyper Page Mode Current (RAS=V
IL
, UCAS or LCAS, Address cycling @t
HPC
=min.)
I
CC5
: Standby Current (RAS=UCAS=LCAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @t
RC
=min.)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, UCAS, LCAS=0.2V,
DQ=Don
t care, T
RC
=31.25us(4K/L-ver), 125us(1K/L-ver)
T
RAS
=T
RAS
min~300ns
I
CCS
: Self Refresh Current
RAS=UCAS=LCAS=V
IL
, W=OE=A0 ~ A11=V
CC
-0.2V or 0.2V,
DQ0 ~ DQ15=V
CC
-0.2V, 0.2V or Open
Symbol
Power
Speed
Max
Units
KM416V1004C
KM416V1204C
KM416C1004C
KM416C1204C
I
CC1
Don
t care
-45
-5
-6
100
90
80
150
140
130
100
90
80
150
140
130
mA
mA
mA
I
CC2
Normal
L
Don
t care
1
1
1
1
2
1
2
1
mA
mA
I
CC3
Don
t care
-45
-5
-6
100
90
80
150
140
130
100
90
80
150
140
130
mA
mA
mA
I
CC4
Don
t care
-45
-5
-6
110
100
90
110
100
90
110
100
90
110
100
90
mA
mA
mA
I
CC5
Normal
L
Don
t care
0.5
200
0.5
200
1
200
1
200
mA
uA
I
CC6
Don
t care
-45
-5
-6
100
90
80
150
140
130
110
90
80
150
140
130
mA
mA
mA
I
CC7
L
Don
t care
300
200
350
250
uA
I
CCS
L
Don
t care
150
150
200
200
uA
KM416C1004C, KM416C1204C
CMOS DRAM
KM416V1004C, KM416V1204C
CAPACITANCE
(T
A
=25
C, V
CC
=5V or 3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A11]
C
IN1
-
5
pF
Input capacitance [RAS, UCAS, LCAS, W, OE]
C
IN2
-
7
pF
Output capacitance [DQ0 - DQ15]
C
DQ
-
7
pF
Test condition (5V device) : V
CC
=5.0V
10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-45
-5
-6
Units
Notes
Min
Max
Min
Max
Min
Max
Random read or write cycle time
t
RC
79
84
104
ns
Read-modify-write cycle time
t
RWC
105
115
140
ns
Access time from RAS
t
RAC
45
50
60
ns
3,4,10
Access time from CAS
t
CAC
14
15
17
ns
3,4,5
Access time from column address
t
AA
23
25
30
ns
3,10
CAS to output in Low-Z
t
CLZ
3
3
3
ns
3
Output buffer turn-off delay from CAS
t
CEZ
3
13
3
13
3
15
ns
6,19
OE to output in Low-Z
t
OLZ
3
3
3
ns
3
Transition time (rise and fall)
t
T
2
50
2
50
2
50
ns
2
RAS precharge time
t
RP
30
30
40
ns
RAS pulse width
t
RAS
45
10K
50
10K
60
10K
ns
RAS hold time
t
RSH
13
13
17
ns
CAS hold time
t
CSH
36
40
50
ns
CAS pulse width
t
CAS
7
10K
8
10K
10
10K
ns
18
RAS to CAS delay time
t
RCD
19
31
20
35
20
43
ns
4
RAS to column address delay time
t
RAD
14
22
15
25
15
30
ns
10
CAS to RAS precharge time
t
CRP
5
5
5
ns
Row address set-up time
t
ASR
0
0
0
ns
Row address hold time
t
RAH
9
10
10
ns
Column address set-up time
t
ASC
0
0
0
ns
11
Column address hold time
t
CAH
7
8
10
ns
11
Column address to RAS lead time
t
RAL
23
25
30
ns
Read command set-up time
t
RCS
0
0
0
ns
Read command hold time referenced to CAS
t
RCH
0
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
0
0
0
ns
8
Write command hold time
t
WCH
8
10
10
ns
Write command pulse width
t
WP
8
10
10
ns
Write command to RAS lead time
t
RWL
10
13
15
ns
Write command to CAS lead time
t
CWL
7
8
10
ns
14
AC CHARACTERISTICS
(0
C
T
A
70
C, See note 1,2)
Test condition (3.3V device) : V
CC
=3.3V
0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
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