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Электронный компонент: KM6161002A-17

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KM6161002A, KM6161002AI
CMOS SRAM
PRELIMINARY
Rev 4.0
- 1 -
February 1998
Document Title
64Kx16 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No.

Rev. 0.0

Rev. 1.0
Rev. 2.0
Rev. 3.0
Rev. 4.0
Remark

Preliminary
Final
Final
Final
Final
History

Initial release with Preliminary.

Release to final Data Sheet.
1.1. Delete Preliminary
Update D.C parameters.
2.1. Update D.C parameters.
Add Industrial Temperature Range parts
3.1. Add Industrial Temperature Range parts with the same parame-
ters as Commercial Temperature Range parts.
3.1.1. Add KM6161002AI parts for Industrial Temperature
Range.
3.1.2. Add ordering information.
3.1.3. Add the condition for operating at Industrial Temp. Range.
3.2. Add the test condition for Voh1 with Vcc=5V
5% at 25
C
3.3. Add timing diagram to define tWP1 as
(
Timing Wave Form of
Write Cycle(OE=Low fixed)
4.1. Delete 17ns Part
Items
Previous spec.
(12/15/17/20ns part)
Updated spec.
(12/15/17/20ns part)
Icc
220/210/200/190mA
190/185/185/180mA
Isb
30mA
25mA
Isb1
10mA
8mA
Draft Data

Apr. 22th, 1995
Feb. 29th, 1996
Jul. 16th, 1996
Jun. 2nd, 1997
Feb. 25th, 1998
KM6161002A, KM6161002AI
CMOS SRAM
PRELIMINARY
Rev 4.0
- 2 -
February 1998
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
15
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
LB
Lower-byte Control(I/O
1
~I/O
8
)
UB
Upper-byte Control(I/O
9
~I/O
16
)
I/O
1
~ I/O
16
Data Inputs/Outputs
V
CC
Power(+5.0V)
V
SS
Ground
N.C
No Connection
64K x 16 Bit High-Speed CMOS Static RAM
The KM6161002A is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
KM6161002A uses 16 common input and output lines and has
an output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control(UB, LB). The device is fabricated
using SAMSUNG
s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
KM6161002A is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward.
GENERAL DESCRIPTION
FEATURES
Fast Access Time 12, 15, 20ns(Max.)
Low Power Dissipation
Standby (TTL) : 25mA(Max.)
(CMOS) : 8mA(Max.)
Operating KM6161002A - 12 : 190mA(Max.)
KM6161002A - 15 : 185mA(Max.)
KM6161002A - 20 : 180mA(Max.)
Single 5.0V
10% Power Supply
TTL Compatible Inputs and Outputs
I/O Compatible with 3.3V Device
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Center Power/Ground Pin Configuration
Data Byte Control : LB:I/O
1
~I/O
8,
UB:I/O
9
~I/O
16
Standard Pin Configuration
KM6161002AJ : 44-SOJ-400
KM6161002AT : 44-TSOP2-400F
Clk Gen.
I/O
1
~I/O
8
OE
UB
CS
PIN CONFIGURATION
(Top View)
SOJ/
FUNCTIONAL BLOCK DIAGRAM
TSOP2
R
o
w

S
e
l
e
c
t
Data
Cont.
Column Select
A
10
A
11
A
12
A
13
A
14
A
15
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
128x16 Columns
I/O Circuit &
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A
15
A
14
A
13
OE
UB
LB
I/O
16
I/O
15
I/O
14
I/O
13
Vss
Vcc
I/O
12
I/O
11
I/O
10
I/O
9
N.C.
A
12
A
11
A
10
A
9
N.C.
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
I/O
3
I/O
4
Vcc
Vss
I/O
5
I/O
6
I/O
7
I/O
8
WE
A
5
A
6
A
7
A
8
N.C.
A
0
I/O
9
~I/O
16
Data
Cont.
WE
LB
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
KM6161002A -12/15/20
Commercial Temp.
KM6161002AI -12/15/20
Industrial Temp.
ORDERING INFORMATION
A
1
A
2
A
3
A
5
A
6
A
7
A
8
A
9
A
4
KM6161002A, KM6161002AI
CMOS SRAM
PRELIMINARY
Rev 4.0
- 3 -
February 1998
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
,
V
OUT
-0.5 to 7.0
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-0.5 to 7.0
V
Power Dissipation
P
D
1.0
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
Commercial
T
A
0 to 70
C
Industrial
T
A
-40 to 85
C
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70
C)
NOTE: The above parameters are also guaranteed at industrial temperature range.
* V
IL
(Min) = -2.0V a.c(Pulse Width
10ns) for I
20mA
** V
IH
(Max) = V
CC +
2.0V a.c (Pulse Width
10ns) for I
20mA
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
-
V
CC
+ 0.5**
V
Input Low Voltage
V
IL
-0.5*
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70
C, Vcc=5.0V
10%, unless otherwise specified)
NOTE
:
The above parameters are also guaranteed at industrial temperature range.
* V
CC
=5.0V, Temp=25
C
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
IN
= V
SS
to
V
CC
-2
2
A
Output Leakage Current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
= V
SS
to
V
CC
-2
2
A
Operating Current
I
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
= V
IH
or
V
IL,
I
OUT
=0mA
12ns
-
190
mA
15ns
-
185
20ns
-
180
Standby Current
I
SB
Min. Cycle, CS=V
IH
-
25
mA
I
SB1
f=0MHz, CS
V
CC
-0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V
-
8
mA
Output Low Voltage Level
V
OL
I
OL
=8mA
-
0.4
V
Output High Voltage Level
V
OH
I
OH
=-4mA
2.4
-
V
V
OH1
*
I
OH1
=-0.1mA
-
3.95
V
CAPACITANCE*
(T
A
=25
C
, f=1.0MHz)
* NOTE : Capacitance is sampled and not 100% tested.
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
C
I/O
V
I/O
=0V
-
8
pF
Input Capacitance
C
IN
V
IN
=0V
-
6
pF
KM6161002A, KM6161002AI
CMOS SRAM
PRELIMINARY
Rev 4.0
- 4 -
February 1998
TEST CONDITIONS
NOTE:
The above test conditions are also applied at industrial temperature range
.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
C
, V
CC
=5.0V
10%, unless otherwise noted.
)
READ CYCLE
NOTE: The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
KM6161002A-12
KM6161002A-15
KM6161002A-20
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
12
-
15
-
20
-
ns
Address Access Time
t
AA
-
12
-
15
-
20
ns
Chip Select to Output
t
CO
-
12
-
15
-
20
ns
Output Enable to Valid Output
t
OE
-
6
-
7
-
9
ns
UB, LB Access Time
t
BA
-
6
-
7
-
9
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
ns
UB, LB Enable to Low-Z Output
t
BLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
6
0
7
0
9
ns
Output Disable to High-Z Output
t
OHZ
0
6
0
7
0
9
ns
UB, LB Disable to High-Z Output
t
BHZ
0
6
0
7
0
9
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
ns
Output Loads(A)
Output Loads(B)
D
OUT
5pF*
480
255
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5.0V
D
OUT
30pF*
480
255
+5.0V
* Including Scope and Jig Capacitance
KM6161002A, KM6161002AI
CMOS SRAM
PRELIMINARY
Rev 4.0
- 5 -
February 1998
WRITE CYCLE
NOTE: The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
KM6161002A-12
KM6161002A-15
KM6161002A-20
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
12
-
15
-
20
-
ns
Chip Select to End of Write
t
CW
8
-
10
-
12
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
8
-
10
-
12
-
ns
Write Pulse Width(OE High)
t
WP
8
-
10
-
12
-
ns
Write Pulse Width(OE Low)
t
WP1
12
-
15
-
20
-
ns
UB, LB Valid to End of Write
t
BW
8
-
10
-
12
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
6
0
7
0
9
ns
Data to Write Time Overlap
t
DW
6
-
7
-
9
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
3
-
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB, LB=V
IL
)
t
AA
t
RC
t
OH