KM616FV8000 Family
Preliminary
Revision 0.0
July 1999
1
CMOS SRAM
Document Title
512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
0.0
Remark
Preliminary
History
Initial draft
Draft Date
July 23, 1999
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
KM616FV8000 Family
Preliminary
Revision 0.0
July 1999
2
CMOS SRAM
512K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
GENERAL DESCRIPTION
The KM616FV8000 families are fabricated by SAMSUNG
s
advanced full CMOS process technology. The families support
various operating temperature ranges and have small package
for user flexibility of system design. The families also support
low data retention voltage for battery back-up operation with low
data retention current.
FEATURES
Process Technology: Full CMOS
Organization: 512K x16
Power Supply Voltage: 3.0~3.6V
Low Data Retention Voltage: 1.5V(Min)
Three state output and TTL Compatible
Package Type: 44-TSOP2-400F/R
PRO
DUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Typ.)
Operating
(I
CC1
, Max)
KM616FV8000
Commercial(0~70
C)
3.0~3.6V
55
1)
/70ns
0.5
A
4mA
44-TSOP2-400F/R
KM616FV8000I
Industrial(-40~85
C)
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Row
select
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
I/O
9
~I/O
16
Vcc
Vss
Precharge circuit.
Memory array
1024 rows
512
16 columns
I/O Circuit
Column select
PIN DESCRIPTION
WE
OE
UB
CS1
LB
Control Logic
CS2
Row
Addresses
Column Addresses
Name
Function
Name
Function
CS
Chip Select Input
Vcc
Power
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
UB
Upper Byte(I/O
9
~
16
)
A
0
~A
18
Address Inputs
LB
Lower Byte(I/O
1
~
8
)
I/O
1
~I/O
16
Data Inputs/Outputs
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A18
A17
A16
A15
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
44-TSOP2
Forward
44-TSOP2
Reverse
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
A12
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A14
A13
A12
A13
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A18
A17
A16
A15
A14
KM616FV8000 Family
Preliminary
Revision 0.0
July 1999
3
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70
C)
Industrial Temperature Products(-40~85
C)
Part Name
Function
Part Name
Function
KM616FV8000T-5
KM616FV8000T-7
KM616FV8000R-5
KM616FV8000R-7
44-TSOP2-F, 55ns, 3.3V
44-TSOP2-F, 70ns, 3.3V
44-TSOP2-R, 55ns, 3.3V
44-TSOP2-R, 70ns, 3.3V
KM616FV8000TI-5
KM616FV8000TI-7
KM616FV8000TI-5
KM616FV8000TI-7
44-TSOP2-F, 55ns, 3.3V
44-TSOP2-F, 70ns, 3.3V
44-TSOP2-R, 55ns, 3.3V
44-TSOP2-R, 70ns, 3.3V
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.2 to 3.6
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 4.0
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-55 to 150
C
Operating Temperature
T
A
-40 to 85
C
FUNCTIONAL DESCRIPTION
Note : X means don
t care. (Must be low or high state)
CS
OE
WE
LB
UB
I/O
1~8
I/O
9~16
Mode
Power
H
X
X
X
X
High-Z
High-Z
Deselected
Standby
L
H
H
X
X
High-Z
High-Z
Output Disabled
Active
L
X
X
H
H
High-Z
High-Z
Output Disabled
Active
L
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
L
H
L
L
Dout
Dout
Word Read
Active
L
X
L
L
H
Din
High-Z
Lower Byte Write
Active
L
X
L
H
L
High-Z
Din
Upper Byte Write
Active
L
X
L
L
L
Din
Din
Word Write
Active
KM616FV8000 Family
Preliminary
Revision 0.0
July 1999
4
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. Commercial products:T
A
=0 to 70
C, otherwise specified
Industrial products:T
A
=-40 to 85
C, otherwise specified
2. Overshoot: V
CC
+2.0V in case of pulse width
20ns.
3. Undershoot: -2.0V in case of pulse width
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
3.0
3.3
3.6
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.2
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
1. Super low power product=10
A with special handling.
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH,
CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS
1
=V
IL,
CS
2
=V
IH
, WE=V
IH
, V
IN
=V
IH
or V
IL
-
-
2
mA
Average operating current
I
CC1
Cycle time=1
s, 100%duty, I
IO
=0mA, CS
1
0.2V,
CS
2
Vcc-0.2V, V
IN
0.2V or V
IN
VCC-0.2V
-
-
4
mA
I
CC2
Cycle time=Min, I
IO
=0mA, 100% duty,
CS
1
=V
IL
, CS
2
=V
IH,
VIN=V
IL
or V
IH
-
-
45
mA
Output low voltage
V
OL
I
OL
= 2.1mA
0.4
V
Output high voltage
V
OH
I
OH
= -1.0mA
2.2
V
Standby Current(TTL)
I
SB
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs=V
IH
or V
IL
-
-
0.3
mA
Standby Current(CMOS)
I
SB1
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or
CS
2
0.2V(CS
2
controlled), Other inputs=0~Vcc
-
0.5
30
1)
A
KM616FV8000 Family
Preliminary
Revision 0.0
July 1999
5
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1.
CS
1
Vcc-0.2V,CS
2
Vcc-0.2V(CS
1
controlled) or CS
2
Vcc-0.2V(CS
2
controlled).
2. Super low power product=4
A with special handling.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
Vcc-0.2V
1)
1.5
-
3.6
V
Data retention current
I
DR
Vcc=1.5V, CS
1
Vcc-0.2V
1)
-
0.5
6
2)
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
tRC
-
-
AC CHARACTERISTICS
(Vcc=3.0~3.6V, Commercial Products: T
A
=0 to 70
C, Industrial products: T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO1
, t
CO2
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
LB, UB valid to data output
t
BA
-
55
-
70
ns
Chip select to low-Z output
t
LZ1
, t
LZ1
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
LB, UB enable to low-Z output
t
BLZ
10
-
10
-
ns
Output hold from address change
t
OH
10
-
10
-
ns
Chip disable to high-Z output
t
HZ1
, t
HZ1
0
20
0
25
ns
OE disable to high-Z output
t
OHZ
0
20
0
25
ns
UB, LB disable to high-Z output
t
BHZ
0
20
0
25
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW1
, t
CW2
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
55
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
LB, UB valid to end of write
t
BW
45
-
60
-
ns
C
L
1)
1. Including scope and jig capacitance
R
2
2)
R
1
2)
V
TM
3)
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.8V
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