KM616V1002C/CL, KM616V1002CI/CLI
CMOS SRAM
Revision 3.0
- 1 -
March 1999
for AT&T
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
Rev. 2.1
Rev. 2.2
Rev. 3.0
Remark
Preliminary
Final
Final
Final
Final
Final
History
Initial release with Preliminary.
Release to Final Data Sheet.
1.1. Delete Preliminary.
1.2. Changed DC characteristics.
Added 48-fine pitch BGA.
Changed device part name for FP-BGA.
ex) KM616V1002CZ -> KM616V1002CF
Changed device ball name for FP-BGA.
1. Added 10ns speed for FP-BGA only.
2. Changed Standby Current.
3. Added Data Retention Characteristics.
Item
Previous
Changed
I
CC
12ns
85mA
95mA
15ns
83mA
93mA
20ns
80mA
90mA
Item
Previous
Changed
Symbol
Z
F
Previous
Changed
I/O1 ~ I/O8
I/O9 ~ I/O16
I/O9 ~ I/O16
I/O1 ~ I/O8
Item
Previous
Changed
Standby Current(Isb1)
0.3mA
0.5mA
Draft Data
Aug. 5. 1998
Sep. 7. 1998
Sep. 17. 1998
Nov. 5. 1998
Dec. 10. 1998
Mar. 2. 1999
KM616V1002C/CL, KM616V1002CI/CLI
CMOS SRAM
Revision 3.0
- 2 -
March 1999
for AT&T
64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)
The KM616V1002C is a 1,048,576-bit high-speed Static Ran-
dom Access Memory organized as 65,536 words by 16 bits.
The KM616V1002C uses 16 common input and output lines
and has at output enable pin which operates faster than
address access time at read cycle. Also it allows that lower and
upper byte access by data byte control (UB, LB). The device is
fabricated using SAMSUNG
s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The KM616V1002C is packaged in a 400mil 44-pin plastic SOJ
or TSOP2 forward or 48-Fine pitch BGA.
GENERAL DESCRIPTION
FEATURES
Fast Access Time 10
*
,12,15,20ns(Max.)
Low Power Dissipation
Standby (TTL) : 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
Operating KM616V1002C/CL - 10: 105mA(Max.)
KM616V1002C/CL - 12: 95mA(Max.)
KM616V1002C/CL - 15: 93mA(Max.)
KM616V1002C/CL - 20: 90mA(Max.)
Single 3.3
0.3V Power Supply
TTL Compatible Inputs and Outputs
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
2V Minimum Data Retention; L-ver. only
Center Power/Ground Pin Configuration
Data Byte Control: LB: I/O
1
~ I/O
8
, UB: I/O
9
~ I/O
16
Standard Pin Configuration:
KM616V1002CJ: 44-SOJ-400
KM616V1002CT: 44-TSOP2-400F
KM616V1002CF: 48-Fine pitch BGA with 0.75 Ball pitch
* FP-BGA only.
Clk Gen.
I/O
1
~I/O
8
OE
UB
CS
FUNCTIONAL BLOCK DIAGRAM
R
o
w
S
e
l
e
c
t
Data
Cont.
Column Select
A
10
A
11
A
12
A
13
A
14
A
15
CLK
Gen
.
Pre-Charge Circuit
Memory Array
512 Rows
128x16 Columns
I/O Circuit &
A
0
I/O
9
~I/O
16
Data
Cont.
WE
LB
KM616V1002C/CL -10/12/15/20
Commercial Temp.
KM616V1002CI/CLI -10/12/15/20
Industrial Temp.
ORDERING INFORMATION
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
9
A
8
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
15
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
LB
Lower-byte Control(I/O
1
~I/O
8
)
UB
Upper-byte Control(I/O
9
~I/O
16
)
I/O
1
~ I/O
16
Data Inputs/Outputs
V
CC
Power(+3.3V)
V
SS
Ground
N.C
No Connection
KM616V1002C/CL, KM616V1002CI/CLI
CMOS SRAM
Revision 3.0
- 3 -
March 1999
for AT&T
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
,
V
OUT
-0.5 to 4.6
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-0.5 to 4.6
V
Power Dissipation
P
d
1
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
Commercial
T
A
0 to 70
C
Industrial
T
A
-40 to 85
C
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
= to 70
C)
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
8ns) for I
20mA.
*** V
IH
(Max) = V
CC +
2.0V a.c(Pulse Width
8ns) for I
20mA
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
3.0
3.3
3.6
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.0
-
V
CC
+0.5***
V
Input Low Voltage
V
IL
-0.5**
-
0.8
V
LB
OE
A0
A1
A2
N.C
I/O1
UB
A3
A4
CS
I/O9
I/O2
I/O3
A5
A6
I/O11
I/O10
Vss
I/O4
N.C
A7
I/O12
Vcc
Vcc
I/O5
N.C
N.C
I/O13
Vss
I/O7
I/O6
A14
A15
I/O14
I/O15
I/O8
N.C
A12
A13
WE
I/O16
N.C
A8
A9
A10
A11
N.C
1
2
3
4
5
6
A
B
C
D
E
F
G
H
48-CSP
PIN CONFIGURATION(TOP VIEW)
SOJ/
TSOP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A
15
A
14
A
13
OE
UB
LB
I/O
16
I/O
15
I/O
14
I/O
13
Vss
Vcc
I/O
12
I/O
11
I/O
10
I/O
9
N.C
A
12
A
11
A
10
A
9
N.C
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
I/O
3
I/O
4
Vcc
Vss
I/O
5
I/O
6
I/O
7
I/O
8
WE
A
5
A
6
A
7
A
8
N.C
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
KM616V1002C/CL, KM616V1002CI/CLI
CMOS SRAM
Revision 3.0
- 4 -
March 1999
for AT&T
TEST CONDITIONS*
* The above test conditions are also applied at industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
C, V
CC
=3.3
0.3V, unless otherwise noted.)
Output Loads(B)
D
OUT
5pF*
319
353
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+3.3V
* Including Scope and Jig Capacitance
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
CAPACITANCE*
(T
A
=25
C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
C
I/O
V
I/O
=0V
-
8
pF
Input Capacitance
C
IN
V
IN
=0V
-
6
pF
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70
C, Vcc=3.3
0.3V, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
** FP-BGA only.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
IN
=V
SS
to
V
CC
-2
2
A
Output Leakage Current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to
V
CC
-2
2
A
Operating Current
I
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
= V
IH
or
V
IL,
I
OUT
=0mA
10ns
**
-
105
mA
12ns
-
95
15ns
-
93
20ns
-
90
Standby Current
I
SB
Min. Cycle, CS=V
IH
-
30
mA
I
SB1
f=0MHz, CS
V
CC
-0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V
Normal
-
5
mA
L-Ver.
-
0.5
Output Low Voltage Level
V
OL
I
OL
=8mA
-
0.4
V
Output High Voltage Level
V
OH
I
OH
=-4mA
2.4
-
V
KM616V1002C/CL, KM616V1002CI/CLI
CMOS SRAM
Revision 3.0
- 5 -
March 1999
for AT&T
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
** FP-BGA only.
Parameter
Symbol
KM616V1002C/
CL-10**
KM616V1002C/
CL-12
KM616V1002C/
CL-15
KM616V1002C/
CL-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
10
-
12
-
15
-
20
-
ns
Chip Select to End of Write
t
CW
7
-
8
-
9
-
10
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
7
-
8
-
9
-
10
-
ns
Write Pulse Width(OE High)
t
WP
7
-
8
-
9
-
10
-
ns
Write Pulse Width(OE Low)
t
WP1
10
-
12
-
15
-
20
-
ns
UB, LB Valid to End of Write
t
BW
7
-
8
-
9
-
10
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
5
0
6
0
7
0
9
ns
Data to Write Time Overlap
t
DW
5
-
6
-
7
-
8
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
3
-
3
-
ns
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
**
FP-BGA only.
Parameter
Symbol
KM616V1002C/
CL-10**
KM616V1002C/
CL-12
KM616V1002C/
CL-15
KM616V1002C/
CL-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
10
-
12
-
15
-
20
-
ns
Address Access Time
t
AA
-
10
-
12
-
15
-
20
ns
Chip Select to Output
t
CO
-
10
-
12
-
15
-
20
ns
Output Enable to Valid Output
t
OE
-
5
-
6
-
7
-
9
ns
UB, LB Access Time
t
BA
-
5
-
6
-
7
-
9
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
3
-
ns
UB, LB Enable to Low-Z Output
t
BLZ
0
-
0
-
0
-
0
-
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
5
0
6
-
7
-
9
ns
Output Disable to High-Z Output
t
OHZ
0
5
0
6
-
7
-
9
ns
UB, LB Disable to High-Z Output
t
BHZ
0
5
0
6
-
7
-
9
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
t
PU
0
-
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
t
PD
-
10
-
12
-
15
-
20
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB, LB=V
IL
t
AA
t
RC
t
OH
PDF 
ZIP