KM68FU8100 Family
Preliminary
Revision 0.0
August 1999
1
CMOS SRAM
Document Title
1M x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
0.0
Remark
Preliminary
History
Initial draft
Draft Date
August 25, 1999
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
KM68FU8100 Family
Preliminary
Revision 0.0
August 1999
2
CMOS SRAM
1M x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM
GENERAL DESCRIPTION
The KM68FU8100 families are fabricated by SAMSUNG
s
advanced full CMOS process technology. The families support
industrial operating temperature ranges and have chip scale
package for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.
FEATURES
Process Technology: Full CMOS
Organization: 1M x8
Power Supply Voltage: 2.7~3.3V
Low Data Retention Voltage: 1.5V(Min)
Three state output and TTL Compatible
Package Type: 44-TSOP2-400F/R, 48-FBGA-8.00x12.00
Name
Function
Name
Function
CS
1
, CS
2
Chip Select Inputs
A
0
~A
19
Address Inputs
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
I/O
1
~I/O
16
Data Inputs/Outputs
DNU
Do Not Use
PRO
DUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Typ.)
Operating
(I
CC1
, Max)
KM68FU8100I
Industrial(-40~85
C)
2.7~3.3V
55
1)
/70ns
0.5
A
3mA
44-TSOP2-400F/R
48-FBGA-8.00x12.00
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Clk gen.
Row
select
I/O
1
~I/O
8
Data
cont
Data
cont
Vcc
Vss
Precharge circuit.
Memory array
2048 rows
256
8 columns
I/O Circuit
Column select
WE
OE
CS1
Control Logic
CS2
Row
Addresses
Column Addresses
DNU
OE
A0
A1
A2
CS2
DNU
DNU
A3
A4
CS1
DNU
I/O1
DNU
A5
A6
DNU
I/O5
Vss
I/O2
A17
A7
I/O6
Vcc
Vcc
I/O3
V
CC
A16
I/O7
Vss
I/O4
DNU
A14
A15
DNU
I/O8
DNU
DNU
A12
A13
WE
DNU
A18
A8
A9
A10
A11
A19
1
2
3
4
5
6
A
B
C
D
E
F
G
H
48-FBGA: Top View (Ball Down)
A4
A3
A2
A1
A0
CS1
DNU
DNU
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
DNU
DNU
WE
A19
A18
A17
A16
A5
A6
A7
OE
CS2
A8
DNU
DNU
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
DNU
DNU
A9
A10
A11
A12
44-TSOP2
Forward
44-TSOP2
Reverse
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
A7
OE
CS2
A8
DNU
DNU
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
DNU
DNU
A9
A10
A11
A12
A13
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
A14
A13
A14
A4
A3
A2
A1
A0
CS1
DNU
DNU
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
DNU
DNU
WE
A19
A18
A17
A16
A15
KM68FU8100 Family
Preliminary
Revision 0.0
August 1999
3
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85
C)
Part Name
Function
KM68FU8100TI-5
KM68FU8100TI-7
KM68FU8100RI-5
KM68FU8100RI-7
KM68FU8100FI-5
KM68FU8100FI-7
44-TSOP2-F, 55ns, 3.0V
44-TSOP2-F, 70ns, 3.0V
44-TSOP2-R, 55ns, 3.0V
44-TSOP2-R, 70ns, 3.0V
48-FBGA, 55ns, 3.0V
48-FBGA, 70ns, 3.0V
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.2 to 3.6
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 4.0
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-55 to 150
C
Operating Temperature
T
A
-40 to 85
C
FUNCTIONAL DESCRIPTION
1. X means don
t care. (Must be low or high state)
CS
1
CS
2
OE
WE
I/O
1~8
Mode
Power
H
X
1)
X
1)
X
1)
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
X
1)
L
Din
Write
Active
KM68FU8100 Family
Preliminary
Revision 0.0
August 1999
4
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. T
A
=-40 to 85
C, otherwise specified
2. Overshoot: V
CC
+2.0V in case of pulse width
20ns.
3. Undershoot: -2.0V in case of pulse width
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
2.7
3.0
3.3
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.2
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.4
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
1. Super low power product=10
A with special handling.
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH,
CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS
1
=V
IL,
CS
2
=V
IH
, WE=V
IH
, V
IN
=V
IH
or V
IL
-
-
2
mA
Average operating current
I
CC1
Cycle time=1
s, 100%duty, I
IO
=0mA, CS
1
0.2V,
CS
2
Vcc-0.2V, V
IN
0.2V or V
IN
VCC-0.2V
-
-
3
mA
I
CC2
Cycle time=Min, I
IO
=0mA, 100% duty,
CS
1
=V
IL
, CS
2
=V
IH,
VIN=V
IL
or V
IH
-
-
35
mA
Output low voltage
V
OL
I
OL
= 2.1mA
0.4
V
Output high voltage
V
OH
I
OH
= -1.0mA
2.2
V
Standby Current(TTL)
I
SB
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs=V
IH
or V
IL
-
-
0.3
mA
Standby Current(CMOS)
I
SB1
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V(CS
1
controlled) or
CS
2
0.2V(CS
2
controlled), Other inputs=0~Vcc
-
0.5
25
1)
A
KM68FU8100 Family
Preliminary
Revision 0.0
August 1999
5
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.2 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1.
CS
1
Vcc-0.2V,CS
2
Vcc-0.2V(CS
1
controlled) or CS
2
Vcc-0.2V(CS
2
controlled).
2. Super low power product=4
A with special handling.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
Vcc-0.2V
1)
1.5
-
3.3
V
Data retention current
I
DR
Vcc=1.5V, CS
1
Vcc-0.2V
1)
-
0.5
6
2)
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
tRC
-
-
AC CHARACTERISTICS
(Vcc=2.7~3.3V, T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO1
, t
CO2
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
Chip select to low-Z output
t
LZ1
, t
LZ2
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ1
, t
HZ2
0
20
0
25
ns
OE disable to high-Z output
t
OHZ
0
20
0
25
ns
Output hold from address change
t
OH
10
-
10
-
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW1
, t
CW2
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
50
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
20
-
25
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
C
L
1)
1. Including scope and jig capacitance
R
2
2)
R
1
2)
V
TM
3)
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.8V
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