68V512B.PDF
KM68V512B, KM68U512B Family
CMOS SRAM
Revision 1.0
August 1998
1
Document Title
64Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0
1.0
Remark
Advance
Final
History
Design target
Finalize
Draft Data
November 25, 1997
August 27, 1998
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
KM68V512B, KM68U512B Family
CMOS SRAM
Revision 1.0
August 1998
2
64Kx8 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The KM68V512B and KM68U512B families are fabricated
by SAMSUNG
s advanced CMOS process technology. The
families support various operating temperature ranges and
has various package types for user flexibility of system
design. The family also support low data retention voltage
for battery back-up operation with low data retention current.
FEATURES
Process Technology : TFT
Organization : 64Kx8
Power Supply Voltage
KM68V512A family : 3.0~3.6V
KM68U512A family : 2.7~3.3V
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : 32-TSOP1-0820F, 32-TSOP1-0813.4F
PIN DESCRIPTION
Name
Function
Name
Function
CS
1
,CS
2
Chip Select Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
OE
Output Enable
Vcc
Power
WE
Write Enable Input
Vss
Ground
A
0
~A
15
Address Inputs
N.C
No Connection
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family
Operating
Temperature
V
CC
Range
Speed (ns)
Power Dissipation
PKG Type
Standby
(Isb
1
, Max)
Operating
(Icc
2
, Max)
KM68V512BL-L
Commercial(0~70
C)
3.0 ~ 3.6V
85
1)
/100ns
10
A
30mA
32-TSOP1-F
32-sTSOP1-F
KM68U512BL-L
2.7 ~ 3.3V
25mA
KM68V512BLI-L
Industrial(-40~85
C)
3.0 ~ 3.6V
30mA
KM68U512BLI-L
2.7 ~ 3.3V
25mA
FUNCTIONAL BLOCK DIAGRAM
32-TSOP
Type1 - Forward
32-
S
TSOP
TYPE1 - Forward
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
N.C
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
N.C
A14
A12
A7
A6
A5
A4
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Precharge circuit.
Memory array
512 rows
128
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A0
A1
A2
A3
A9
A11
A10
A4
A5
A6
A7
A8
A12
A14
CS1
CS2
WE
I/O
1
Data
cont
Data
cont
OE
I/O
8
A13
A15
Control
logic
KM68V512B, KM68U512B Family CMOS SRAM
Revision 1.0
August 1998
3
PRODUCT LIST
Commercial Temperature Products(0~70
C)
Industrial Temperature Products(-40~85
C)
Part Name
Function
Part Name
Function
KM68V512BLT-8L
KM68V512BLT-10L
KM68U512BLT-8L
KM68U512BLT-10L
32-TSOP1 F, 85ns, 3.3V, LL
32-TSOP1 F, 100ns, 3.3V, LL
32-TSOP1 F, 85ns, 3.0V, LL
32-TSOP1 F, 100ns, 3.0V, LL
KM68V512BLTI-8L
KM68V512BLTI-10L
KM68V512BLTGI-8L
KM68V512BLTGI-10L
KM68U512BLTI-8L
KM68U512BLTI-10L
KM68U512BLTGI-8L
KM68U512BLTGI-10L
32-TSOP1 F, 85ns, 3.3V, LL
32-TSOP1 F, 100ns, 3.3V, LL
32-sTSOP1 F, 85ns,3.3V,LL
32-sTSOP1 F, 100ns,3.3V,LL
32-TSOP1 F, 85ns, 3.0V, LL
32-TSOP1 F, 100ns, 3.0V, LL
32-sTSOP1 F, 85ns, 3.0V, LL
32-sTSOP1 F, 100ns,3.0V, LL
FUNCTIONAL DESCRIPTION
1. X means don
t care (Must be in high or low states)
CS
1
CS
2
OE
WE
I/O
Mode
Power
H X
1)
X
1)
X
1)
High-Z Deselected Standby
X
1)
L X
1)
X
1)
High-Z Deselected Standby
L H H H High-Z Output Disabled Active
L H L H Dout Read Active
L H X
1)
L Din Write Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss V
IN
,V
OUT
-0.5 to V
CC
+0.5 V -
Voltage on Vcc supply relative to Vss V
CC
-0.3 to 4.6 V -
Power Dissipation P
D
1 W -
Storage temperature T
STG
-65 to 150
C -
Operating Temperature T
A
0 to 70
C KM68V512BL, KM68U512BL
-40 to 85
C KM68V512BLI, KM68U512BLI
Soldering temperature and time T
SOLDER
260
C, 10sec (Lead Only) - -
KM68V512B, KM68U512B Family
CMOS SRAM
Revision 1.0
August 1998
4
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. Commercial Product : T
A
=0 to 70
C, otherwise specified
Industrial Product : T
A
=-40 to 85
C, otherwise specified
2. Overshoot : V
CC
+3.0V in case of pulse width
30ns
3. Undershoot : -3.0V in case of pulse width
30ns
4. Overshoot and undershoot are sampled, not 100% tested
Item
Symbol
Product
Min
Typ
Max
Unit
Supply voltage
Vcc
KM68V512B Family
3.0
3.3
3.6
V
KM68U512B Family
2.7
3.0
3.3
V
Ground
Vss
All Family
0
0
0
V
Input high voltage
V
IH
KM68V512B, KM68U512B Family
2.2
-
Vcc+0.3V
2)
V
Input low voltage
V
IL
KM68V512B, KM68U512B Family
-0.3
3)
-
0.6
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
6
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
8
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply
I
CC
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL,
Read
-
-
5
mA
Average operating current
I
CC1
Cycle time=1
s, 100% duty, I
IO
=0mA,
CS
1
0.2V, CS
2
Vcc-0.2V, V
IN
0.2V or V
IN
Vcc-0.2V
-
-
5
mA
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA
CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IL
or V
IH
KM68V512B
-
-
30
mA
KM68U512B
-
-
25
mA
Output low voltage
V
OL
I
OL
=2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs=V
IL
or V
IH
-
-
0.3
mA
Standby Current (CMOS)
I
SB1
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V, or CS
2
0.2V
,
Other inputs=0~Vcc
-
-
10
A
KM68V512B, KM68U512B Family
CMOS SRAM
Revision 1.0
August 1998
5
C
L
*
* Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
1)
=100pF+1TTL
1. 85ns part tested with 30pF test load.
AC CHARACTERISTICS
(KM68V512B Family:Vcc=3.0~3.6V, KM68U512B Family:Vcc=2.7~3.3V,
Commercial products:T
A
=0 to 70
C, Industrial products:T
A
=-40 to 85
C
)
Parameter List
Symbol
Speed Bins
Units
85ns
100ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
85
-
100
-
ns
Address access time
t
AA
-
85
-
100
ns
Chip select to output
t
CO
-
85
-
100
ns
Output enable to valid output
t
OE
-
45
-
50
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
30
0
30
ns
Output disable to high-Z output
t
OHZ
0
20
0
20
ns
Output hold from address change
t
OH
10
-
15
-
ns
Write
Write cycle time
t
WC
85
-
100
-
ns
Chip select to end of write
t
CW
70
-
80
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
70
-
80
-
ns
Write pulse width
t
WP
60
-
70
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write recovery time
t
WR1
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
30
ns
Data to write time overlap
t
DW
35
-
40
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
Item
Sym
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
Vcc-2.0V, CS
2
Vcc-2.0V or CS
2
0.2V
2.0
-
3.6
V
Data retention current
I
DR
Vcc=3.0V, CS
1
Vcc-0.2V, CS
2
Vcc-0.2V or CS
2
0.2V
-
-
10
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
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