- 1 -

184pin Unbuffered DDR SDRAM MODULE

Rev. 0.0 Sep. 1999

KMM368L3223AT

Preliminary

Performance range

·
·
·
·
·
·
·

· Power supply

Vdd: 2.5V

0.2V

Power: G - normal, F - Low power

· MRS cycle with address key programs

CAS Latency (Access from column address):2,2.5

Burst length ;2, 4, 8

Data scramble ;Sequential & Interleave

· Serial presence detect with EEPROM

PCB : Height 1450 (mil), double sided component

Part No.

Max Freq.

Interface

KMM

368L3223AT-G(F)Z

133MHz(7.5ns@CL=2)

SSTL_2

KMM

368L3223AT-G(F)Y

133MHz(7.5ns@CL=2.5)

KMM

368L3223AT-G(F)0

100MHz(10ns@CL=2)

2. FEATURE

1. GENERAL DESCRIPTION

PIN DESCRIPTION

* These pins are not used in this module.

Pin Name

Function

A0 ~ A12

Address input (Multiplexed)

BA0 ~ BA1

Bank Select Address

DQ0 ~ DQ63

Data input/output

DQS0 ~ DQS7

Data Strobe input/output

CK0,CK0 ~ CK2, CK2

Clock input

CKE0

Clock enable input

CS0

Chip select input

RAS

Row address strobe

CAS

Column address strobe

Write enable

DM0 ~ DM7

Data - in mask

VDD

Power supply (2.5V)

VDDQ

Power Supply for DQs(2.5V)

VSS

Ground

VREF

Power supply for reference

V33

Serial EEPROM Power
Supply (3.3V)

SDA

Serial data I/O

SCL

Serial clock

SA0 ~ 2

Address in EEPROM

Write protection

VDDID

VDD identification flag

Don

t use

No connection

3. PIN CONFIGURATIONS (Front side/back side)

Pin

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

Front

VREF

DQ0
VSS
DQ1

DQS0

DQ2
VDD
DQ3

NC
NC

VSS
DQ8
DQ9

DQS1

VDDQ

CK0

/CK0

VSS

DQ10
DQ11
CKE0

VDDQ

DQ16
DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

Pin

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

53
54
55
56
57
58
59
60
61

Front

DQ24

VSS

DQ25

DQS3

VDD

DQ26
DQ27

VSS

*CB0
*CB1

VDD

*DQS8

*CB2

VSS

*CB3

BA1

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35
DQ40

Pin

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92

Front

VDDQ

/WE

DQ41

/CAS

VSS

DQS5

DQ42
DQ43

VDD

DQ48
DQ49

VSS

/CK2

CK2

VDDQ

DQS6

DQ50
DQ51

VSS

VDDID

DQ56
DQ57

VDD

DQS7

DQ58
DQ59

VSS

SDA

SCL

Pin

93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123

Back

VSS
DQ4
DQ5

VDDQ

DM0
DQ6
DQ7

VSS

NC
NC

*A13

VDDQ

DQ12
DQ13

DM1
VDD

DQ14
DQ15

*CKE1
VDDQ

*BA2

DQ20

A12

VSS

DQ21

A11

DM2
VDD

DQ22

DQ23

Pin

124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

145
146
147
148
149
150
151
152
153

Back

VSS

DQ28
DQ29

VDDQ

DM3

DQ30

VSS

DQ31

*CB4
*CB5

VDDQ

CK1

/CK1

VSS

*DM8

A10

*CB6

VDDQ

*CB7

VSS

DQ36
DQ37

VDD
DM4

DQ38
DQ39

VSS

DQ44

Pin

154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184

Back

/RAS

DQ45

VDDQ

/CS0

*/CS1

DM5

VSS

DQ46
DQ47

VDDQ

DQ52
DQ53

VDD
DM6

DQ54
DQ55

VDDQ

DQ60
DQ61

VSS

DM7

DQ62
DQ63

VDDQ

SA0
SA1
SA2
V33

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

KEY

KMM368L3223AT DDR SDRAM 184pin DIMM

32Mx64 DDR SDRAM 184pin DIMM based on 32Mx8

The Samsung KMM368L3223AT is 32M bit x 64 Double Data

Rate SDRAM high density memory modules based on first

gen of 256Mb DDR SDRAM respectively.

The Samsung KMM368L3223AT consists of eight CMOS 32M

x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-

II(400mil) packages mounted on a 184pin glass-epoxy sub-

strate. Four 0.1uF decoupling capacitors are mounted on the

printed circuit board in parallel for each DDR SDRAM. The

KMM368L3223AT is Dual In-line Memory Modules and inten-

ded for mounting into 184pin edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. Data I/O transactions are possible on both

edges of DQS. Range of operating frequencies, programmable

latencies and burst lengths allow the same device to be useful

for a variety of high bandwidth, high performance memory sys-

tem applications.

- 2 -

184pin Unbuffered DDR SDRAM MODULE

Rev. 0.0 Sep. 1999

KMM368L3223AT

Preliminary

5. Functional Block Diagram

DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3

I/O 7
I/O 6
I/O 1
I/O 0

DM0

I/O 5
I/O 4
I/O 3
I/O 2

DQ12
DQ13
DQ14

DQ8
DQ9
DQ10
DQ11

I/O 7
I/O 6
I/O 1
I/O 0

I/O 5
I/O 4
I/O 3

DM1

DQ20
DQ21
DQ22
DQ23

DQ16
DQ17
DQ18
DQ19

I/O 7
I/O 6
I/O 1
I/O 0

I/O 5
I/O 4
I/O 3
I/O 2

DM2

DQ28
DQ29
DQ30
DQ31

DQ24
DQ25
DQ26
DQ27

I/O 7
I/O 6
I/O 1
I/O 0

I/O 5
I/O 4
I/O 3
I/O 2

DM3

DQ36
DQ37
DQ38
DQ39

DQ32
DQ33
DQ34
DQ35

I/O 7
I/O 6
I/O 1
I/O 0

DM4

I/O 5
I/O 4
I/O 3
I/O 2

DQ44
DQ45
DQ46
DQ47

DQ40
DQ41
DQ42
DQ43

I/O 7
I/O 6
I/O 1
I/O 0

I/O 5
I/O 4
I/O 3
I/O 2

DM5

DQ52
DQ53
DQ54
DQ55

DQ48
DQ49
DQ50
DQ51

I/O 7
I/O 6
I/O 1
I/O 0

I/O 5
I/O 4
I/O 3
I/O 2

DQ60
DQ61
DQ62
DQ63

DQ56
DQ57
DQ58
DQ59

I/O 7
I/O 6
I/O 1
I/O 0

I/O 5
I/O 4
I/O 3
I/O 2

DM7

A0 - An

A0-An: SDRAMs D0 - D7

Serial PD

SA0

SA1

SA2

SCL

SDA

RAS

RAS: SDRAMs D0 - D7

CAS

CAS: SDRAMs D0 - D7

CKE0

CKE: SDRAMs D0 - D7

WE: SDRAMs D0 - D7

CS0

BA0 - BAn

BA0-BAn: SDRAMs D0 - D7

DQS0

DQS

DQS4

DQS1

DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6

DQS6

DQS7

DQ15

I/O 2

DQS

D0 - D7

DDQ

D0 - D7

VREF

Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships
must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD

VDDQ.

DDID

Strap: see Note 4

*Clock Net Wiring

Card
Edge

Dram1

Cap

Dram3

Cap

Dram5

Cap

R=120

*(Cap)

Cap will replace DRAM3

*If two DRAMs are loaded,

Dummy Cap = 3.0pF

* Clock Wiring

Clock
Input

SDRAMs

CK0/CK0
CK1/CK1
CK2/CK2

3 SDRAMs+3*Dummy Cap
2 SDRAMs+3*Dummy Cap
3 SDRAMs+3*DummyCap

47K

- 3 -

184pin Unbuffered DDR SDRAM MODULE

Rev. 0.0 Sep. 1999

KMM368L3223AT

Preliminary

6. ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-0.5 ~ 3.6

Voltage on V

supply relative to Vss

-1.0 ~ 4.6

Voltage on V

DDQ

supply relative to Vss

DDQ

-0.5 ~ 3.6

Storage temperature

STG

-55 ~ +150

Power dissipation

Short circuit current

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

7. POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to V

=0V, T

=0 to 70

Note

Parameter

Symbol

Min

Max

Unit

Note

Supply voltage(for device with a nominal V

of 2.5V)

2.3

2.7

I/O Supply voltage

DDQ

2.3

2.7

I/O Reference voltage

REF

1.15

1.35

I/O Termination voltage(system)

REF

-0.04

REF

+0.04

Input logic high voltage

(DC)

REF

+0.18

DDQ

+0.3

Input logic low voltage

(DC)

-0.3

REF

-0.18

Input Voltage Level, CK and CK inputs

(DC)

-0.3

DDQ

+0.3

Input Differential Voltage, CK and CK inputs

(DC)

0.36

DDQ

+0.6

Input leakage current

-5

Output leakage current

-5

Output High Current (V

OUT

= 1.95V)

-15.2

Output Low Current (V

OUT

= 0.35V)

15.2

1. Typically, the value of V

REF

is expected to be about 0.5*V

DDQ

of the transmitting device.

REF

is expected to track variation in V

DDQ

2. Peak to peak AC noise on V

REF

may not exceed 2% V

REF

(DC).

3. V

of the transmitting device must track V

REF

of the receiving device.

- 4 -

184pin Unbuffered DDR SDRAM MODULE

Rev. 0.0 Sep. 1999

KMM368L3223AT

Preliminary

8. DC CHARACTERISTICS

Recommended operating conditions Unless Otherwise Noted, T

=0 to 70

)

Note : 1. Measured with outputs open.

2. Refresh period is 64ms

Parameter

Symbol

Test Condition

CAS

Latency

Version

Unit Note

-Z

-Y

-0

Operating Current
(One Bank Active)

DD1

Burst=2 tRC

tRC(min), CL=2.5

OUT

=0mA, Active-Read-Precharge

T.B.D

Precharge Power-down Standby
Current

DD2

CKE

VIL(max), tCK=tCK(min), All banks idle

T.B.D

Precharge Standby Current
in Non Power-down mode

DD2

CKE

VIH(min), CS

VIH(min), tCK=tCK(min)

T.B.D

Active Standby Current
in Power-down mode

DD3

All banks idle,CKE

VIL(max),tCK=tCK(min)

T.B.D

Active Standby Current
in Non Power-down mode

DD3

One bank; Active-Precharge, tRC=tRAS(max),
tCK=tCK(min)

T.B.D

Operating Current(Read)

DD4R

Burst=2, tCK=tCK(min),
I

OUT

=0mA

2.5

T.B.D

Operating Current(Write)

DD4W

Burst=2, tCK=tCK(min)

2.5

T.B.D

Auto Refresh Current

DD5

RFC

(min)

T.B.D

Self Refresh Current

DD6

CKE

0.2V

T.B.D

9. AC Operating Conditions

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

VIH(AC)

VREF + 0.35

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

VIL(AC)

VREF - 0.35

Input Differential Voltage, CK and CK inputs

VID(AC)

0.7

VDDQ+0.6

Input Crossing Point Voltage, CK and CK inputs

VIX(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same.

- 5 -

184pin Unbuffered DDR SDRAM MODULE

Rev. 0.0 Sep. 1999

KMM368L3223AT

Preliminary

10.

AC OPERATING TEST CONDITIONS

=3.3V, V

DDQ

=2.5V, T

= 0 to 70

)

Parameter

Value

Unit

Note

Input reference voltage for Clock

0.5 * V

DDQ

Input signal maximum peak swing

1.5

Input signal minimum slew rate

1.0

V/ns

Input Levels(V

)

REF

+0.35/V

REF

-0.35

Input timing measurement reference level

REF

Output timing measurement reference level

Output load condition

See Load Circuit

(Fig. 1) Output Load Circuit (SSTL_2)

Output

Z0=50

LOAD

=30pF

REF

=0.5*V

DDQ

=50

=0.5*V

DDQ

11. Input/Output CAPACITANCE

=3.3V, V

DDQ

=2.5V, T

= 25

f=1MHz)

Parameter

Symbol

Min

Max

Unit

Input capacitance(A

~ A

, BA

~ BA

,RAS,CAS,

WE )

IN1

Input capacitance(CKE

)

IN2

Input capacitance(

)

IN3

Input capacitance(

CLK

, CLK

CLK

)

IN4

Data & DQS input/output capacitance(DQ

~DQ

)

OUT

Input capacitance(DM

~DM

)

IN5

- 6 -

184pin Unbuffered DDR SDRAM MODULE

Rev. 0.0 Sep. 1999

KMM368L3223AT

Preliminary

12. AC CHARACTERISTICS.

(These AC charicteristics were tested on the Component)

Parameter

Symbol

- Z(PC266@CL=2)

- Y(PC266@CL=2.5) - 0(PC200@CL=2)

Unit

Note

Min

Max

Min

Max

Min

Max

Row cycle time

tRC

Refresh row cycle time

tRFC

Row active time

tRAS

12K

RAS to CAS delay

tRCD

Row precharge time

tRP

Row active to Row active delay

tRRD

Write recovery time

tWR

tCK

Last data in to Read command

tCDLR

tCK

Last data in to Write command

tCDLW

tCK

Col. address to Col. address delay

tCCD

tCK

Clock cycle time

CL=2.0

tCK

7.5

CL=2.5

7.5

Clock high level width

tCH

0.45

0.55

0.45

0.55

0.45

0.55

tCK

Clock low level width

tCL

0.45

0.55

0.45

0.55

0.45

0.55

tCK

DQS-out access time from CK/CK

tDQSCK

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

Output data access time from CK/CK

tAC

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

Data strobe edge to ouput data edge

tDQSQ

-0.5

+0.5

-0.5

+0.5

-0.6

+0.6

Read Preamble

tRPRE

0.9

1.1

0.9

1.1

0.9

1.1

tCK

Read Postamble

tRPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Data out high impedence time from CK/CK tHZQ

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

CK to valid DQS-in

tDQSS

0.75

1.25

0.75

1.25

0.75

1.25

tCK

DQS-in setup time

tWPRES

DQS-in hold time

tWPREH

0.25

tCK

DQS-in high level width

tDQSH

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS-in low level width

tDQSL

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS-in cycle time

tDSC

0.9

1.1

0.9

1.1

0.9

1.1

tCK

Address and Control Input setup time

tIS

1.1

1.2

Address and Control Input hold time

tIH

1.1

1.2

Mode register set cycle time

tMRD

DQ & DM setup time to DQS

tDS

0.5

0.6

DQ & DM hold time to DQS

tDH

0.5

0.6

DQ & DM input pulse width

tDIPW

1.75

Power down exit time

tPDEX

Exit self refresh to write command

tXSW

116

- 7 -

184pin Unbuffered DDR SDRAM MODULE

Rev. 0.0 Sep. 1999

KMM368L3223AT

Preliminary

1. Maximum burst refresh of 8

2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced

to a specific voltage level, but specify when the device output is no longer driving.

3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from

High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,

DQS could be High at this time, depending on tDQSS.

4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,

but system performance (bus turnaround) will degrade accordingly.

Parameter

Symbol

PC266A

PC266B

PC200

Unit

Note

Min

Max

Min

Max

Min

Max

Exit self refresh to bank active command

tXSA

Exit self refresh to read command

tXSR

200

Cycle

Refresh interval time

256Mb

tREF

7.8

Output DQS valid window

tDV

0.35

tCK

DQS write postamble time

tWPST

0.25

tCK

Auto precharge write recovery + Precharge time

tDAL

- 8 -

184pin Unbuffered DDR SDRAM MODULE

Rev. 0.0 Sep. 1999

KMM368L3223AT

Preliminary

13.

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

t Care, H=Logic High, L=Logic Low)

COMMAND

CKEn-1

CKEn

RAS

CAS

0,1

/AP

11,

~ A

Note

Extended MRS

OP CODE

1, 2

Mode Register Set

OP CODE

1, 2

Refresh

Auto Refresh

Self
Refresh

Entry

Exit

Bank Active & Row Addr.

Row Address

Read &
Column Address

Auto Precharge Disable

Column

Address

)

Auto Precharge Enable

Write &
Column Address

Auto Precharge Disable

Column

Address

)

Auto Precharge Enable

4, 6

Burst Stop

Precharge

Bank Selection

All Banks

Active Power Down

Entry

Exit

Precharge Power Down Mode

Entry

Exit

No Operation Command

1. OP Code : Operand Code. A

~ A

& BA

~ BA

: Program keys. (@EMRS/MRS)

2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA

~ BA

: Bank select addresses.

If both BA

and BA

are "Low" at read, write, row active and precharge, bank A is selected.

If both BA

is "High" and BA

is "Low" at read, write, row active and precharge, bank B is selected.

If both BA

is "Low" and BA

is "High" at read, write, row active and precharge, bank C is selected.

If both BA

and BA

are "High" at read, write, row active and precharge, bank D is selected.

5. If A

/AP is "High" at row precharge, BA

and BA

are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t

after the end of burst.

7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

Note :

- 9 -

184pin Unbuffered DDR SDRAM MODULE

Rev. 0.0 Sep. 1999

KMM368L3223AT

Preliminary

Tolerances :

0.005(.13) unless otherwise specified.

The used device is 16Mx8 SDRAM, TSOP.
SDRAM Part NO : KM48L32331AT

14. PACKAGE DIMENSIONS

5.25

± 0.006

5.077

Units : Inches (Millimeters)

0.050

0.0078

±0.006

(0.20

0.15)

0.145 Max

0.050

0.0039

(1.270

0.10)

.
1

i
n

(
2

.
3

i
n

)

.
3

(
1

.
0

)

(1.270)

.
1

(
2

.
5

)

Detail B

0.089

(2.26)

(128.950)

(133.350

± 0.15

)

0.250

(6.350)

Detail A

0.157
(4.00)

0.071

(1.80)

.
1

(
4

.
0

)

(3.67 Max)

0.039

0.002

(1.000

0.050)

(3.80)

2.175

(6.62)

(64.77)

(49.53)

(19.80)

(
1

.
8

)

2.55

1.95

0.78

0.26

2.500

.
7

0.10 M

B A

0.10 M C

A M

0.1496

(3.00)

0.118

(2.00)

0.0787

(4.00)

0.1575

1.45

± 0.006

(36.83

±0.15)

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