DRAM MODULE
KMM372V320(8)0CS1
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Fast page mode cycle time,
t
PC
.
* NOTE :
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
I
CC1
*
I
CC2
I
CC3
*
I
CC4
*
I
CC5
I
CC6
*
I(
IL)
I(
OL)
V
OH
V
OL
Symbol
Speed
KMM372V3200CS1
KMM372V3280CS1
Unit
Min
Max
Min
Max
I
CC1
-5
-6
-
-
1998
1818
-
-
1458
1278
mA
mA
I
CC2
Don
t care
-
100
-
100
mA
I
CC3
-5
-6
-
-
1998
1818
-
-
1458
1278
mA
mA
I
CC4
-5
-6
-
-
1098
918
-
-
1098
918
mA
mA
I
CC5
Don
t care
-
30
-
30
mA
I
CC6
-5
-6
-
-
1998
1818
-
-
1998
1818
mA
mA
I
I(L)
I
O(L)
Don
t care
-10
-10
10
10
-10
-10
10
10
uA
uA
V
OH
V
OL
Don
t care
2.4
-
-
0.4
2.4
-
-
0.4
V
V
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current (RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
: Fast Page Mode Current * (RAS=V
IL
, CAS cycling :
t
PC
=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
V
IN
Vcc+0.3V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
V
OUT
Vcc)
: Output High Voltage Level (I
OH
= -2mA)
: Output Low Voltage Level (I
OL
= 2mA)
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70
C)
*1 : V
CC
+1.3V at pulse width
15ns, which is measured at V
CC
.
*2 : -1.3V at pulse width
15ns, which is measured at V
SS
.
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
3.0
0
2.0
-0.3
*2
3.3
0
-
-
3.6
0
V
CC
+0.3
*1
0.8
V
V
V
V
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
-0.5 to +4.6
-0.5 to +4.6
-55 to +125
36
50
V
V
C
W
mA
DRAM MODULE
KMM372V320(8)0CS1
CAPACITANCE
(T
A
= 25
C, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0, B0, A1 - A12]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0 - RAS3]
Input capacitance[CAS0, 1, 4, 5]
Input/Output capacitance[DQ0 - 71]
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ
-
-
-
-
-
20
20
73
20
24
pF
pF
pF
pF
pF
Test condition : V
ih
/V
il
=2.2/0.7V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
Symbol
-5
-6
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
90
110
ns
Read-modify-write cycle time
t
RWC
133
155
ns
Access time from RAS
t
RAC
50
60
ns
3,4,10
Access time from CAS
t
CAC
18
20
ns
3,4,5,11
Access time from column address
t
AA
30
35
ns
3,10,11
CAS to output in Low-Z
t
CLZ
5
5
ns
3,11
Output buffer turn-off delay
t
OFF
5
18
5
20
ns
6,11
Transition time(rise and fall)
t
T
1
50
1
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
18
20
ns
11
CAS hold time
t
CSH
48
58
ns
11
CAS pulse width
t
CAS
13
10K
15
10K
ns
RAS to CAS delay time
t
RCD
18
32
18
40
ns
4,11
RAS to column address delay time
t
RAD
13
20
13
25
ns
10,11
CAS to RAS precharge time
t
CRP
10
10
ns
11
Row address set-up time
t
ASR
5
5
ns
11
Row address hold time
t
RAH
8
8
ns
11
Column address set-up time
t
ASC
0
0
ns
Column address hold time
t
CAH
10
10
ns
Column address to RAS lead time
t
RAL
30
35
ns
11
Read command set-up time
t
RCS
0
0
ns
Read command hold referencde to CAS
t
RCH
0
0
ns
8
Read command hold referenced to RAS
t
RRH
-2
-2
ns
8,11
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to RAS lead time
t
RWL
20
20
ns
11
Write command to CAS lead time
t
CWL
13
15
ns
Data in set-up time
t
DS
-2
-2
ns
9,11
Data in hold time
t
DH
15
15
ns
9,11
Refresh period(4K & 8K)
t
REF
64
64
ms
Write command set-up time
t
WCS
0
0
ns
7
CAS to W delay time
t
CWD
36
40
ns
7
Column address to W delay time
t
AWD
48
55
ns
7
CAS prechange to W delay time
t
CPWD
53
60
ns
7
RAS ro W delay time
t
RWD
71
83
ns
7,11
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=3.3V
0.3V. See notes 1,2.)
DRAM MODULE
KMM372V320(8)0CS1
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=3.3V
0.3V. See notes 1,2.)
Parameter
Symbol
-5
-6
Unit
Note
Min
Max
Min
Max
CAS setup time(CAS-before-RAS refresh)
t
CSR
10
10
ns
11
CAS hold time(CAS-before-RAS refresh)
t
CHR
8
8
ns
11
RAS to CAS precharge time
t
RPC
3
3
ns
11
Access time from CAS precharge
t
CPA
35
40
ns
3,11
Fast page mode cycle time
t
PC
35
40
ns
Fast page mode read-modify-write cycle time
t
PRWC
76
85
ns
CAS precharge time(Fast page cycle)
t
CP
10
10
ns
RAS pulse width(Fast page cycle)
t
RASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
35
40
ns
11
W to RAS precharge time(C-B-R refresh)
t
WRP
15
15
ns
11
W to RAS hold time(C-B-R refresh)
t
WRH
8
8
ns
11
OE access time
t
OEA
18
20
ns
11
OE to data delay
t
OED
18
20
ns
11
Output buffer turn off delay time from OE
t
OEZ
5
18
5
20
ns
11
OE command hold time
t
OEH
13
15
ns
PDE to Valid PD bit
t
PD
10
10
ns
PDE to PD bit Inactive
t
PDOFF
2
7
2
7
ns
Present Detect Read Cycle
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are V
ih
/V
il
. V
IH
(min) and V
IL
(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between V
IH
(min) and V
IL
(max) and
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
Assumes tha
t
RCD
t
RCD
(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are not restrictive operat-
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If
t
WCS
t
WCS
(min) the cycle is an
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If
t
RWD
t
RWD
(min),
t
CWD
t
CWD
(min),
t
AWD
t
AWD
(min) and
t
CPWD
t
CPWD
(min).
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
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