REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

PIN NAMES

* These pins are not used in this module.

These pins should be NC in the system

which does not support SPD.

Pin Name

Function

A0 ~ A11

Address input (Multiplexed)

BA0~BA1

Select bank

DQ0 ~ DQ63

Data input/output

CB0 ~ CB7

Check bit (Data-in/data-out)

CLK0

Clock input

CKE0

Clock enable input

CS0, CS2

Chip select input

RAS

Row address storbe

CAS

Colume address strobe

Write enable

DQM0 ~ 7

DQM

Power supply (3.3V)

Ground

REF

Power supply for reference

REGE

SDA

Serial data I/O

SCL

Serial clock

SA0 ~ 2

Address in EEPROM

Don

t use

No connection

Write protection

PIN CONFIGURATIONS (Front side/back side)

Pin

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Front

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7
DQ8

DQ9

DQ10
DQ11
DQ12
DQ13

DQ14
DQ15

CB0
CB1

NC
NC

DQM0

Pin

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

Front

DQM1

CS0

A0
A2
A4
A6
A8

A10/AP

BA1

CLK0

CS2

DQM2
DQM3

NC
NC

CB2
CB3

DQ16
DQ17

Pin

57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

Front

DQ18
DQ19

DQ20

REF

*CKE1

DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27

DQ28
DQ29
DQ30
DQ31

*CLK2

NC/WP

**SDA

**SCL

Pin

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112

Back

DQ32
DQ33
DQ34
DQ35

DQ36
DQ37
DQ38
DQ39
DQ40

DQ41
DQ42
DQ43
DQ44
DQ45

DQ46
DQ47

CB4
CB5

NC
NC

CAS

DQM4

Pin

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140

Back

DQM5

*CS1

RAS

A1
A3
A5
A7
A9

BA0

A11
V

*CLK1

*A12

CKE0

*CS3

DQM6
DQM7

*A13

NC
NC

CB6
CB7

DQ48
DQ49

Pin

141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

Back

DQ50
DQ51

DQ52

REF

REGE

DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59

DQ60
DQ61
DQ62
DQ63

*CLK3

**SA0
**SA1
**SA2

The Samsung KMM375S823CT is a 8M bit x 72 Synchronous

Dynamic RAM high density memory module. The Samsung

KMM375S823CT consists of nine CMOS 8Mx8 bit Synchro-

nous DRAMs in TSOP-II 400mil packages, two 18-bits Drive

ICs for input control signal, one PLL in 24-pin TSSOP package

for clock and one 2K EEPROM in 8-pin TSSOP package for

Serial Presence Detect on a 168-pin glass-epoxy substrate.

Two 0.1uF decoupling capacitors are mounted on the printed

circuit board in parallel for each SDRAM. The

KMM375S823CT is a Dual In-line Memory Module and is

intented for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable laten-

cies allows the same device to be useful for a variety of high

bandwidth, high performance memory system applications.

GENERAL DESCRIPTION

KMM375S823CT SDRAM DIMM

8Mx72 SDRAM DIMM with PLL & Register based on 8Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD

� Performance range

� Burst mode operation
� Auto & self refresh capability (4096 Cycles/64ms)
� LVTTL compatible inputs and outputs
� Single 3.3V

�

0.3V power supply

� MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
� All inputs are sampled at the positive going edge of the
system clock
� Serial presence detect with EEPROM
� PCB : Height(1,500mil), double sided component

Part No.

Max Freq. (Speed)

KMM375S823CT-G8

125MHz (8ns @ CL=3)

KMM375S823CT-GH

100MHz (10ns @ CL=2)

KMM375S823CT-GL

100MHz (10ns @ CL=3)

KMM375S823CT-G0

100MHz (10ns @ CL=3)

FEATURE

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

PIN CONFIGURATION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

Chip select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.

A0 ~ A11

Address

Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8

BA0 ~ BA1

Bank select address

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Write enable

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

DQM0 ~ 7

Data input/output mask

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

REGE

Register enable

The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to V

through 10K ohm

Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.

DQ0 ~ 63

Data input/output

Data inputs/outputs are multiplexed on the same pins.

CB0 ~ 7

Check bit

Check bits for ECC.

Power supply/ground

Power and ground for the input buffers and the core logic.

REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

A0~A9

RAS,CAS,WE

DQM0,1,4,5

CS0

REGE

PCLK2

A0~B

BRAS,BCAS,BWE
BDQM0,1,4,5
BCS0

SN74ALVC162836

A10,A11,BA0~1

CS2

CKE0

DQM2,3,6,7

A10,B

A11,BBA0~1

BCS2
BCKE0
BDQM2,3,6,7

Vcc

10k

SN74ALVC162836

10pF

FUNCTIONAL BLOCK DIAGRAM

CLK
CS
CKE
Add,CTL
DQM
DQ0~7

PCLK0

BCS0

BCKE0

A0~B

A11,BBA0~1,BRAS,BCAS,BWE

BDQM0

DQ0~7

CLK
CS
CKE
Add,CTL
DQM
DQ0~7

DQ8~15

CLK
CS
CKE
Add,CTL
DQM
DQ0~7

PCLK1

BDQM1

CB0~7

CLK
CS
CKE
Add,CTL
DQM
DQ0~7

BDQM7

DQ56~63

CLK
CS
CKE
Add,CTL
DQM
DQ0~7

BCS2

BDQM2

DQ16~23

PCLK3

BDQM3

DQ24~31

BDQM4

DQ32~39

BDQM5

DQ40~47

BDQM6

DQ48~55

�

Serial PD

SDA

SCL

SA1 SA2

SA0

CDC2509A

1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3

CLK
FIBIN

Vcc

CLK0

FBOUT

PCLK0
PCLK1
PCLK2
PCLK3

47K

10pF

REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

*1. Register Input

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLK

RAS

CAS

RAS

CAS

CAS latency(refer to *1)

tSAC

tRDL

Read

Row Active

Command

Precharge
Command

Row Active

Write

Command

Precharge
Command

1CLK

td, tr = Delay of register (SN74ALVC162836)

Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (SN74ALVC162836). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. D

is to be issued 1clock after write command in external timing because D

is issued directly to module.

: Don

care

STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)

*2. Register Output

*3. SDRAM

REG

Control Signal(RAS,CAS,WE)

OUT

=2CLK+1CLK

tRAC(refer to *1)

tRAC(refer to *2)

CAS latency(refer to *2)

Qa0

Qa1

Qa2

Qa3

Db0

Db1

Db2

Db3

=2CLK

REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to Vss

, V

DDQ

-1.0 ~ 4.6

Storage temperature

STG

-55 ~ +150

�

Power dissipation

Short circuit current

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70

�

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

3.0

3.3

3.6

Input high voltage

2.0

3.0

DDQ

+0.3

Input low voltage

-0.3

0.8

Output high voltage

2.4

= -2mA

Output low voltage

0.4

= 2mA

Input leakage current (Inputs)

-2

Input leakage current (I/O Pins)

-1.5

1.5

3,4

1. V

(max) = 5.6V AC. The overshoot voltage duration is

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V

DDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V

OUT

DDQ.

Notes :

CAPACITANCE

= 3.3V, T

= 23

�

C, f = 1MHz, V

REF

=1.4V

�

200

mV)

Parameter

Symbol

Min

Max

Unit

Input capacitance (A

~ A

)

Input capacitance (RAS, CAS, WE)

Input capacitance (CKE0)

Input capacitance (CLK0)

Input capacitance (CS0, CS2)

Input capacitance (DQM0 ~ DQM7)

Input capacitance (BA0 ~ BA1)

Data input/output capacitance (DQ0 ~ DQ63)

Data input/output capacitance (CB0 ~ CB7)

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT

OUT1

REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T

= 0 to 70

�

Parameter

Symbol

Test Condition

CAS

Latency

Version

Unit

Note

-8

-H

-L

-0

Operating Current
(One bank active)

CC1

Burst length = 1
t

(min)

= 0 mA

825

780

735

Precharge standby current in
power-down mode

CC2

CKE

(max), t

= 15ns

CC2

PS CKE & CLK

(max), t

Precharge standby current in
non power-down mode

CC2

CKE

(min), CS

(min), t

= 15ns

Input signals are changed one time during 30ns

110

CC2

CKE

(min), CLK

(max), t

Input signals are stable

Active standby current in
power-down mode

CC3

CKE

(max), t

= 15ns

CC3

PS CKE & CLK

(max), t

Active standby current in
non power-down mode
(One bank active)

CC3

CKE

(min), CS

(min), t

= 15ns

Input signals are changed one time during 30ns

180

CC3

CKE

(min), CLK

(max), t

Input signals are stable

Operating current
(Burst mode)

CC4

= 0 mA

Page burst
t

CCD

= 2CLKs

1,055

875

830

Refresh current

CC5

(min)

1,127

990

Self refresh current

CC6

CKE

0.2V

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Measured with 1 PLL & 2 Drive ICs.

Notes :

REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

3.3V

1200

870

Output

50pF

(DC) = 2.4V, I

= -2mA

(DC) = 0.4V, I

= 2mA

Vtt = 1.4V

Output

50pF

Z0 = 50

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit

AC OPERATING TEST CONDITIONS

= 3.3V

�

0.3V, T

= 0 to 70

�

Parameter

Value

Unit

AC input levels (Vih/Vil)

2.4/0.4

Input timing measurement reference level

1.4

Input rise and fall time

tr/tf = 1/1

Output timing measurement reference level

1.4

Output load condition

See Fig. 2

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

-8

-H

-L

-0

Row active to row active delay

RRD

(min)

RAS to CAS delay

RCD

(min)

Row precharge time

(min)

Row active time

RAS

(min)

RAS

(max)

100

Row cycle time

(min)

Last data in to row precharge

RDL

(min)

Last data in to new col. address delay

CDL

(min)

CLK

Last data in to burst stop

BDL

(min)

CLK

Col. address to col. address delay

CCD

(min)

CLK

Number of valid output data

CAS latency=3

CAS latency=2

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

Notes :

REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

Parameter

Symbol

-8

-H

-L

-0

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS latency=3

1000

CAS latency=2

CLK to valid
output delay

CAS latency=3

SAC

1,2

CAS latency=2

Output data
hold time

CAS latency=3

1,2

CAS latency=2

CLK high pulse width

3.5

CLK low pulse width

3.5

Input setup time

2.5

Input hold time

CLK to output in Low-Z

SLZ

CLK to output
in Hi-Z

CAS latency=3

SHZ

CAS latency=2

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :

REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE

KMM375S823CT-8

Frequency

CAS

Latency

RAS

RRD

RCD

CCD

CDL

RDL

68ns

48ns

20ns

16ns

20ns

8ns

125MHz (8.0ns)

100MHz (10.0ns)

83MHz (12.0ns)

75MHz (13.0ns)

66MHz (15.0ns)

(Unit : Number of clock)

KMM375S823CT-L

Frequency

CAS

Latency

RAS

RRD

RCD

CCD

CDL

RDL

70ns

50ns

20ns

10ns

100MHz (10.0ns)

83MHz (12.0ns)

75MHz (13.0ns)

66MHz (15.0ns)

60MHz (16.7ns)

(Unit : Number of clock)

KMM375S823CT-H

Frequency

CAS

Latency

RAS

RRD

RCD

CCD

CDL

RDL

70ns

50ns

20ns

10ns

100MHz (10.0ns)

83MHz (12.0ns)

75MHz (13.0ns)

66MHz (15.0ns)

60MHz (16.7ns)

(Unit : Number of clock)

KMM375S823CT-0

Frequency

CAS

Latency

RAS

RRD

RCD

CCD

CDL

RDL

80ns

50ns

24ns

20ns

24ns

10ns

12ns

100MHz (10.0ns)

83MHz (12.0ns)

75MHz (13.0ns)

66MHz (15.0ns)

60MHz (16.7ns)

(Unit : Number of clock)

REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

Notes :

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

t care, H=Logic high, L=Logic low)

Command

CKEn-1

CKEn

RAS

CAS

DQM

0,1

/AP

11,

~ A

Note

Mode register set

OP code

1,2

Refresh

Auto refresh

Self
refresh

Entry

Exit

Bank active & row addr.

Row address

Read &
column address

Auto precharge disable

Column

address

~ A

)

Auto precharge enable

4,5

Write &
column address

Auto precharge disable

Column

address

~ A

)

Auto precharge enable

4,5

Burst stop

Precharge

Bank selection

All banks

Clock suspend or
active power down

Entry

Exit

Precharge power down mode

Entry

Exit

DQM

No operation command

1. OP Code : Operand code
A

~ A

& BA

~ BA

: Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA

~ BA

: Bank select addresses.

If both BA

and BA

are "Low" at read, write, row active and precharge, bank A is selected.

If both BA

is "Low" and BA

is "High" at read, write, row active and precharge, bank B is selected.

If both BA

is "High" and BA

is "Low" at read, write, row active and precharge, bank C is selected.

If both BA

and BA

are "High" at read, write, row active and precharge, bank D is selected.

If A

/AP is "High" at row precharge, BA

and BA

is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t

after the end of burst.

6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

REV. 2 Jan 1999

Preliminary
KMM375S823CT

SDRAM MODULE

PACKAGE DIMENSIONS

5.250

5.014

Units : Inches (Millimeters)

0.050

0.039

�

.002

0.010Max

(0.250 Max)

0.150Max

0.050

�

0.0039

(1.270

�

0.10)

R 0.079

(R 2.000)

0.250

(6.350)

1.450

(36.830)

2.150

(54.61)

.
1

(
3

.
0

)

0.350

.
1

i
n

(
2

.
5

i
n

)

.
7

(
1

.
7

)

(1.000

�

.050)

(1.270)

.
1

i
n

(
2

.
5

i
n

)

Detail C

.118DIA

�

.004

(3.000DIA

�

.100)

(8.890)

0.250

(6.350)

.450
(11.430)

4.550

(115.57)

0.157

�

0.004

(4.000

�

0.100)

0.054

(1.372)

(127.350)

(133.350)

.
5

(
3

.
1

)

0.118

(3.000)

0.250

(6.350)

Detail A

0.123

�

.005

(3.125

�

.125)

0.250

(6.350)

Detail B

0.123

�

.005

(3.125

�

.125)

0.079

�

.004

(2.000

�

.100)

0.079

�

.004

(2.000

�

.100)

.
1

i
n

(
4

.
1

i
n

)

(3.81Max)

Tolerances :

�

.005(.13) unless otherwise specified

The used device is 8Mx8 SDRAM, TSOP
SDRAM Part No. : KM48S8030BT

REG

PLL

REG

Электронный компонент: KMM375S823CT-L