KS57C2504
4-BIT CMOS Microcontroller
Product Specification
41
OVERVIEW
The S3C7254 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM4 (Samsung Arrangeable Microcontrollers).With a two-channel comparator, up-to-
320-dot LCD direct drive capability, 8-bit timer/counter, and serial I/O, the S3C7254 offers an excellent design
solution for a wide variety of applications which require LCD functions.
Up to 27 pins of the 80-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast response
to internal and external events. In addition, the S3C7254's advanced CMOS technology provides for low power
consumption and a wide operating voltage range.
FEATURES
Memory
512
4-bit RAM
4096
8-bit ROM
27 I/O Pins
I/O: 15 pins
Input only: 4 pins
Output only: 8 pins
Comparator
Two-channel mode: internal
reference (4-bit resolution)
One-channel mode: external
reference
LCD Controller/Driver
40 segments and 8 common
terminals
3, 4 and 8 common
selectable
Internal resistor circuit for
LCD bias
All dot can be switched
on/off
8-Bit Basic Timer
4 interval timer functions
8-Bit Timer/Counter
Programmable 8-bit timer
External event counter
Arbitrary clock frequency
output
External clock signal divider
Serial I/O interface clock
generator
Watch Timer
Time interval generation:
0.5 s, 3.9 ms at 32768 Hz
Four frequency outputs to
BUZ pin
Clock source generation for
LCD
8-Bit Serial I/O Interface
8-bit transmit/receive mode
8-bit receive only mode
LSB-first or MSB-first
transmission selectable
Internal or external clock
source
Interrupts
Three internal vectored
interrupts
Four external vectored
interrupts
Two quasi-interrupts
Bit Sequential Carrier
Supports 16-bit serial data
transfer in arbitrary format
Memory-Mapped I/O Structure
Data memory bank 15
Two Power-Down Modes
Idle mode (only CPU clock
stops)
Stop mode (main system
oscillation stops)
Oscillation Sources
Crystal, ceramic, or RC for
main system clock
Crystal oscillator for
subsystem clock
Main system clock
frequency: 4.19 MHz
(typical)
Subsystem clock frequency:
32.768 kHz
CPU clock divider circuit (by
4, 8, or 64)
PRODUCT SPECIFICATION
S3C7254
42
Instruction Execution Times
0.95, 1.91, 15.3 s at 4.19
MHz
122 s at 32.768 kHz
Operating Temperature
40
C to 85
C
Operating Voltage Range
2.7 V to 6.0 V
Package Type
80-pin QFP
ARITHMETIC
LOGIC UNIT
INTERRUPT
CONTROL
BLOCK
STACK
POINTER
PROGRAM
COUNTER
PROGRAM
STATUS WORD
LCD
DRIVER/
CONTROLLER
VLC1VLC5
COM0COM7
SEG0SEG31
P5.0/SEG32
P5.7/SEG39
512 x 4-BIT
DATA
MEMORY
4-KB
PROGRAM
MEMORY
BASIC
TIMER
FLAGS
INSTRUCTION DECODER
CLOCK
RESET
XIN
XTIN
XOUT
XTOUT
INTERNAL
INTERRUPTS
I/O PORT 4
P4.0/CLO
P4.1/TCL0
P4.2/TCLO0
P1.0 / INT0 / CIN0
P1.1 / INT1 / CIN1
P1.2 / INT2
P1.3 / INT4
WATCH
TIMER
8-BIT
TIMER/
COUNTER
SIO
INPUT
PORT 1
P0.0 /
SCK
/ K0
P0.1 / SO / K1
P0.2 / SI / K2
P0.3 / BUZ / K3
I/O PORT 0
COMPARA-
TOR
I/O PORT 2
I/O PORT 3
P2.0P2.3
P3.0
P3.1
P3.2 / LCDSY
P3.3 / LCDCK
Figure 1. S3C7254 Simplified Block Diagram
S3C7254
PRODUCT SPECIFICATION
43
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
XT
OUT
XT
IN
X
IN
X
OUT
V
DD
TEST
RESET
P4.2 / TCLO0
P4.1 / TCL0
P4.0 / CLO
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
KS57C2504
(TOP VIEW)
SEG30
SEG31
P5.0 / SEG32
P5.1 / SEG33
P5.2 / SEG34
P5.3 / SEG35
P5.4 / SEG36
P5.5 / SEG37
P5.6 / SEG38
P5.7 / SEG39
VSS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
P0.0 /
SCK
/ K0
P0.1 / SO / K1
P0.2 / SI / K2
P0.3 / BUZ / K3
P1.0 / INT0 / CIN0
P1.1 / INT1 / CIN1
P1.2 / INT2
P1.3 / INT4
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
LCDSY / P3.2
LCDCK / P3.3
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
Figure 2. S3C7254 80Pin QFP Assignment Diagram
S3C7254
(TOP VIEW)
PRODUCT SPECIFICATION
S3C7254
44
Table 1. S3C7254 Pin Descriptions
Pin Name
Pin Type
Description
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
25
26
27
28
K0/
SCK
K1/SO
K2/SI
K3/BUZ
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit or 4-bit read and test are possible.
The 1-bit unit pull-up resistors are assigned to input
pins by software.
An interrupt is generated by digital input at P1.0,
P1.1.
29
30
31
32
INT0/CIN0
INT1/CIN1
INT2
INT4
P2.0P2.3
I/O
Same as port 0 except that 8-bit read/write and test is
possible.
3336
P3.0
P3.1
P3.2
P3.3
37
38
39
40
LCDSY
LCDCK
P4.0
P4.1
P4.2
I/O
Same as port 0 except that port 4 is 3-bit I/O port.
41
42
43
CLO
TCL0
TCLO0
P5.0P5.7
O
Output port for 1-bit data
310
SEG32
SEG39
SCK
I/O
Serial I/O interface clock signal
25
P0.0/K0
SO
I/O
Serial data output
26
P0.1/K1
SI
I/O
Serial data input
27
P0.2/K2
BUZ
I/O
2 KHz, 4 KHz, 8 KHz or 16 KHz frequency output for
buzzer sound
28
P0.3/K3
K0K3
I/O
External interrupt. The triggering edge is selectable.
2528
P0.0P0.3
INT0
INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
29
30
P1.0/CIN0
P1.1/CIN1
INT2
I
Quasi-interrupt with detection of rising or falling
edges
31
P1.2
INT4
I
External interrupts with detection of rising and falling
edges
32
P1.3
S3C7254
PRODUCT SPECIFICATION
45
Table 1. S3C7254 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Number
Share Pin
CIN0
CIN1
I
2-channel comparator input.
CIN0: comparator input or external reference input
CIN1: comparator input only.
29
30
P1.0/INT0
P1.1/INT1
LCDSY
I/O
LCD synchronization clock output for display expan-
sion
39
P3.2
LCDCK
I/O
LCD clock output for display expansion
40
P3.3
CLO
I/O
Clock output
41
P4.0
TCL0
I/O
External clock input for timer/counter 0
42
P4.1
TCLO0
I/O
Timer/counter 0 clock output
43
P4.2
SEG32SEG39
O
LCD segment signal output
310
P5.0P5.7
SEG0SEG29
SEG30SEG31
O
LCD segment signal output
5180
12
COM0COM7
O
LCD common signal output
1219
V
LC1
V
LC5
LCD power supply. Voltage dividing resistors are
assignable by mask option.
2024
X
IN,
X
OUT
Crystal, ceramic or RC oscillator pins for system
clock.
48, 47
XT
IN,
XT
OUT
Crystal oscillator pins for subsystem clock.
49, 50
V
DD
Main power supply
46
V
SS
Ground
11
RESET
I
Chip reset signal input
44
TEST
I
Chip test signal input (must be connected to V
SS
)
45
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
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