KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW

1-1

PRODUCT OVERVIEW

OVERVIEW

The KS57C5204/C5208/C5304/C5308/C5312 single-chip CMOS microcontroller has been designed for high-
performance using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core
is notable for its low energy consumption and low operating voltage.

You can select from three ROM sizes: 4K, 8K, or 12K bytes.
Except for the difference in ROM size, the features and functions of the KS57C5204 and the KS57C5208 are
identical and the KS57C5304, KS57C5308, and the KS57C5312 are identical.

With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, the KS57C5204/C5208
/C5304/C5308/C5312 offers an excellent design solution for a wide variety of telecommunication applications.

Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the KS57C5204/C5208, and up to 23 pins
of the available 30-pin SDIP or 32-pin SOP package for the KS57C5304/C5308/C5312 can be assign to I/O. Six
vectored interrupts for KS57C5204/C5208 and four vectored interrupts for KS57C5304/C5308/C5312 provide fast
response to internal and external events. In addition, the KS57C5204/C5208/C5304/C5308/C5312's advanced
CMOS technology provides for low power consumption and a wide operating voltage range.

OTP

The KS57C5204/C5208 microcontroller is also available in OTP (One Time Programmable) version, KS57P5208.
The KS57C5304/C5308/C5312 microcontroller is also available in OTP (One Time Programmable) version,
KS57P5308/P5312. The KS57P5208/P5308/P5312 microcontroller has an on-chip 8K-byte (P5208/P5308) or
12K-byte (P5312) one-time-programable EPROM instead of masked ROM. The KS57P5208 is comparable to
KS57C5204/C5208, both in function and in pin configuration. Also, the KS57P5308/P5312 is comparable to the
KS57C5304/C5308/C5312, both in function and in pin configuration.

PRODUCT OVERVIEW

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

1-2

FEATURES

Memory

768

4-bit RAM

4,096

8-bit ROM (KS57C5204/C5304)

8,192

8-bit ROM (KS57C5208/C5308)

12,288

8-bit ROM (KS57C5312)

I/O Pins

Input only: 4 pins (KS57C5204/C5208)
1 pins (KS57C5304/C5308/C5312)

I/O: 35 pins (KS57C5204/C5208)

23 pins (KS57C5304/C5308/C5312)

N-channel open-drain I/O: 8 pins

Memory-Mapped I/O Structure

Data memory bank 15

DTMF Generator

16 dual-tone frequencies for tone dialing

8-Bit Basic Timer

Programmable interval timer

Watchdog timer

Two 8-Bit Timer/Counters

Programmable 8-bit timer

External event counter function

Arbitrary clock frequency output

Watch Timer

Real-time and time interval generation

Four frequency outputs to the BUZ pin

Bit Sequential Carrier

Supports 16-bit serial data transfer in arbitrary

format

Interrupts

3 external interrupt vectors (KS57C5204/C5208)

1 external interrupt vectors
(KS57C5304/C5308/C5312)

3 internal interrupt vectors

2 quasi-interrupts

Power-Down Modes

Idle: Only CPU clock stops

Stop: System clock stops

Oscillation Sources

Crystal, or ceramic for main system clock

Main system clock frequency: 0.46.0 MHz

(typical)

CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

0.95, 1.91, and 15.3

s at 4.19 MHz

1.12, 2.23, 17.88

s at 3.58 MHz

0.67, 1.33, 10.7

s at 6.0 MHz

Operating Temperature

C to 85

Operating Voltage Range

1.8 V to 5.5 V

Package Types

42 SDIP, 44 QFP (KS57C5204/C5208)

30 SDIP, 32 SOP (KS57C5304/C5308/C5312)

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW

1-3

BLOCK DIAGRAM

Program

Status Word

Flags

Arithmetic

and

Logic Unit

Instruction Decoder

Internal

Interrupts

RESET

Interrupt

Control

Block

Stack

Pointer

Clock

Program Memory

KS57C5204/C5304: 4KBytes
KS57C5208/C5308: 8KBytes
KS57C5312: 12KBytes

768x4-Bit

Data

Memory

Input

Port 1

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4

P9.0 - P9.2

OUT

Program

Counter

8-Bit

Timer/

Counter 0

Watchdog

Timer

NOTE:

KS57C5304/C5308/C5312 does not use P1.1/INT1, P1.2/INT2, P1.3/INT4, P3.2, P3.3, INT1, INT2,
INT4, P8.0-P8.3, and P9.0-P9.2.

8-Bit

Timer/

Counter 1

I/O Port 3

I/O Port 2

I/O Port 7

I/O Port 6

I/O Port 9

I/O Port 8

Basic

Timer

Watch

Timer

I/O Port 5

I/O Port 4

DTMF

Generator

P2.0/TCLO0
P2.1/TCLO1
P2.2/CLO
P2.3/BUZ

P3.0/TCL0
P3.1/TCL1
P3.2
P3.3

P4.0/BTCO
P4.1-4.3

P5.0-P5.3

DTMF

P6.0-P6.3/

KS0-KS3

P7.0-P7.3/

KS4-KS7

P8.0 - P8.3

INT0, INT1, INT2, INT4

Figure 1-1. KS57C5204/C5208/C5304/C5308/C5312 Simplified Block Diagram

PRODUCT OVERVIEW

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

1-4

PIN ASSIGNMENTS

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4

P2.0/TCLO0
P2.1/TCLO1

P2.2/CLO

P2.3/BUZ

P3.0/TCL0
P3.1/TCL1

OUT

TEST

P4.0/BTCO

P4.1

RESET

P3.2
P3.3
P4.2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

P9.2
P9.1
P9.0
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

KS57C5204/C5208

(42-SDIP-600)

Figure 1-2. KS57C5204/C5208 Pin Assignment Diagram (42-SDIP)

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW

1-5

DTMF

P9.0
P9.1
P9.2

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4

P2.0/TCLO0
P2.1/TCLO1

KS57C5204

/C5208

(44-QFP-1010B)

P7.3/KS7

P7.2/KS6

P7.1/KS5

P7.0/KS4

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P5.3

P5.2

P5.1

P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
NC
P4.2
P3.3
P3.2

RESET

34
35
36
37
38
39
40
41
42
43
44

P2.2/CLO

P2.3/BUZ

P3.0/TCL0

P3.1/TCL1

OUT

TEST

P4.0/BTCO

P4.1

22
21
20
19
18
17
16
15
14
13
12

Figure 1-3. KS57C5204/C5208 Pin Assignment Diagram (44-QFP)

PRODUCT OVERVIEW

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

1-6

OUT

TEST

P4.0/BTCO

P4.1

RESET

P4.2
P4.3
P5.0
P5.1
P5.2
P5.3

P6.0/KS0
P6.1/KS1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

P3.1/TCL1
P3.0/TCL0
P2.3/BUZ
P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0
P1.0/INT0
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

KS57C5304/C5308/C5312

(30-SDIP-400)

Figure 1-4. KS57C5304/C5308/C5312 Pin Assignment Diagram (30-SDIP)

OUT

TEST

P4.0/BTCO

P4.1

RESET

P4.2

P4.3
P5.0
P5.1
P5.2
P5.3

P6.0/KS0
P6.1/KS1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

P3.1/TCL1
P3.0/TCL0
P2.3/BUZ
P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0
P1.0/INT0
NC
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

KS57C5304/C5308/C5312

(32-SOP-450A)

Figure 1-5. KS57C5304/C5308/C5312 Pin Assignment Diagram (32-SOP)

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW

1-7

PIN DESCRIPTIONS

Table 1-1. KS57C5204/C5208 Pin Descriptions

Pin

Name

Pin

Type

Reset
Value

Description

Pin

Number

Share

Pin

Circuit

Type

P1.0
P1.1
P1.2
P1.3

4-bit input port.
1-bit and 4-bit read and test is possible.
Each pull-up resistors are assignable by software.

1 (39)
2 (40)
3 (41)
4 (42)

INT0
INT1
INT2
INT4

A-4

P2.0
P2.1
P2.2
P2.3

I/O

4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.

5 (43)
6 (44)

7 (1)
8 (2)

TCLO0
TCLO1

CLO
BUZ

D-2

P3.0
P3.1
P3.2
P3.3

4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 2 and 3 can be paired to enable 8-bit data
transfer.

9 (3)

10 (4)

19 (13)
20 (14)

TCL0

TCL1

D-4

P4.0
P4.1
P4.2
P4.3

P5.0-P5.3

I/O

4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
N-channel open-drain or push-pull output can be
selected by software (1-bit unit)
Ports 4 and 5 can be paired to support 8-bit data
transfer.

16 (10)
17 (11)
21 (15)
22 (17)

27-30

(22-25)

BTCO

E-2

P6.0-P6.3

P7.0-P7.3

I/O

4-bit I/O ports.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 6 and 7 can be paired to enable 8-bit data
transfer.

31-34

(26-29)

35-38

(30-33)

KS0-KS3

KS4-KS7

D-4

P8.0-P8.3

P9.0-P9.2

I/O

4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 8 and 9 can be paired to enable 8-bit data
transfer.

23-26

(18-21)

40-42

(35-37)

D-2

PRODUCT OVERVIEW

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

1-8

Table 1-1. KS57C5204/C5208 Pin Descriptions (Continued)

Pin Name

Pin

Type

Reset
Value

Description

Pin

Number

Share

Pin

Circu

Type

DTMF

DTMF output.

39 (34)

G-6

BTCO

I/O

Basic timer clock output

16 (10)

P4.0

E-2

INT0
INT1

External interrupts. The triggering edge for INT0 and
INT1 is selectable.

1 (39)
2 (40)

P1.0
P1.1

A-4

INT2

Quasi-interrupt with detection of rising edges

3 (41)

P1.2

A-4

INT4

External interrupt with detection of rising and falling
edges.

4 (42)

P1.3

A-4

TCLO0

I/O

Timer/counter 0 clock output

5 (43)

P2.0

D-2

TCLO1

I/O

Timer/counter 1 clock output

6 (44)

P2.1

D-2

CLO

I/O

Clock output

7 (1)

P2.2

D-2

BUZ

I/O

2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the
watch timer clock frequency of 4.19 MHz for buzzer
sound

8 (2)

P2.3

D-2

TCL0

I/O

External clock input for timer/counter 0

9 (3)

P3.0

D-4

TCL1

I/O

External clock input for timer/counter 1

10 (4)

P3.1

D-4

KS0-KS3

KS4-KS7

I/O

Quasi-interrupt inputs with falling edge detection

31-34

(26-29)

35-38

(30-33)

P6.0-P6.3
P7.0-P7.3

D-4

Power supply

11 (5)

Ground

12 (6)

RESET

signal

18 (12)

OUT

Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use X

and input X

reverse phase to X

OUT

)

14 (8)
13 (7)

TEST

Chip test input pin, Hold GND when the device is
operating.

15 (9)

No connection

(16, 38)

NOTE: Parentheses indicate pin number for 44 QFP package.

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW

1-9

Table 1-2. KS57C5304/C5308/C5312 Pin Descriptions

Pin

Name

Pin

Type

Description

Pin

Number

Share

Pin

Circuit

Type

P1.0

1-bit input port.
1-bit and 4-bit read and test is possible.
Each bit pull-up resistors are assignable.

23 (25)

INT0

A-4

P2.0
P2.1
P2.2
P2.3

I/O

4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software assignable to
input pins and are automatically disabled for output
pins.

24 (26)
25 (27)
26 (28)
27 (29)

TCLO0
TCLO1

CLO
BUZ

D-2

P3.0
P3.1

Ports 2 and 3 can be paired to enable 8-bit data
transfer.

28 (30)
29 (31)

TCL0

TCL1

D-4

P4.0
P4.1
P4.2
P4.3
P5.0-P5.3

I/O

4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software assignable to
input pins and are automatically disabled for output
pins.
The N-channel open-drain or push-pull output can be
selected by software (1-bit unit).
Ports 4 and 5 can be paired to enable 8-bit data
transfer.

5 (5)
6 (6)
8 (8)

9 (10)
10-13

(11-14)

BTCO

E-2

P6.0-P6.3

P7.0-P7.3

I/O

4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software assignable to
input pins and are automatically disabled for output
pins.
Ports 6 and 7 can be paired to enable 8-bit data
transfer.

14-17

(15-18)

18-21

(19-22)

KS0-KS3

KS4-KS7

D-4

PRODUCT OVERVIEW

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

1-10

Table 1-2. KS57C5304/C5308/C5312 Pin Descriptions (Continued)

Pin Name

I/O

Type

Description

Pin

Number

Share

Pin

Circuit

Type

DTMF

DTMF output.

22 (23)

G-6

INT0

External interrupt input.
The triggering edge for INT0 is selectable.

23 (25)

P1.0

A-3

TCLO0

I/O

Timer/counter 0 clock output

24 (26)

P2.0

D-2

TCLO1

I/O

Timer/counter 1 clock output

25 (27)

P2.1

D-2

CLO

I/O

Clock output

26 (28)

P2.2

D-2

BUZ

I/O

2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the
watch timer clock frequency of 4.19 MHz for buzzer
sound

27 (29)

P2.3

D-2

TCL0

I/O

External clock input for timer/counter 0

28 (30)

P3.0

D-4

TCL1

I/O

External clock input for timer/counter 1

29 (31)

P3.1

D-4

BTCO

I/O

Basic timer clock output

5 (5)

P4.0

E-2

Power supply

30 (32)

Ground

1 (1)

OUT

Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use X

and input X

reverse phase to X

OUT

)

3 (3)
2 (2)

No connection

(9, 24)

TEST

Chip test input pin, Hold GND when the device is
operating.

4 (4)

RESET

signal

7 (7)

KS0-KS3

KS4-KS7

I/O

Quasi-interrupt inputs with falling edge detection

14-17

(15-18)

18-21

(19-22)

P6.0-P6.3
P7.0-P7.3

D-4

NOTE: Parentheses indicate the pin number for 32-SOP package.

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW

1-11

PIN CIRCUIT DIAGRAMS

P-Channel

N-Channel

Figure 1-6. Pin Circuit Type A

Schmitt Trigger

Pull-Up
Resistor

Resistor
Enable

P-Channel

Figure 1-7. Pin Circuit Type A-4

Schmitt Trigger

Pull-Up
Resistor

Figure 1-8. Pin Circuit Type B

P-Channel

N-Channel

Out

Output

DIsable

Data

Figure 1-9. Pin Circuit Type C

PRODUCT OVERVIEW

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

1-12

P-Channel

I/O

Output

DIsable

Data

Circuit

Type C

Pull-up
Enable

Pull-up
Resistor

Figure 1-10. Pin Circuit Type D-2

P-Channel

I/O

Output

Disable

Data

Circuit

Type C

Pull-up
Enable

Schmitt Trigger

Pull-up
Resistor

Figure 1-11. Pin Circuit Type D-4

PNE

Output

Disable

Data

Pull-up
Resistor
Enable

I/O

Pull-up
Resistor

P-Channel

N-Channel

Figure 1-12. Pin Circuit Type E-2

DTMF Out

Output

Disable

Figure 1-13. Pin Circuit Type G-6

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

ELECTRICAL DATA

13-1

ELECTRICAL DATA

OVERVIEW

In this section, information on KS57C5204/C5208/C5304/C5308/C5312 electrical characteristics is presented as
tables and graphics. The information is arranged in the following order:

Standard Electrical Characteristics

-- Absolute maximum ratings

-- D.C. electrical characteristics

-- System clock oscillator characteristics

-- I/O capacitance

-- A.C. electrical characteristics

-- Operating voltage range

Miscellaneous Timing Waveforms

-- A.C timing measurement point

-- Clock timing measurement at X

and X

OUT

-- TCL timing

-- Input timing for

RESET

-- Input timing for external interrupts

Stop Mode Characteristics and Timing Waveforms

-- RAM data retention supply voltage in stop mode

-- Stop mode release timing when initiated by

RESET

-- Stop mode release timing when initiated by an interrupt request

ELECTRICAL DATA

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

13-2

Table 13-1. Absolute Maximum Ratings

= 25

Parameter

Symbol

Conditions

Rating

Units

Supply Voltage

0.3 to + 6.5

Input Voltage

All I/O ports

0.3 to V

+ 0.3

Output Voltage

0.3 to V

+ 0.3

Output Current High

One I/O port active

All I/O ports active

Output Current Low

One I/O port active

+ 30 (Peak value)

+ 15

(note)

All I/O ports active

+ 100 (Peak value)

+ 60

(note)

Operating Temperature

40 to + 85

Storage Temperature

stg

65 to + 150

NOTE: The values for output current low ( I

) are calculated as peak value

Duty .

Table 13-2. D.C. Electrical Characteristics

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Input high
voltage

IH1

All input pins except those specified
below for V

IH2

IH3

0.7 V

IH2

Ports 1, 3, 6, 7, and

RESET

0.8 V

IH3

and X

OUT

0.1

Input low
voltage

IL1

All input pins except those specified
below for V

IL2

IL3

0.3 V

IL2

Ports 1, 3, 6, 7, and

RESET

0.2 V

IL3

and X

OUT

0.1

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

ELECTRICAL DATA

13-3

Table 13-2. D.C. Electrical Characteristics (Continued)

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Output high
voltage

= 1 mA

Ports except 1

1.0

Output low
voltage

OL1

= 4.5 V to 5.5 V

= 15 mA, Ports 4 and 5 only

= 1.8 to 5.5 V, I

= 1.6mA

0.4

OL2

= 4.5 V to 5.5 V

= 4 mA, all out ports except 4,5

= 1.8 to 5.5 V, I

= 1.6mA

0.4

Input high
leakage current

LIH1

= V

All input pins except those specified
below

µA

LIH2

= V

and X

OUT

Input low
leakage current

LIL1

= 0

All input pins except below and

RESET

µA

LIL2

= 0 V

and X

OUT

only

Output high
leakage current

LOH

= V

All out pins

µA

Output low
leakage current

LOL

= 0 V

All out pins

µA

Pull-up resistor

= 5 V; V

= 0 V

except

RESET

100

= 3 V

200

= 5 V; V

= 0 V;

RESET

100

220

400

= 3 V

200

450

800

ELECTRICAL DATA

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

13-4

Table 13-2. D.C. Electrical Characteristics (Concluded)

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Supply

current

(1)

DD1

(DTMF on)

Run mode; V

= 5 V

10%

(2)

3.58 MHz crystal oscillator,
C1 = C2 = 22 pF

2.5

5.0

= 3 V ± 10%

1.4

3.0

DD2

Run mode; V

= 5 V

10%

6.0 MHz

2.5

8.0

(DTMF off)

crystal oscillator, C1 = C2 = 22 pF

3.58 MHz

1.6

4.0

= 3 V ± 10%

6.0 MHz

1.2

4.0

3.58 MHz

0.7

2.3

DD3

Idle mode; = V

= 5 V

10%

6.0 MHz

0.7

2.5

crystal oscillator, C1 = C2 = 22 pF

3.58 MHz

0.6

1.8

= 3 V ± 10%

6.0 MHz

0.3

1.5

3.58 MHz

0.2

1.0

DD4

Stop mode; V

= 5 V ± 10%

0.01

µA

Stop mode; V

= 3 V ± 10%

0.01

Row tone level

ROW

= 2.0 V to 5.5 V

RL = 12 k

, Temp = 30

C to 60

16.0 14.0 11.0

dBV

Ratio of
column to row
tone

= 2.0 V to 5.5 V

RL = 12 k

, Temp = 30

C to 60

Distortion
(Dual tone)

THD

= 2.0 V to 5.5 V

1MHz band; RL= 12 k

Temp = 30

C to 60

NOTES:
1.

D.C. electrical values for Supply Current (I

DD1

to I

DD3

) do not include current drawn through internal pull-up registers.

For D.C. electrical values, the power control register (PCON) must be set to 0011B.

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

ELECTRICAL DATA

13-5

Table 13-3. Main System Clock Oscillator Characteristics

= 40

C + 85

C, V

= 1.8 V to 5.5 V)

Oscillator

Clock

Configuration

Parameter

Test Condition

Min

Typ

Max

Units

Ceramic
Oscillator

OUT

Oscillation frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

Stabilization time

(2)

= 3 V

Crystal
Oscillator

OUT

Oscillation frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

Stabilization time

(2)

= 3 V

External
Clock

OUT

input frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

input high and low

level width (t

, t

)

83.3

1250

NOTES:
1.

Oscillation frequency and X

input frequency data are for oscillator characteristics only.

Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.

ELECTRICAL DATA

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

13-6

Table 13-4. Recommended Oscillator Constants

= 40

C to + 85

Manufacturer

Series

Number

(1)

Frequency Range

Load Cap (pF)

Oscillator Voltage

Range (V)

Remarks

MIN

MAX

TDK

FCR

3.58 MHz-6.0 MHz

2.0

5.5

Leaded Type

FCR

MC5

3.58 MHz-6.0 MHz

(2)

2.0

5.5

On-chip C
Leaded Type

CCR

MC3

3.58 MHz-6.0 MHz

(3)

2.0

5.5

On-chip C
SMD Type

NOTES:
1.

Please specify normal oscillator frequency.

On-chip C: 30pF built in.

On-chip C: 38pF built in.

Table 13-5. Input/Output Capacitance

= 25

C, V

0 V )

Parameter

Symbol

Condition

Min

Typ

Max

Units

Input
Capacitance

f = 1 MHz; Unmeasured pins
are returned to V

Output
Capacitance

OUT

I/O Capacitance

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

ELECTRICAL DATA

13-7

Table 13-6. A.C. Electrical Characteristics

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Instruction Cycle
Time

= 2.7 V to 5.5 V

0.67

µs

= 1.8 V to 5.5 V

1.33

TCL0, TCL1 Input
Frequency

TI0

TI1

= 2.7 V to 5.5 V

1.5

MHz

= 1.8 V to 5.5V

MHz

TCL0, TCL1 Input
High, Low Width

TIH0

TIL0

TIH1

TIL1

= 2.7 V to 5.5 V

0.48

µs

= 1.8 V to 5.5 V

1.8

Interrupt Input
High, Low Width

INTH

, t

INTL

INT0, INT1, INT2, INT4,
KS0-KS7

µs

RESET

Input Low

Width

RSL

Input

µs

ELECTRICAL DATA

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

13-8

1.5 MHz

CPU Clock

0.75 MHz

15.625 kHz

Main Oscillator Frequency
(Divided by 4)

3 MHz

6 MHz

Supply Voltage (V)

CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)

2.7

1.8

Figure 13-1. Standard Operating Voltage Range

Table 13-7. RAM Data Retention Supply Voltage in Stop Mode

= 40

C to + 85

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Data retention supply voltage

DDDR

1.8

5.5

Data retention supply current

DDDR

= 1.8 V

0.1

µA

Release signal set time

SREL

µs

Oscillator stabilization wait

WAIT

Released by

RESET

/fx

time

(1)

Released by interrupt

(2)

NOTES:
1.

During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.

Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

ELECTRICAL DATA

13-9

TIMING WAVEFORMS

Execution of

STOP Instruction

Internal RESET

Operation

~ ~

DDDR

~ ~

Stop Mode

Idle Mode

Operating Mode

Data Retention Mode

SREL

WAIT

RESET

Figure 13-2. Stop Mode Release Timing When Initiated by

RESET

Execution of

STOP Instruction

DDDR

~ ~

Data Retention

Normal
Operating
Mode

~ ~

Stop Mode

Idle Mode

SREL

WAIT

Power-down Mode Terminating Signal
(Interrupt Request)

Figure 13-3. Stop Mode Release Timing When Initiated by Interrupt Request

ELECTRICAL DATA

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

13-10

Timing Waveforms (continued)

0.8 V

0.2 V

0.8 V

0.2 V

Measurement

Points

Figure 13-4. A.C. Timing Measurement Points (Except for X

)

1/fx

- 0.1 V

0.1 V

Figure 13-5. Clock Timing Measurement at X

TCL

TIH

TIL

1/f

0.8 V

0.2 V

Figure 13-6. TCL Timing

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312MECHANICAL DATA

14-1

MECHANICAL DATA

OVERVIEW

The KS57C5204/C5208 microcontroller are available in a 42-pin SDIP package (42-SDIP-600), and a 44-pin QFP
package (44-QFP-1010B). The KS57C5304/C5308/C5312 microcontrollers are available in a 30-pin SDIP
package (30-SDIP-400) and a 32-pin SOP package (32-SOP-450A).

NOTE : Dimensions are in millimeters.

39.50 MAX

39.10

± 0.2

0.50 ±

0.1

1.778

(1.77)

0.51 MIN

3.30

± 0.3

3.50

0.2

5.08 MAX

42-SDIP-600

0-15

1.00 ±

0.1

0.25

+ 0.1

- 0.05

15.24

14.00

#42

#22

#21

Figure 14-1. 42-SDIP-600 Package Dimensions

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

KS57P5208/P5308/P5312 OTP

15-1

KS57P5208/P5308/P5312 OTP

OVERVIEW

The KS57P5208/P5308/P5312 single-chip CMOS microcontroller is the OTP (One Time Programmable)

version

of the KS57C5204/C5208/C5304/C5308/C5312 microcontroller. It has an on-chip EPROM instead of masked
ROM. The EPROM is accessed by a serial data format.

The KS57P5208/P5308/P5312 is fully compatible with the KS57C5208/C5308/C5312, both in function and in pin
configuration. Because of its simple programming requirements, the KS57P5208/P5308/P5312 is ideal for use as
an evaluation chip for the KS57C5208/C5308/C5312.

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4

P2.0/TCLO0
P2.1/TCLO1

P2.2/CLO

P2.3/BUZ

SDAT /P3.0/TCL0
SCLK /P3.1/TCL1

OUT

/TEST

P4.0/BTCO

P4.1

RESET

RESET

P3.2
P3.3
P4.2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

P9.2
P9.1
P9.0
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

KS57P5208

(42-SDIP-600)

Figure 15-1. KS57P5208 Pin Assignment Diagram (42-SDIP)

KS57P5208/P5308/P5312 OTP

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

15-2

DTMF

P9.0
P9.1
P9.2

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4

P2.0/TCLO0
P2.1/TCLO1

KS57P5208

(44-QFP-1010B)

P7.3/KS7

P7.2/KS6

P7.1/KS5

P7.0/KS4

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P5.3

P5.2

P5.1

P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
NC
P4.2
P3.3
P3.2

RESET/RESET

34
35
36
37
38
39
40
41
42
43
44

P2.2/CLO

P2.3/BUZ

SDAT

/P3.0/TCL0

SCLK

/P3.1/TCL1

OUT

/TEST

P4.0/BTCO

P4.1

22
21
20
19
18
17
16
15
14
13
12

Figure 15-2. KS57P5208 Pin Assignment Diagram (44-QFP)

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

KS57P5208/P5308/P5312 OTP

15-3

OUT

/TEST

P4.0/BTCO

P4.1

RESET/RESET

P4.2
P4.3
P5.0
P5.1
P5.2
P5.3

P6.0/KS0
P6.1/KS1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

P3.1/TCL1/SCLK
P3.0/TCL0/SDAT
P2.3/BUZ
P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0
P1.0/INT0
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

KS57P5308/P5312

(30-SDIP-400)

Figure 15-3. KS57P5308/P5312 Pin Assignment Diagram (30-SDIP)

OUT

/TEST

P4.0/BTCO

P4.1

RESET/RESET

P4.2

P4.3
P5.0
P5.1
P5.2
P5.3

P6.0/KS0
P6.1/KS1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

P3.1/TCL1/SCLK
P3.0/TCL0/SDAT
P2.3/BUZ
P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0
P1.0/INT0
NC
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

KS57P5308/P5312

(32-SOP-450A)

Figure 15-4. KS57P5308/P5312 Pin Assignment Diagram (32-SOP)

KS57P5208/P5308/P5312 OTP

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

15-4

Table 15-1. KS57P5208 Pin Descriptions Used to Read/Write the EPROM

Main Chip

During Programming

Pin Name

Pin No.

I/O

Function

P3.0

SDAT

9 (3)

I/O

Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.

P3.1

SCLK

10 (4)

I/O

Serial clock pin. Input only pin.

TEST

(TEST)

15 (9)

Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option) Hold GND when OPT is operating.

RESET

18 (12)

Chip initialization

/ V

11/12

(5/6)

Logic power supply pin. V

should be tied to +5

V during programming.

NOTE: Parentheses indicate pin numbers of 44 QFP package.

Table 15-2. KS57P5308/P5312 Pin Descriptions Used to Read/Write the EPROM

Main Chip

During Programming

Pin Name

Pin No.

I/O

Function

P3.0

SDAT

28 (30)

I/O

Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.

P3.1

SCLK

29 (31)

I/O

Serial clock pin. Input only pin.

TEST

(TEST)

4 (4)

RESET

7 (7)

Chip initialization

/ V

30/1

(32/1)

Logic power supply pin. V

should be tied to +5

V during programming.

NOTE: Parentheses indicate pin numbers of 32 SDIP package.

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

KS57P5208/P5308/P5312 OTP

15-5

Table 15-3. Comparison of KS57P5208 and KS57C5208 Features

Characteristic

KS57P5208

KS57C5208

Program Memory

8 K byte EPROM

8 K byte mask ROM

Operating Voltage (V

)

1.8 V (3 MHz) to 5.5 V

OTP Programming Mode

= 5 V, V

(TEST) = 12.5 V

Pin Configuration

42 SDIP / 44 QFP

EPROM Programmability

User Program 1 time

Programmed at the factory

Table 15-4. Comparison of KS57P5308/P5312 and KS57C5308/C5312 Features

Characteristic

KS57P5308/P5312

KS57C5308/C5312

Program Memory

8 K byte EPROM / 12 K (P5312)

8 K byte mask ROM / 12 K (C5312)

Operating Voltage (V

)

1.8 V (3 MHz) to 5.5 V

OTP Programming Mode

= 5 V, V

(TEST) = 12.5 V

Pin Configuration

30 SOP / 32 SOP

EPROM Programmability

User Program 1 time

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the Vpp(TEST) pin of the KS57P5208/P5308/P5312, the EPROM programming mode
is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the
pins listed in Table 15-3 below.

Table 15-5. Operating Mode Selection Criteria

Vpp

(TEST)

REG/

MEM

Address

(A15-A0)

Mode

5 V

0000H

EPROM read

12.5V

0000H

EPROM program

12.5V

0000H

EPROM verify

12.5V

0E3FH

EPROM read protection

NOTE: "0" means Low level; "1" means High level.

KS57P5208/P5308/P5312 OTP

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

15-6

OTP ELECTRICAL DATA

Table 15-6. Absolute Maximum Ratings

= 25

Parameter

Symbol

Conditions

Rating

Units

Supply Voltage

0.3 to + 6.5

Input Voltage

All I/O ports

0.3 to V

+ 0.3

Output Voltage

0.3 to V

+ 0.3

Output Current High

One I/O port active

All I/O ports active

Output Current Low

One I/O port active

+ 30 (Peak value)

+ 15

(note)

All I/O ports active

+ 100 (Peak value)

+ 60

(note)

Operating Temperature

40 to + 85

Storage Temperature

stg

65 to + 150

NOTE: The values for output current low ( I

) are calculated as peak value

Duty .

Table 15-7. D.C. Electrical Characteristics

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Input high
voltage

IH1

All input pins except those
specified below for V

IH2

IH3

0.7 V

IH2

Ports 1, 3, 6, 7, and

RESET

0.8 V

IH3

and X

OUT

0.1

Input low
voltage

IL1

All input pins except those
specified below for V

IL2

IL3

0.3 V

IL2

Ports 1, 3, 6, 7, and

RESET

0.2 V

IL3

and X

OUT

0.1

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

KS57P5208/P5308/P5312 OTP

15-7

Table 15-7. D.C. Electrical Characteristics (Continued)

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Output high
voltage

= 1 mA

Ports except 1

1.0

Output low
voltage

OL1

= 4.5 V to 5.5 V

= 15 mA, Ports 4 and 5 only

= 1.8 to 5.5 V, I

= 1.6mA

0.4

OL2

= 4.5 V to 5.5 V

= 4 mA, all out ports except 4,5

= 1.8 to 5.5 V, I

= 1.6mA

0.4

Input high
leakage current

LIH1

= V

All input pins except those specified
below

µA

LIH2

= V

and X

OUT

Input low
leakage current

LIL1

= 0

All input pins except below and

RESET

µA

LIL2

= 0 V

and X

OUT

only

Output high
leakage current

LOH

= V

All out pins

µA

Output low
leakage current

LOL

= 0 V

All out pins

µA

Pull-up resistor

= 5 V; V

= 0 V

except

RESET

100

= 3 V

200

= 5 V; V

= 0 V;

RESET

100

220

400

= 3 V

200

450

800

KS57P5208/P5308/P5312 OTP

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

15-8

Table 15-7. D.C. Electrical Characteristics (Concluded)

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Supply

current

(1)

DD1

(DTMF on)

Run mode; V

= 5 V

10%

(2)

3.58 MHz crystal oscillator,
C1 = C2 = 22 pF

2.5

5.0

= 3 V ± 10%

1.4

3.0

DD2

Run mode; V

= 5 V

10%

6.0 MHz

2.5

8.0

(DTMF off)

crystal oscillator, C1 = C2 = 22 pF

3.58 MHz

1.6

4.0

= 3 V ± 10%

6.0 MHz

1.2

4.0

3.58 MHz

0.7

2.3

DD3

Idle mode; = V

= 5 V

10%

6.0 MHz

0.7

2.5

crystal oscillator, C1 = C2 = 22 pF

3.58 MHz

0.6

1.8

= 3 V ± 10%

6.0 MHz

0.3

1.5

3.58 MHz

0.2

1.0

DD4

Stop mode; V

= 5 V ± 10%

0.01

µA

Stop mode; V

= 3 V ± 10%

0.01

Row tone level

ROW

= 2.0 V to 5.5 V

RL = 12 k

, Temp = 30

C to 60

16.0 14.0 11.0

dBV

Ratio of column
to row tone

= 2.0 V to 5.5 V

RL = 12 k

, Temp = 30

C to 60

Distortion
(Dual tone)

THD

= 2.0 V to 5.5 V

1MHz band; RL= 12 k

Temp = 30

C to 60

NOTES:
1.

D.C. electrical values for Supply Current (I

DD1

to I

DD3

) do not include current drawn through internal pull-up registers.

For D.C. electrical values, the power control register (PCON) must be set to 0011B.

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

KS57P5208/P5308/P5312 OTP

15-9

Table 15-8. Main System Clock Oscillator Characteristics

= 40

C + 85

C, V

= 1.8 V to 5.5 V)

Oscillator

Clock

Configuration

Parameter

Test Condition

Min

Typ

Max

Units

Ceramic
Oscillator

OUT

Oscillation frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

Stabilization time

(2)

= 3 V

Crystal
Oscillator

OUT

Oscillation frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

Stabilization time

(2)

= 3 V

External
Clock

OUT

input frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

input high and low

level width (t

, t

)

83.3

1250

NOTES:
1.

Oscillation frequency and X

input frequency data are for oscillator characteristics only.

Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.

KS57P5208/P5308/P5312 OTP

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

15-10

Table 15-9. Input/Output Capacitance

= 25

C, V

0 V )

Parameter

Symbol

Condition

Min

Typ

Max

Units

Input
Capacitance

f = 1 MHz; Unmeasured pins
are returned to V

Output
Capacitance

OUT

I/O Capacitance

Table 15-10. A.C. Electrical Characteristics

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Instruction Cycle
Time

= 2.7 V to 5.5 V

0.67

µs

= 1.8 V to 5.5 V

1.33

TCL0, TCL1 Input
Frequency

TI0

TI1

= 2.7 V to 5.5 V

1.5

MHz

= 1.8 V to 5.5V

MHz

TCL0, TCL1 Input
High, Low Width

TIH0

TIL0

TIH1

TIL1

= 2.7 V to 5.5 V

0.48

µs

= 1.8 V to 5.5 V

1.8

Interrupt Input
High, Low Width

INTH

, t

INTL

INT0, INT1, INT2, INT4,
KS0-KS7

µs

RESET

Input Low

Width

RSL

Input

µs

KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312

KS57P5208/P5308/P5312 OTP

15-11

1.5 MHz

CPU Clock

0.75 MHz

15.625 kHz

Main Oscillator Frequency
(Divided by 4)

3 MHz

6 MHz

Supply Voltage (V)

CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)

2.7

1.8

Figure 15-5. Standard Operating Voltage Range

Table 15-11. RAM Data Retention Supply Voltage in Stop Mode

= 40

C to + 85

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Data retention supply voltage

DDDR

1.8

5.5

Data retention supply current

DDDR

= 1.8 V

0.1

µA

Release signal set time

SREL

µs

Oscillator stabilization wait

WAIT

Released by

RESET

/fx

time

(1)

Released by interrupt

(2)

NOTES:
1.

During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.

Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: KS57P5312

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: KS57P5312