DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

80-QFP-1420C

DIGITAL SIGNAL PROCESSOR

The KS9286B is a CMOS integrated circuit designed for

the Digital Audio Signal Processor for Compact Disc

Player. It is a monolithic IC that builts-in 16-bit Digital

Analog Convertor, ESP Interface and Digital De-emphasis

additional conventional DSP function.

FEATURES

EFM data demodulation

Frame sync detection/protection/insertion

Powerful error correction (C1: 2error, C2: 4erasure)

Interpolation

8fs digital filter (51th+13th+9th)

Subcode data serial output

CLV servo controller

Micom interface

Digital audio output

Digital de-emphasis

ESP interface

Built-in 16K SRAM

Built-in Digital PLL

Double speed play available

Built-in 16-bit D/A converter

Operating Voltage range

ORDERING INFORMATION

Device

Package

Tempe. Range

KS9286B

80-QFP-1420C

-20

C ~ +75

KS9286B-L

KS9286B : 5V
KS9286B-L : 3.4V

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

BLOCK DIAGRAM

1
9
1
9

EFM
PHAS E
DETECTOR

DIG I TAL
PLL

CLV
SERVO

CPU
INTERFACE

MODE
SELECTOR

SUBCODE
SYNC
DETECTOR

23BI T
SHIFT
REG IS TER

FRAME SYNC
DETECTOR
PROTECTOR
INSE RTOR

X-TAL
TIMING
GENERATOR

TRACK
COUNTER

DIG I TAL
OUTPUT

SUBCODE
OUTPUT

EFM
DEMODULATOR

ADDRES S
GENERATOR

16K
SRAM

ECC

INTERPO LATOR

DIG I TAL
FILTER
& DE-EMPH

D/A
CONVE RTER

SUBCODE-Q
REG IS TER

5
3

4
2

75
76

37
38
36

69
68

I
T
D

A
B

EFMI

CNTVOL

DPFIN

DPFOUT

DPDO

SMEF

SMON

SMDP

SMDS

LOCK
XOUT

XIN

MDAT

MCK

MLT

TRCNT

/ISTAT

3
3

3
2

2
6

SQDT
SQCK

LRCHO

ADATAO

BCKO

BCKI

ADATAI

LRCHI

EMPH

VREFL1

VREFH1

6
5

6
3

6
2

6
1

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

PIN CONFIGURATION

61
60

58
57

56
55

54
53

51
50

48
47

46
45
44

42
41

4
5

6
7

11
12
13

14
15

20
21

22
23

2
5

2
6

2
7

2
8

2
9

3
0

3
1

3
2

3
3

3
4

3
5

3
6

3
7

3
8

3
9

4
0

SRAM

CDROM

FOK

XTALSEL

/CS

/WE

C16M

C4M

/JIT

ULKFS

FSDW

DVSS2

/PBCK

FLAG5

FLAG4

FLAG3

FLAG2

FLAG1

RD0

RD1

RD2

RD3

RD4

RD5

AVDDI

DPDO

DPFIN

DPFOUT

CNTVOL

AVSS1

DATX

XIN

XOUT

WDCHO

LRCHO

ADATAO

DVSS1

BCKO

C2PO

VREFL2

VREFL1

AVDD2

RCHOUT

LCHOUT

AVSS2

VREFH1

VREFH2

EMPH

/
I
S

/
E

KS9286B

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

PIN DESCRIPTION

PIN NO

SYMBOL

DESCRIPTION

AVDD1

Analog VCC1

DPDO

Charge pump output for Digital PLL

DPFIN

Filter input for Digital PLL

DPFOUT

Filter output for Digital PLL

CNTVOL

VCO control voltage for Digital PLL

AVSS1

Analog Ground1

DATX

Digital Audio output data

XIN

X'tal oscillator input

XOUT

X'tal oscillator output

WDCHO

Word clock output of 48bit/Slot (88.2KHz)

LRCHO

Channel clock output of 48 bit/Slot (44.1KHz)

ADATAO

Serial audio data output of 48 bit/Slot (MSB first)

DVSS1

Digital Ground1

BCKO

Audio data bit clock output of 48 bit/Slot (2.1168MHz)

C2PO

C2 Pointer for output audio data

VREFL2

Input terminal2 of reference voltage "L" (Floating)

VREFL1

Input terminal1 of reference voltage "L" (GND connection)

AVDD2

Analog VCC2

RCHOUT

Right-Channel audio output through D/A converter

LCHOUT

Left-Channel audio output through D/A converter

AVSS2

Analog ground2

VREFH1

Input terminal1 of reference voltage "H" (VDD connection)

VREFH2

Input terminal2 of reference voltage "H" (Floating)

EMPH

H: Emphasis ON, L: Emphasis OFF

LKFS

The Lock Status output of frame sync

S0S1

Output of subcode sync signal(S0+S1)

RESET

System reset at "L"

/ESP

ESP function ON/OFF control ("L": ESP function ON, "H": ESP function OFF)

SQCK

Clock for output Subcode-Q data

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

PIN DESCRIPTION (continued)

PIN NO

SYMBOL

DESCRIPTION

SQDT

Serial output of Subcode-Q data

SQOK

The CRC (Cycle Redundancy Check) check result signal output of Subcode-Q

SBCK

Clock for output subcode data

SDAT

Subcode serial data output

DVDD1

Digital VDD1

MUTE

Mute control input ("H": Mute ON)

MLT

Latch Signal Input from Micom (Schmit Trigger)

MDAT

Serial data input from Micom (Schmit Trigger)

MCK

Serial clock input from Micom (Schmit Trigger)

RD7

I/O

SRAM data I/O port 8 (MSB)

RD6

I/O

SRAM data I/O port 7

RD5

I/O

SRAM data I/O port 6

RD4

I/O

SRAM data I/O port 5

RD3

I/O

SRAM data I/O port 4

RD2

I/O

SRAM data I/O port 3

RD1

I/O

SRAM data I/O port 2

RD0

I/O

SRAM data I/O port 1 (LSB)

FLAG1

I/O

Monitoring output for error correction (RA0)

FLAG2

I/O

Monitoring output for error correction (RA1)

FLAG3

I/O

Monitoring output for error correction (RA2)

FLAG4

I/O

Monitoring output for error correction (RA3)

FLAG5

I/O

Monitoring output for error correction (RA4)

/PBCK

I/O

Output of VCO/2 (4.3218MHz) (RA5)

DVSS2

I/O

Digital ground 2

FSDW

I/O

Window or unprotected frame sync (RA6)

ULKFS

I/O

Frame sync protection state (RA7)

/JIT

I/O

Display of either RAM overflow or underflow for + 4 frame jitter margin (RA8)

C4M

I/O

Only monitoring signal (4.2336MHz) (RA9)

C16M

I/O

16.9344MHz signal output(RA10)

/WE

I/O

Terminal for test

/CS

I/O

Terminal for test

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

PIN NO

SYMBOL

DESCRIPTION

XTALSEL

Mode Selection1 (H: 33.8688MHz, L: 16.9344MHz)

FOK

SERVO FOK Signal input terminal

CDROM

Mode Selection2 (H: CD-ROM, L: CDP)

SRAM

TEST input terminal (GND connection)

TEST1

TEST input terminal (GND connection)

EFMI

EFM signal input

ADATAI

Serial audio data input of 48 bit/Slot (MSB first)

/ISTAT

The internal status output

TRCNT

Tracking counter input signal

LOCK

Output signal of LKFS condition sampled PBFR/16 (if LKFS is "H", LOCK is "H",
if LKFS is sampled "L" at least 8 times by PBFR/16, LOCK is "L".)

PBFR

Write frame clock (Lock: 7.35KHz)

SMEF

LPF time constant control of the spindle servo error signal

SMON

ON/OFF control signal for spindle servo

DVDD2

Digital VDD2

SMDP

Spindle Motor drive (Rough control in the SPEED mode, Phase control in the PHASE
mode)

SMDS

Spindle Motor drive (Velocity control in the PHASE mode)

BCKI

Audio data bit clock input of 48 bit/Slot (2.1168MHz)

TESTV

TEST input terminal (GND connection)

DSPEED

TEST input terminal (VDD connection)

LRCHI

Channel clock input of 48 bit/Slot (44.1KHz)

PIN DESCRIPTION (continued)

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Value

Unit

Supply Voltage

VDD

-0.3 ~ 7.0

Input Voltage

-0.3 ~ 7.0

Output Voltage

-0.3 ~ 7.0

Operating Temperature

TOPR

-20 ~ 75

Storage Temperature

TSTG

-40 ~ 125

ELECTRICAL CHARACTERISTIC

1. DC Characteristic

(Vcc=5V, Vss=0V, Ta=25

, unless otherwise specified)

Characteristic

Symbol

Test

Conditions

Min

Typ

Max

Unit

'H' INPUT VOLTAGE1

VIH(1)

(Note1)

0.7VDD

'L' INPUT VOLTAGE1

VIL(1)

(Note1)

0.3VDD

'H' INPUT VOLTAGE2

VIH(2)

(Note2)

0.8VDD

'L' INPUT VOLTAGE2

VIL(2)

(Note2)

0.2VDD

'H' OUTPUT VOLTAGE1

VOH(1)

IOH=-1mA (Note3)

VDD-0.5

VDD

'L' OUTPUT VOLTAGE1

VOL(1)

IOL=1mA (Note3)

0.4

'H' OUTPUT VOLTAGE2

VOH(2)

IOH=-1mA (Note4)

VDD-0.5

VDD

'L' OUTPUT VOLTAGE2

VOL(2)

IOL=2mA (Note4)

0.4

INPUT LEAK CURRENT

ILKG

VI=0~VDD (Note5)

-5

THREE STATE OUTPUT
LEAK CURRENT

IO(LKG)

VO=0~VDD (Note6)

-5

(Note1) Related pins : XTALSEL, TEST0, CDROM, SRAM, TEST1, EFMI, ADATAI, BCKI, DSPEED & LRCHI

(Note2) Related pins : All bi-direction pins & RESET, MLT, MCK, MDAT, MUTE, TRCNT

(Note3) Related pins : All output pins except (Note4) and OSCILATOR, DPFOUT

(Note4) Related pins : /ISTAT

(Note5) Related pins : XIN

(Note6) Related pins : SMEF, SMDP, SMDS & DPDO

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

2. AC CHARACTERISTIC

A. XIN (When the pulse is input)

(Vcc=5V, Vss=0V, Ta=25

, unless otherwise specified)

Characteristic

Symbol

Min

Typ

Max

UNIT

'H' LEVEL PULSE WIDTH

TWH

'L' LEVEL PULSE WIDTH

TWL

PULSE FREQUENCY

TCK

INPUT 'H' LEVEL

VIH

VDD-1.0

INPUT 'L' LEVEL

VIL

0.8

RISING & FALLING TIME

TR,TF

VIH

VIHx0.9

VIL*0.1

VIL

VDD/2

TWH

TWL

TCK

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

B. MCK, MDAT, MLT & TRCNT

(Vcc=5V, Vss=0V, Ta=25

, unless otherwise specified)

Characteristic

Symbol

Min

Typ

Max

Unit

CLOCK FREQUENCY

FCK1

MHz

CLOCK PULE WIDTH

300

SETUP TIME

TSU

300

HOLD TIME

300

DELAY TIME

300

LATCH PULSE WIDTH

TWCK1

300

TRCNT, SQCK FREQUENCY

FCK2

MHz

TRCNT, SQCK PULSE WIDTH

TWCK2

300

MCK

MDAT

MLT

TRCNT

SQCK

SQDAT

1/FCK1

TWCK1

TWCK2

1/FCK2

TSU

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

FUNCTION DESCRIPTION

1. Micom Interface

The data inputted from Micom is inputted to MDAT and transfered by MCK, and the inputted signal is loaded to

control register by means of MLT. The timing chart is as follows.

Fig.1. Micom data input timing chart

CONTROL

REGSTER

COMMENT

ADDRESS

D7~D4

DATA

/ISTAT

PIN

CNTL-Z

DATA CONTROL

ZCMT

NCLV

CRCQ

S0S1

CNTL-S

FRAME SYNC PROTECTION
ATTENUATION CONTROL

FSEM

FSEL

WSEL

ATTM

LKFS

CNTL-L

TRACKING COUNTER
LOWER 4 BITS

TRC3

TRC2

TRC1

TRC0

/COMPLETE

CNTL-U

TRACKING COUNTER
UPPER 4 BITS

TRC7

TRC6

TRC5

TRC4

/COUNT

CNTL-W

CLV CONTROL

GAIN

FOK

CNTL-C

CLV-MODE

CM3

CM2

CM1

CM0

/(Pw > 64)

CNTL-D

DOUBLE-SPEED

DS1

DS2

TRCNT

Table 1. Control register & data

MDAT

MCK

MLT

(9X ~ FX)

Valid

D7 <MSB>

(88XX, 8DXX)

MDAT

MCK

MLT

Valid

D15 <MSB>

D11

D12

D13

D14

¡ó

CONTROL

REGSTER

COMMENT

ADDRESS

D15~D8

DATA

/ISTAT

PIN

CNTL-F

FUNCTION
CONTROL

88XX

DEEM

ERA_

OFF

Hi-Z

CNTL-H

ESP,MONITOR
PIN CONTROL

8DXX

ESP_

DUMB

Hi-Z

* Send the 9X, AX, DX, FX command when output the S0S1, LKFS, FOK, TRCNT signal to /ISTAT pin
also just send MDAT, MCK except MLT

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

1) CNTL-Z REGISTER

It is a register to control zero cross mute of audio data, phase terminal

control, phase servo control and having or not of CRCF in data SQDT.

DATA = 0

DATA = 1

ZCMT

Zero cross mute is OFF

Zero cross mute is ON

NCLV

The phase servo is acted by frame sync

The phase servo is controlled by base
counter

CRCQ

SQDT outputs except for SQOK

SQDT=CRCF when S0S1='H'

Table 2. CNTL-Z register & data

2) CNTL-S REGISTER
It is a register to control frame sync protection and attenuation.

FSEM

FSEL

FRAME

WSEL

CLOCK

ATTM

MUTE

+ 3

+ 7

-12

Table 3. CNTL-S register & data

3) CNTL-L, U REGISTER

After the counter of track that must be counted is inputted from Micom, the data

is loaded to tracking counter by CNTL-L, U register.

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

4) CNTL-W REGISTER

It is a register to control CLV-Servo.

Table 4. CNTL-W register & data

5) CNTL-C REGISTER

It is a register to control CLV-Mode.

Table 5. CNTL-C register & data

6) CNTL-D REGISTER

It is a register to control normal speed mode and double speed mode.

Table 6. CNTL-D register & data

DATA=0

DATA=1

COMMENT

XTFR/32

XTFR/16

Bottom hold period control during speed or Hspeed-mode

XTFR/4

XTFR/2

Peak hold period control during speed-mode

GAIN

-12dB

0dB

SMDP gain control during speed or Hspeed-mode

MODE

D7~D4

D3~D0

SMDP

SMSD

SMEF

SMON

FORWARD

1110

1000

Hi-Z

REVERSE

1010

Hi-Z

SPEED

1110

SPEED-MODE

Hi-Z

HSPEED

1100

HSPEED-MODE

Hi-Z

PHASE

1111

PHASE-MODE

Hi-Z

XPHSP

0110

SPEED or PHASE-

MODE

Hi-Z or

PHASE-MODE

L, Hi-Z

VPHSP

0101

SPEED or PHASE-

MODE

Hi-Z or

PHASE-MODE

L, Hi-Z

STOP

0000

Hi-Z

MODE

D7~D4

D3~D0

COMMENT

NORMAL

1111

0000

Normal Speed

DOUBLE

0011

Double Speed

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

7) CNTL-F REGISTER
It is a register to control De-emphasis and ECC Erasure correction

Table 6. CNTL-F register & data

8) CNTL-H RESISTER
It isa resister to control ESP interface and Monitor pin

Note) Monitor pin : FLAG1 ~ FLAG5, /PBCK, FSDW, ULKFS, C16M, PBFR

Table 7. CNTL-H register & data

2. Tracking Counter Block

This block is used to improve the Track-jump characteristics.

The numbers of tracks that are to be jumped (inputted from Micom) are loaded into either register CNTL-L or

CNTL-U at the rising edge of MLT. When the address is set in CNTL-L, the signal /COMPLETE is output in /ISTAT

Pin, and when the address is set in CNTL-U, the signal /COUNT is output.

The following is timing chart of tracking counter block.

Fig.2. Tracking counter timing chart

Fig.3. /ISTAT output signal according to CNTL Register

DATA = 0

DATA = 1

DEEM

Internal De-emphasis Filter operation OFF

Internal De-emphasis Filter operation ON

ERA_OFF

ECC Erasure correction ON

ECC Erasure correction OFF

MLT

CNTL-L,U

TRCNT

/ISTAT

=(/count)

/ISTAT

=(/complete)

DATA = 0

DATA = 1

ESP_ON

ESP Interface Disable

ESP Interface Enable

DUMB

Monitor Pin Output Enable

Monitor Pin Output Disable

CNTL -L

CNTL -U

CNTL -C

/co mple te

/coun t

/(PW >64)

HI-Z

O the r Mo de

MDAT

ML T

CNTL

State

/ISTAT

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

3. EFM DEMODULATION BLOCK

The EFM block consists of EFM demodulator circuit which demodulates EFM data obtained from a disc, EFM

phase detector circuit and control signal generator circuit etc.

1) EFM Demodulator

The modulated 14-bit data is demodulated to 8-bit data through the demodulator circuit.

There are two kinds of demodulated data, one is subcode data and the other is audio data, and the subcode data

is inputted into subcode block and the audio data is written into built-in 16K SRAM and performed error correction.

2) Frame SYNC Detector, Protector and Inserter

A. Frame SYNC Detector

The data consists of frame unit, that is, it consists of frame SYNC, subcode data, audio data and redundancy data

etc.

The frame SYNC is detected in order to maintain the synchronization.

B. Frame SYNC Protector and Inserter

Occasionally, the frame sync is omitted or detected in the place where it does not exist by the effect of error or jit-

ter on a disc. In these case, it is need to protect or insert frame SYNC signal.

The window is made by using the WSEL of CNTL-S register to protect the frame SYNC, and it's width is deter-

mined by WSEL. If the frame SYNC is inputted to the window, it is true data and if it isn't inputted, it is ignored.

If the frame SYNC is not detected in the frame SYNC protection window, one is inserted from the internal counter

block.

When continuous inserting of frame SYNC, the appointed number of frame according to the FSEM and FSEL of

CNTL-S register is achieved, the ULKFS becomes "H" and the frame SYNC protection window is ignored. At that

time, the frame SYNC is received absolutely, the ULKFS signal becomes "L" and the frame SYNC in window is

received.

Table 8

LKFS

ULKFS

COMMENT

Corresponding with play back frame SYNC and generated frame SYNC

1) Out of corresponding with play back frame SYNC and generated frame SYNC, but PBFR SYNC is
detected in the window selected by WSEL.
2) Out of corresponding with PBFR SYNC and XTFR SYNC, the SYNC is inserted because it is'nt
detected in the window selected by WSEL.

1) After insertion as many as the frame decided by FSEM and FSEL of CNTL-S register as frame isn't
detected in the window.
2) In the case that the PBFR SYNC is not detected continually after 1)

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

4. SUBCODE BLOCK

The 14-bit subcode SYNC signal(that is S0,S1) is detected in the subcode SYNC block. After detection of S0

and passing through a frame, the S1 is detected.

The S0+S1 signal is outputted to S0S1 terminal, and the subcode data is outputted to SDAT terminal when the

S0S1 signal is "H".

The subcode data among the data inputted to EFMI terminal is demodulated to 8-bit subcode data

(P,Q,R,S,T,U,V,W). It is synchronized with PBFR signal and outputted to SDAT terminal by SBCK clock.

Among the eight subcode data, only Q data is selected and loaded to the eighty shift register by FBFR signal.

The result of checking the CRC (Cycle Redundancy Check) of loading data is synchronized with S0S1 rising

edge and outputted to SQOK terminal.

If the result of CRC checking is error, "L" is outputted to SQOK terminal, and if it is true, "H" is outputted to

SQOK terminal. In case of CRCQ of CNTL-Z register being "H", the result of CRC checking is outputted to

SQDT terminal during from S0S1 "H" to SQCK negative edge.

The following is the timing chart of subcode block

1) SQCK Using External Clock: S0S1, SQOK, SQCK, SQDT Timing Chart

Fig.4. Subcode-Q timing chart

When the CRCQ of CNTL-Z register is "H", SQOK signal is outputted to SQDT terminal according SQCK signal,

and when the CRCQ is "L", SQOK signal is not outputted to SQDT terminal.

Q2 Q1

Q6 Q5

Q12

Q80 Q79 Q78 Q77

Q1 Q8

Q6 Q5 Q12

Q80 Q79 Q78 Q77

SQOK(n +1)

SOS1

SQOK

SQCK

SQDT

CRCQ=0

SQDT

CRCQ=1

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

2) SDAT, SBCK TIMING CHART

a. After PBFR becomes falling edge, SBCK becomes "L" during about 10

b. If S0S1 is "L", subcode P is outputted, and if S0S1 is "H", S0S1 is outputted.

c. If the pulse inputted to the SBCK terminal is over seven, subcode data P, Q, R, S, T, U, V, W is repeated.

Fig.5. Timing chart of Subcode-Q data output

PBFR

SBCK

SDAT

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

5. ECC (Error Correction Code) Block

The function of ECC block is to recover damaged data to some extent when data on a disk is damaged.

By using CIRC (Cross-interleave Reed-Solomon Code), C1(32,28: 2 Error) and C2 (28,24: 4 Erasure) error are

corrected, and ECC is performed by the unit of one symbol of 8-bit.

In C1 correcting, a C1 pointer is generated, and in C2 correcting , a C2 pointer is generated. C1 & C2 pointer

send error information or the data which ECC gives.

The information signal is used to deal with the error data, and the process of error correction can monitored by

FLAG1, FLAG2, FLAG3, FLAG4, FLAG5 terminal.

Table 9. Error Correction monitoring flag

MODE

FLAG5

FLAG4

FLAG3

FLAG2

FLAG1

REMARK

C1 No error

C1 correction start

C1 1 error

C1 2 error

C1 Irretrirvable error

C1 pointer set

C2 No error

C2 correction start

C2 1 error

C2 2 error

C2 3 error

C2 4 error

C2 Irretrievable error 1

C1 pointer copy

C2 Irretrievable error 2

C2 pointer set

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

6. INTERPOLATOR / MUTE BLOCK

1) Interpolator

When a burst error occurs on a disc, sometimes the data can't be corrected even if the ECC process is performed.

The interpolator block revises the data by using a C2 pointer outputted through the ECC block.

The data inputted to a data bus is inputted to the left and right channel respectively, in the order of C2 pointer,

lower 8-bit and upper 8-bit.

In case of C2PO being "H" and the occurrence of a single error, an average interpolation method is carried out

with the range of the data before and after an error happens. A pre-hold method is taken when the C2 pointer is "H"

and 3 errors occur continuously.

When a check against a checked cycle LRCH is "L", R-ch data is outputted, and L-ch data is outputted when the

check is "H".

The following is timing chart of interpolator block.

B = ( A + C ) / 2: Average Interpolation
F = E = D: Previous Data Hold
G = (F + H ) / 2: Average Interpolation

Fig.6. Interpolation

pointer

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

2) MUTE AND ATTENUATION

By using a mute terminal and the ATTM signal of the CNTL-S register, the audio data is muted or attenuated.

A. Zero Cross Muting
The audio data is muted, after ZCMT of CNTL-S register goes to "H", and in case that mute is "H" and the upper 6
bits of audio data become all "L" or "H".

B. Muting
The audio data is muted when the ZCMT of CNTL-S rgister is "L" and MUTE terminal is "H".

C. Attenuation
The signal attenuation is occured by ATTM of CNTL-S register and MUTE signal as following.

Table 10.

ATTM

MUTE

Degree of Attenuation

0dB

- dB

-12dB

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

8. DIGITAL AUDIO OUTPUT BLOCK

The 2-channel, 16-bit data is connected and outputted serially to other digital
system by the digital audio interface format.

1) Digital Audio Interface Format for CD

0L : L-ch format including block sync preamble
1L ~ 191L : L-ch format including L-ch sync preamble
0R ~ 191R : R-ch format including R-ch sync preamble

Fig.9. Digital audio output format

A. Preamble
It is used to discriminated against the block sync of data and L/R-channel of data.
Fig.10. Preamble Signal

Fig.10. Preamble Signal

191R

........

190L

190R

191L

191R

192T

L-ch

R-ch

Preamble

Modulated '0' 8-bit

Modulated 16-bit audio data

1LRCH

Control signal

8.4672MHz

L-ch sync (Except for Block Sync)

R-ch sync

Block sync(L-ch)

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

B. CONTROL SIGNAL

1) Validity Bit: It is indicated that the error of 16-bit audio data exists, or doesn't. ("H": Error, "L": Valid data)

2) User Definable Bit: Subcode data output.

Fig.11. Timing chart of digital audio output

3) Channel Status Bit: Output a high position information of 4-bit of Subcode-Q indicating the

number of channel, pre-emphasis and copy etc. Indicates the CDP category.

Fig.12. Timing chart of channel status data output

4) Parity Bit: Making even parity.

2) Timing Chart of Digital Audio Data Output

48 bits/slot

Fig.13. Timing chart of audio data output

sync pattern

Q R S T U V W

S0S1

PBFR

SBCK

SBDT

S0S1

SQDT

PBFR

ID0 ID1 COP Y EMPH

15 14 13 12 11

8 7 6

5 4

3 2

15 14 13 12 11

8 7 6

5 4 3

2 1

L-ch (MSB )

R-ch (MSB )

LRCH

(44.1KHz)

BCK

(2.12MHz)

WDCH

(88.2KHz)

ADATA

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

9. CLV SERVO BLOCK

The CNTL-C register is selected to control CLV (Constant Linear Velocity) servo by the data inputted from Micom.

In the CNTL-C register, the CLV servo action mode is appointed by the data inputted from Micom to control the

spindle motor.

1) Forward

It is a mode of spindle motor rotates in forward direction. Output condition in forward mode is as following.

Table 11.

2) Reverse

It is a mode of spindle motor rotates in reverse direction. Output condition in reverse mode is as following.

Table 12.

3) Speed-Mode

The spindle motor is controlled roughly by speed mode when track jumping or EFM phase is unlocked.

If a period of VCO is "T", the pulse width of frame sync is 22T. In case that the signal detected from EFM signal

exceeds 22T by noise on the disc and etc., it must be removed, if not, the right frame sync can't be detected. In

this case, the pulse width of EFM signal is detected by peak hold clock and bottom hold clock. ( Peak hold clock is

XTFR/2 or XTFR/4, and bottom hold clock is XTFR/16 or XTFR/32.)

The detected value is used for synchronized frame signal. If the frame signal is less than 21T, the SMDP termi-

nal outputs "L", eaqul to 22T, outputs "Hi-Z", and more than 23T, ouputs "H".

If the gain signal of CNTL-W register is "L", the output of SMDP terminal is reduced up to -12dB, if it is "H", there

is no reduction.

Output condition: SMSD="Hi-Z", SMEF="L", SMON="H".

SMDP

SMSD

SMEF

SMON

Hi-Z

SMDP

SMSD

SMEF

SMON

Hi-Z

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

4) Hspeed-Mode

The rough servo mode, which moves 20,000 tracks in high speed acts between the inside and outside of the CD.

The mirror domain of track which hasn't pit is duplicated with 20KHz signal to EFM. In this case, servo action is

unstable because the peak value of mirror signal which is longer than orignal frame sync signal which is detected. In

Hspeed mode, by using the 8.4672/256MHz signal against peak hold and XTFR/16 or XTFR/32 signal against bot-

tom hold, the mirror component is removed, and Hspeed servo action to be stable.

The output condition is as following.

Table 13.

5) Phase-Mode

The phase mode is the mode to control the EFM phase. Phase difference between PBFR/4 and XTFR/4 is

detected when NCLV of CNTL-Z register is "L",and phase difference between Read Base Counter/4 and Write Base

Counter/4 detected when NCLV is "H", and the difference is outputted to SMDP(Fig.14).

If the cycle of VCO/2 signal is put as "T" and it is put as "/WP" during a "H" period of PBFR, it outputs "H" to

SMSD terminal from the falling edge of PBFR to the (/WP-278T) x 32, and then, outputs "L" to the falling edge of the

next PBFR (Fig.15).

6) XPHSP-Mode

The XPHSP mode is the mode used in normal operation.

The LKFS signal made from frame sync block is to sampling which period is PBFR/ 16. If the sampling is "H", the

Phase mode is performed, and if the sampling is eight of "L" continously, Speed-mode is performed automatically.

The selection of peak hold period in Speed-mode and selection of bottom hold period and gain in Speed/ Hspeed-

mode is determined by CNTL-W register.

7) VPHSP-Mode

The VPHSP mode is the mode used for rough servo control. It uses VCO instead of X-tal in the EFM pattern test.

When the range of VCO center changes, VCO is easily locked because the rotation of a spindle motor changes in

the same direction.

SMDP

SMSD

SMEF

SMON

Hi-Z

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

8) Stop-Mode
The stop mode is used to stop the spindle motor.
The output condition is as following.

Table 14

Fig.14. Timing chart of SMDP output

(A) Timing chart of SMSD when PBFR is 278T

(B) Timing chart of SMSD when PBFR is 294T

Fig.15. Timing chart of SMSD output in phase mode

SMDP

SMSD

SMEF

SMON

Hi-Z

XTFR/4;

(XTFR/8)

PBFR/4;

(PBFR/8)

SMDP

287T

288T

PBFR

SMSD

294T

512T

PBFR

SMSD

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

10. DIGITAL PLL

This device contains Digital PLL in order to obtain the stable channel clock for demodulating EFM signal.

The block diagram of Digital PLL is as follows.

Fig.17. Digital PLL circuit diagram

11. D/A Converter (Digital to Analog Converter)

The KS9286B has a built-in 16-bit D/A converter. Digital audio data is a 2's complement serial format (MSB sirst),

PHASE

COMPARATO

LOW PASS

FILTER

VOLTAGE

CONTROLED

OSCILATOR

1/N

DIVIDER

DIGITAL MAIN

PLL

X'tal

/PBCK

EFMI

Frequency Synthesizer

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

1) Vref Terminal

Vref, the reference voltage across a resister-ladder, is usually recommended with VrefH1=5V, VrefL1=0V.

One way of avoiding an amplitude mismatching between the Vref and OP AMP input connected to the output of D/

A converter is to reduce the analog output amplitude with VrefH2=5V and VrefL2=0V (At this time about 100uF

capacitor should be connected from VreH1 and VrefL1 to GND). By the effect of built-in RH and RL with this

choice, the maximum analog output amplitude result in a narrow range of about 1.5 ~ 3.5V for 0dB playback.

Fig.18. Vref relation circuit

2) D/A Converter Electrical Characteristic
The D/A Converter electrical characteristic built in KS9286B is as follows.

(VDD=5V, VSS=0V, Ta=25

Table 15

Voltage

Dividing

D/A converter

Analog

MUX

Control
Circuit

D3 ~ D0,

D15 ~ D7

VREFH1

VREFH2

RCHOUT

LCHOUT

D6 ~ D4

VREFL1

VREFL2

Characteristics

Symbol

Test Conditon

MIN

TYP

MAX

Unit

Total Harmonic Distortion

THD

Data=1kHz, 0dB

0.08

Signal to Noise Ratio

S/N

VDD=4.5V

Data=1kHz, 0dB

Cross-Talk

Data=1kHz, 0dB

-85

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

12. Digital De-Emphasis

The Emphasis/De-Emphasis circuit is used for improving S/N ration by decreasing high frequency noise in case of

the frequency characteristic of signal not being changed.

The digital de-emphasis circuit, which can de-emphasise the signal emphasised on disc, is built-in KS9286B, and

the frequency characteristic is as follows.

Table 16. Frequency characteristic of de-emphasis circuit

Frequency

Characteristic

1KHz

-0.51dB

5KHz

-4.5dB

10KHz

-7.59dB

20KHz

-9.5dB

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

13. ESP INTERFACE BLOCK

1) Introduction

Because the location of normal table CD Player used in family is fixed, it is possible to play music stabilitable when

the degree of damage on disc is in limit range.

But in now, it is general that user can hear music when moving by Walkman-CD Player. In this case, if user has

been shocked suddenly, it often happens that music playing is unstable.

On this, the ESP interface block is added to KS9286B for realizing the function of Anti-shock.

The application circuit of using NPC anti-shock memory controller IC SM5859AF and KS9286B is as follows.

Fig.19. ESP interface application

M ic r o -

c on t r o l l e r

1 6K S RA M

E FM º¹Á¶

E CC

S UB - Q º¹Á¶

C LV - S e r v o

I NT E R P O L A T I O N

D ig i t a l F il t e r

D ig i t a l d e-

e mp h a s i s

D /A C on v e r t e r

P ar t A

P ar t B

YMDATA

YMCLK

YMLD

ZSENSE

SM5859

YBLKCK

YFLSG

YFCLK

YLRCK

YSCK

YSRDATA

S0S1

/JIT

VSS

LRCKO

BCKO

ADATAO

LRCKI

BCKI

ADATAI

ZLRCK

ZSCK

ZSRDATA

KS9286B

/RAS

/WE

A0 to A10

D0 to D3

/CAS

/OE

/RAS

/WE

A0 to A10

D0 to D3

NCAS

VSS

DRAM

/ESP

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

The operation of KS9286B is different when normal operation and forming anti- shock function with external ESP

IC. From Fig.19, the operation of part B composed by Digital Filter, Digital de-emphasis and 16-bit D/A Converter in

KS9286B and part A except part B is separated. When anti-shock function is used in case of /ESP Pin being "L",

part A block operates in double speed and part B block operates in normal speed. That is, after EFM Demodula-

tion, Error Correction and Interpolation block operation in double speed, audio data is inputted to ESP IC which is

the anti-shock memory controller. Audio data received by ESP IC is saved in external memory and then inputted

to KS9286B. In part B of KS9286B, the data is dealed with in normal speed and then outputted .

The anti-shock function is not used in case of /ESP terminal being "H".

2) Timing Chart

The interface timing diagram of ESP IC is as follows

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

Fig.20. Timing chart of signal outputting to ESP IC

Fig.21. Timing chart of signal ESP IC outputting to DSP

LRCHO

BCKO

ADATAO

D15

D14 D13 D12 D11 D10 D9 D8

D7 D6

D5 D4 D3 D2 D1 D0

D15

D14 D13 D12 D11

D1 D0

88.2Khz

D14 D13 D12 D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

LRCHI

BCKI

ADATAI

D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15

D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15

D14 D13 D12 D

D1 D0

44.1Khz

DIGITAL SIGNAL PROCESSOR for CDP

KS9286B/KS9286B-L

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Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: KS9286

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: KS9286